Change-Id: I9fb6700085d817d35a691f6484193f67939a4e0f Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4933 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>master
@@ -6869,7 +6869,7 @@ The @var{num} parameter is a value shown by @command{flash banks}. | |||
@end deffn | |||
@deffn {Flash Driver} stm32l4x | |||
All members of the STM32L4 microcontroller families from STMicroelectronics | |||
All members of the STM32L4 and STM32WB microcontroller families from STMicroelectronics | |||
include internal flash and use ARM Cortex-M4 cores. | |||
The driver automatically recognizes a number of these chips using | |||
the chip identification register, and autoconfigures itself. | |||
@@ -6911,7 +6911,9 @@ is the register offset of the Option byte to read. | |||
For example to read the FLASH_OPTR register: | |||
@example | |||
stm32l4x option_read 0 0x20 | |||
# Option Register: <0x40022020> = 0xffeff8aa | |||
# Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa | |||
# Option Register (for STM32WBx): <0x58004020> = ... | |||
# The correct flash base address will be used automatically | |||
@end example | |||
The above example will read out the FLASH_OPTR register which contains the RDP | |||
@@ -169,6 +169,10 @@ static const struct stm32l4_rev stm32_470_revs[] = { | |||
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" }, | |||
}; | |||
static const struct stm32l4_rev stm32_495_revs[] = { | |||
{ 0x2001, "2.1" }, | |||
}; | |||
static const struct stm32l4_part_info stm32l4_parts[] = { | |||
{ | |||
.id = 0x415, | |||
@@ -230,6 +234,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = { | |||
.flash_regs_base = 0x40022000, | |||
.fsize_addr = 0x1FFF75E0, | |||
}, | |||
{ | |||
.id = 0x495, | |||
.revs = stm32_495_revs, | |||
.num_revs = ARRAY_SIZE(stm32_495_revs), | |||
.device_str = "STM32WB5x", | |||
.max_flash_size_kb = 1024, | |||
.has_dual_bank = false, | |||
.flash_regs_base = 0x58004000, | |||
.fsize_addr = 0x1FFF75E0, | |||
}, | |||
}; | |||
/* flash bank stm32l4x <base> <size> 0 0 <target#> */ | |||
@@ -714,7 +728,7 @@ static int stm32l4_probe(struct flash_bank *bank) | |||
} | |||
if (!stm32l4_info->part_info) { | |||
LOG_WARNING("Cannot identify target as an STM32L4 family device."); | |||
LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device."); | |||
return ERROR_FAIL; | |||
} | |||
@@ -804,6 +818,12 @@ static int stm32l4_probe(struct flash_bank *bank) | |||
stm32l4_info->bank1_sectors = num_pages / 2; | |||
} | |||
break; | |||
case 0x495: | |||
/* single bank flash */ | |||
page_size = 4096; | |||
num_pages = flash_size_in_kb / 4; | |||
stm32l4_info->bank1_sectors = num_pages; | |||
break; | |||
default: | |||
LOG_ERROR("unsupported device"); | |||
return ERROR_FAIL; | |||
@@ -881,7 +901,7 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size) | |||
part_info->device_str, rev_id); | |||
return ERROR_OK; | |||
} else { | |||
snprintf(buf, buf_size, "Cannot identify target as a STM32L4x device"); | |||
snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device"); | |||
return ERROR_FAIL; | |||
} | |||
@@ -0,0 +1,103 @@ | |||
# script for stm32wbx family | |||
# | |||
# stm32wb devices support both JTAG and SWD transports. | |||
# | |||
source [find target/swj-dp.tcl] | |||
source [find mem_helper.tcl] | |||
if { [info exists CHIPNAME] } { | |||
set _CHIPNAME $CHIPNAME | |||
} else { | |||
set _CHIPNAME stm32wbx | |||
} | |||
set _ENDIAN little | |||
# Work-area is a space in RAM used for flash programming | |||
# By default use 64kB | |||
if { [info exists WORKAREASIZE] } { | |||
set _WORKAREASIZE $WORKAREASIZE | |||
} else { | |||
set _WORKAREASIZE 0x10000 | |||
} | |||
#jtag scan chain | |||
if { [info exists CPUTAPID] } { | |||
set _CPUTAPID $CPUTAPID | |||
} else { | |||
if { [using_jtag] } { | |||
set _CPUTAPID 0x6ba00477 | |||
} else { | |||
# SWD IDCODE (single drop, arm) | |||
set _CPUTAPID 0x6ba02477 | |||
} | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
set _FLASHNAME $_CHIPNAME.flash | |||
flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME | |||
# Common knowledges tells JTAG speed should be <= F_CPU/6. | |||
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on | |||
# the safe side. | |||
# | |||
# Note that there is a pretty wide band where things are | |||
# more or less stable, see http://openocd.zylin.com/#/c/3366/ | |||
adapter_khz 500 | |||
adapter_nsrst_delay 100 | |||
if {[using_jtag]} { | |||
jtag_ntrst_delay 100 | |||
} | |||
reset_config srst_nogate | |||
if {![using_hla]} { | |||
# if srst is not fitted use SYSRESETREQ to | |||
# perform a soft reset | |||
cortex_m reset_config sysresetreq | |||
} | |||
$_TARGETNAME configure -event reset-init { | |||
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz. | |||
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1. | |||
# 2 WS compliant with VOS=Range1 and 24 MHz. | |||
mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency) | |||
mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz | |||
# Boost JTAG frequency | |||
adapter_khz 4000 | |||
} | |||
$_TARGETNAME configure -event reset-start { | |||
# Reset clock is MSI (4 MHz) | |||
adapter_khz 500 | |||
} | |||
$_TARGETNAME configure -event examine-end { | |||
# Enable debug during low power modes (uses more power) | |||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP | |||
mmw 0xE0042004 0x00000007 0 | |||
# Stop watchdog counters during halt | |||
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP | |||
mmw 0xE004203C 0x00001800 0 | |||
} | |||
$_TARGETNAME configure -event trace-config { | |||
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync | |||
# change this value accordingly to configure trace pins | |||
# assignment | |||
mmw 0xE0042004 0x00000020 0 | |||
} |