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cfg: refactor lpc1xxx targets onto one base config 

Since now auto-detection for flash size works nicely, there's no
reason to keep numerous configs around.

Change-Id: If0cbc37985abf17ef7c1f7d0688e76500fac228f
Signed-off-by: Vanya Sergeev <vsergeev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1960
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
tags/v0.9.0-rc1
Vanya Sergeev 10 years ago
committed by Andreas Fritiofson
parent
1e439e2a9a
commit
b5a6ba46aa
21 changed files with 185 additions and 436 deletions
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  1. +2
    -5
      tcl/board/mbed-lpc11u24.cfg
  2. +0
    -50
      tcl/target/lpc11uxx.cfg
  3. +8
    -0
      tcl/target/lpc11xx.cfg
  4. +8
    -0
      tcl/target/lpc12xx.cfg
  5. +8
    -0
      tcl/target/lpc13xx.cfg
  6. +0
    -21
      tcl/target/lpc1751.cfg
  7. +0
    -21
      tcl/target/lpc1752.cfg
  8. +0
    -21
      tcl/target/lpc1754.cfg
  9. +0
    -21
      tcl/target/lpc1756.cfg
  10. +0
    -21
      tcl/target/lpc1758.cfg
  11. +0
    -21
      tcl/target/lpc1759.cfg
  12. +0
    -21
      tcl/target/lpc1763.cfg
  13. +0
    -21
      tcl/target/lpc1764.cfg
  14. +0
    -21
      tcl/target/lpc1765.cfg
  15. +0
    -21
      tcl/target/lpc1766.cfg
  16. +0
    -21
      tcl/target/lpc1767.cfg
  17. +0
    -17
      tcl/target/lpc1768.cfg
  18. +0
    -17
      tcl/target/lpc1769.cfg
  19. +0
    -17
      tcl/target/lpc1788.cfg
  20. +6
    -99
      tcl/target/lpc17xx.cfg
  21. +153
    -0
      tcl/target/lpc1xxx.cfg

+ 2
- 5
tcl/board/mbed-lpc11u24.cfg View File

@@ -4,10 +4,7 @@

source [find interface/cmsis-dap.cfg]

# increase working area to 8KB
# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM
set WORKAREASIZE 0x2000

# chip name
set CHIPNAME lpc11u24

source [find target/lpc11uxx.cfg]
source [find target/lpc11xx.cfg]

+ 0
- 50
tcl/target/lpc11uxx.cfg View File

@@ -1,50 +0,0 @@
#
# NXP lpc11uxx family

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc11uxx
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1800
}

if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x00000000
}

# delays on reset lines
adapter_nsrst_delay 100
#jtag_ntrst_delay 100

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

#set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME lpc2000 0 0 0 0 $_TARGETNAME

if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

+ 8
- 0
tcl/target/lpc11xx.cfg View File

@@ -0,0 +1,8 @@
# NXP LPC11xx Cortex-M0 with at least 1kB SRAM
set CHIPNAME lpc11xx
set CHIPSERIES lpc1100
if { ![info exists WORKAREASIZE] } {
set WORKAREASIZE 0x400
}

source [find target/lpc1xxx.cfg]

+ 8
- 0
tcl/target/lpc12xx.cfg View File

@@ -0,0 +1,8 @@
# NXP LPC12xx Cortex-M0 with at least 4kB SRAM
set CHIPNAME lpc12xx
set CHIPSERIES lpc1200
if { ![info exists WORKAREASIZE] } {
set WORKAREASIZE 0x1000
}

source [find target/lpc1xxx.cfg]

+ 8
- 0
tcl/target/lpc13xx.cfg View File

@@ -0,0 +1,8 @@
# NXP LPC13xx Cortex-M3 with at least 4kB SRAM
set CHIPNAME lpc13xx
set CHIPSERIES lpc1300
if { ![info exists WORKAREASIZE] } {
set WORKAREASIZE 0x1000
}

source [find target/lpc1xxx.cfg]

+ 0
- 21
tcl/target/lpc1751.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM,
set CHIPNAME lpc1751
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x2000
set CPUROMSIZE 0x8000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1752.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM,
set CHIPNAME lpc1752
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x10000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1754.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1754
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x20000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1756.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1756
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1758.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1758
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1759.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1759
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1763.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1763
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1764.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1764
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x20000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1765.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM,
set CHIPNAME lpc1765
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1766.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1766
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 21
tcl/target/lpc1767.cfg View File

@@ -1,21 +0,0 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1767
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 17
tcl/target/lpc1768.cfg View File

@@ -1,17 +0,0 @@
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1768
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 17
tcl/target/lpc1769.cfg View File

@@ -1,17 +0,0 @@
# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1769
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 0
- 17
tcl/target/lpc1788.cfg View File

@@ -1,17 +0,0 @@
# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
set CHIPNAME lpc1788
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x10000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000

#Include the main configuration file.
source [find target/lpc17xx.cfg]

+ 6
- 99
tcl/target/lpc17xx.cfg View File

@@ -1,101 +1,8 @@
# Main file for NXP LPC17xx Cortex-M3
#
# !!!!!!
#
# This file should not be included directly, rather
# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
# needed variables to the appropriate values.
#
# !!!!!!

# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}

if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
set CHIPNAME lpc17xx
set CHIPSERIES lpc1700
if { ![info exists WORKAREASIZE] } {
set WORKAREASIZE 0x2000
}

if { [info exists CPURAMSIZE] } {
set _CPURAMSIZE $CPURAMSIZE
} else {
error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
set _CPUROMSIZE $CPUROMSIZE
} else {
error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME

# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 10

# delays on reset lines
adapter_nsrst_delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}

$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

mww 0x400FC040 0x01
}

if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
source [find target/lpc1xxx.cfg]

+ 153
- 0
tcl/target/lpc1xxx.cfg View File

@@ -0,0 +1,153 @@
# Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts
#
# !!!!!!
#
# This file should not be included directly, rather by the lpc11xx.cfg,
# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
# appropriate values.
#
# !!!!!!

# LPC11xx chips support only SWD transport.
# LPC12xx chips support only SWD transport.
# LPC11Uxx chips support both JTAG and SWD transports.
# LPC13xx chips support both JTAG and SWD transports.
# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
}

if { [info exists CHIPSERIES] } {
# Validate chip series is supported
if { $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" } {
error "Unsupported LPC1xxx chip series specified."
}
set _CHIPSERIES $CHIPSERIES
} else {
error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
}

# After reset, the chip is clocked by an internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
# Allow user override
set _CCLK $CCLK
} else {
# LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one
if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
set _CCLK 12000
} elseif { $_CHIPSERIES == "lpc1700" } {
set _CCLK 4000
}
}

if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
# LPC11xx/LPC12xx uses a Cortex M0 core, LPC13xx/LPC17xx use a Cortex M3 core
if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
set _CPUTAPID 0x0bb11477
} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" } {
if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
}

if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
}

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME

# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE

# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
#
# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
# (same cmd51 destination boundary alignment, and all three support 256 byte
# transfers).
#
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
auto $_CCLK calc_checksum

if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
# Bit Symbol Value Description
# 1:0 MAP System memory remap
# 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
# 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
# 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
# 31:2 - - Reserved.
$_TARGETNAME configure -event reset-init {
mww 0x40048000 0x02
}
} elseif { $_CHIPSERIES == "lpc1700" } {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
$_TARGETNAME configure -event reset-init {
mww 0x400FC040 0x01
}
}

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 10

# delays on reset lines
adapter_nsrst_delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}

# LPC11xx/LPC12xx (Cortex M0 core) supports SYSRESETREQ
# LPC13xx/LPC17xx (Cortex M3 core) supports SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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