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@@ -1563,6 +1563,17 @@ read/write memory on your target, @command{init} must occur before |
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the memory read/write commands. This includes @command{nand probe}. |
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@end deffn |
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@deffn {Overridable Procedure} jtag_init |
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This is invoked at server startup to verify that it can talk |
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to the scan chain (list of TAPs) which has been configured. |
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The default implementation first tries @command{jtag arp_init}, |
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which uses only a lightweight JTAG reset before examining the |
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scan chain. |
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If that fails, it tries again, using a harder reset |
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from the overridable procedure @command{init_reset}. |
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@end deffn |
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@anchor{TCP/IP Ports} |
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@section TCP/IP Ports |
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@cindex TCP port |
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@@ -2192,8 +2203,9 @@ issues (not limited to errata). |
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For example, certain JTAG commands might need to be issued while |
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the system as a whole is in a reset state (SRST active) |
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but the JTAG scan chain is usable (TRST inactive). |
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(@xref{JTAG Commands}, where the @command{jtag_reset} |
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command is presented.) |
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Many systems treat combined assertion of SRST and TRST as a |
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trigger for a harder reset than SRST alone. |
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Such custom reset handling is discussed later in this chapter. |
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@end itemize |
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There can also be other issues. |
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@@ -2260,7 +2272,7 @@ Possible values are @option{none} (the default), @option{trst_only}, |
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@quotation Tip |
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If your board provides SRST and/or TRST through the JTAG connector, |
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you must declare that or else those signals will not be used. |
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you must declare that so those signals can be used. |
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@end quotation |
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@item |
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@@ -2309,6 +2321,81 @@ powerup and pressing a reset button. |
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@end itemize |
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@end deffn |
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@section Custom Reset Handling |
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OpenOCD has several ways to help support the various reset |
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mechanisms provided by chip and board vendors. |
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The commands shown in the previous section give standard parameters. |
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There are also @emph{event handlers} associated with TAPs or Targets. |
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Those handlers are Tcl procedures you can provide, which are invoked |
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at particular points in the reset sequence. |
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After configuring those mechanisms, you might still |
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find your board doesn't start up or reset correctly. |
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For example, maybe it needs a slightly different sequence |
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of SRST and/or TRST manipulations, because of quirks that |
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the @command{reset_config} mechanism doesn't address; |
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or asserting both might trigger a stronger reset, which |
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needs special attention. |
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Experiment with lower level operations, such as @command{jtag_reset} |
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and the @command{jtag arp_*} operations shown here, |
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to find a sequence of operations that works. |
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@xref{JTAG Commands}. |
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When you find a working sequence, it can be used to override |
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@command{jtag_init}, which fires during OpenOCD startup |
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(@pxref{Configuration Stage}); |
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or @command{init_reset}, which fires during reset processing. |
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You might also want to provide some project-specific reset |
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schemes. For example, on a multi-target board the standard |
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@command{reset} command would reset all targets, but you |
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may need the ability to reset only one target at time and |
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thus want to avoid using the board-wide SRST signal. |
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@deffn {Overridable Procedure} init_reset mode |
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This is invoked near the beginning of the @command{reset} command, |
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usually to provide as much of a cold (power-up) reset as practical. |
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By default it is also invoked from @command{jtag_init} if |
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the scan chain does not respond to pure JTAG operations. |
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The @var{mode} parameter is the parameter given to the |
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low level reset command (@option{halt}, |
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@option{init}, or @option{run}), @option{setup}, |
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or potentially some other value. |
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The default implementation just invokes @command{jtag arp_init-reset}. |
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Replacements will normally build on low level JTAG |
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operations such as @command{jtag_reset}. |
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Operations here must not address individual TAPs |
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(or their associated targets) |
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until the JTAG scan chain has first been verified to work. |
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Implementations must have verified the JTAG scan chain before |
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they return. |
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This is done by calling @command{jtag arp_init} |
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(or @command{jtag arp_init-reset}). |
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@end deffn |
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@deffn Command {jtag arp_init} |
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This validates the scan chain using just the four |
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standard JTAG signals (TMS, TCK, TDI, TDO). |
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It starts by issuing a JTAG-only reset. |
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Then it performs checks to verify that the scan chain configuration |
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matches the TAPs it can observe. |
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Those checks include checking IDCODE values for each active TAP, |
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and verifying the length of their instruction registers using |
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TAP @code{-ircapture} and @code{-irmask} values. |
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If these tests all pass, TAP @code{setup} events are |
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issued to all TAPs with handlers for that event. |
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@end deffn |
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@deffn Command {jtag arp_init-reset} |
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This uses TRST and SRST to try resetting |
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everything on the JTAG scan chain |
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(and anything else connected to SRST). |
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It then invokes the logic of @command{jtag arp_init}. |
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@end deffn |
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@node TAP Declaration |
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@chapter TAP Declaration |
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@@ -2540,9 +2627,6 @@ there seems to be no problems with JTAG scan chain operations. |
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@section Other TAP commands |
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@c @deffn Command {jtag arp_init-reset} |
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@c ... more or less "toggle TRST ... and SRST too, what the heck" |
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@deffn Command {jtag cget} dotted.name @option{-event} name |
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@deffnx Command {jtag configure} dotted.name @option{-event} name string |
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At this writing this TAP attribute |
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@@ -3218,7 +3302,7 @@ The following target events are defined: |
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@end ignore |
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@item @b{reset-assert-pre} |
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@* Issued as part of @command{reset} processing |
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after SRST and/or TRST were activated and deactivated, |
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after @command{reset_init} was triggered |
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but before SRST alone is re-asserted on the tap. |
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@item @b{reset-assert-post} |
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@* Issued as part of @command{reset} processing |
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@@ -3248,10 +3332,11 @@ multiplexing, and so on. |
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the target clocks are fully set up.) |
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@item @b{reset-start} |
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@* Issued as part of @command{reset} processing |
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before either SRST or TRST are activated. |
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before @command{reset_init} is called. |
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This is the most robust place to switch to a low JTAG clock rate, if |
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SRST disables PLLs needed to use a fast clock. |
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This is the most robust place to use @command{jtag_rclk} |
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or @command{jtag_khz} to switch to a low JTAG clock rate, |
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when reset disables PLLs needed to use a fast clock. |
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@ignore |
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@item @b{reset-wait-pos} |
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@* Currently not used |
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@@ -5983,6 +6068,17 @@ The @command{reset_config} command should already have been used |
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to configure how the board and JTAG adapter treat these two |
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signals, and to say if either signal is even present. |
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@xref{Reset Configuration}. |
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Note that TRST is specially handled. |
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It actually signifies JTAG's @sc{reset} state. |
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So if the board doesn't support the optional TRST signal, |
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or it doesn't support it along with the specified SRST value, |
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JTAG reset is triggered with TMS and TCK signals |
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instead of the TRST signal. |
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And no matter how that JTAG reset is triggered, once |
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the scan chain enters @sc{reset} with TRST inactive, |
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TAP @code{post-reset} events are delivered to all TAPs |
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with handlers for that event. |
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@end deffn |
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@deffn Command {runtest} @var{num_cycles} |
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@@ -6015,7 +6111,7 @@ The @var{tap_state} names used by OpenOCD in the @command{drscan}, |
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and @command{irscan} commands are: |
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@itemize @bullet |
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@item @b{RESET} ... should act as if TRST were active |
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@item @b{RESET} ... acts as if TRST were pulsed |
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@item @b{RUN/IDLE} ... don't assume this always means IDLE |
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@item @b{DRSELECT} |
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@item @b{DRCAPTURE} |
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@@ -6046,7 +6142,7 @@ may not be as expected. |
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@item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable |
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choices after @command{drscan} or @command{irscan} commands, |
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since they are free of JTAG side effects. |
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However, @sc{run/idle} may have side effects that appear at other |
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@item @sc{run/idle} may have side effects that appear at non-JTAG |
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levels, such as advancing the ARM9E-S instruction pipeline. |
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Consult the documentation for the TAP(s) you are working with. |
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@end itemize |
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