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@@ -591,9 +591,20 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun |
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buffer += 4; |
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} |
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target_halt(target); |
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while (target->state != TARGET_HALTED) |
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target_poll(target); |
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retval = target_halt(target); |
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if (retval == ERROR_OK) |
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retval = target_wait_state(target, TARGET_HALTED, 500); |
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if (retval == ERROR_OK) { |
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uint32_t endaddress = |
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buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); |
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if (endaddress != address + count*4) { |
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LOG_ERROR("DCC write failed," |
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" expected end address 0x%08" PRIx32 |
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" got 0x%0" PRIx32 "", |
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address + count*4, endaddress); |
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retval = ERROR_FAIL; |
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} |
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} |
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/* restore target state */ |
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for (i = 0; i <= 5; i++) |
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@@ -607,7 +618,7 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun |
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armv4_5->core_cache->reg_list[15].dirty = 1; |
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armv4_5->core_state = core_state; |
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return ERROR_OK; |
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return retval; |
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} |
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int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target) |
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