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@@ -143,6 +143,133 @@ proc pll_v02_setup {pll_addr mult config} { |
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mww $pll_ctrl_addr $pll_ctrl |
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} |
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# PLL version 0x03: tested on dm365 |
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proc pll_v03_setup {pll_addr mult config} { |
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set pll_ctrl_addr [expr $pll_addr + 0x100] |
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set pll_secctrl_addr [expr $pll_addr + 0x108] |
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set pll_ctrl [mrw $pll_ctrl_addr] |
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# 1 - power up the PLL |
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set pll_ctrl [expr $pll_ctrl & ~0x0002] |
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mww $pll_ctrl_addr $pll_ctrl |
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# 2 - clear PLLENSRC (bit 5) |
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set pll_ctrl [expr $pll_ctrl & ~0x0020] |
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mww $pll_ctrl_addr $pll_ctrl |
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# 2 - clear PLLEN (bit 0) ... enter bypass mode |
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set pll_ctrl [expr $pll_ctrl & ~0x0001] |
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mww $pll_ctrl_addr $pll_ctrl |
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# 3 - wait at least 4 refclk cycles |
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sleep 1 |
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# 4 - set PLLRST (bit 3) |
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set pll_ctrl [expr $pll_ctrl | 0x0008] |
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mww $pll_ctrl_addr $pll_ctrl |
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# 5 - wait at least 5 usec |
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sleep 1 |
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# 6 - clear PLLRST (bit 3) |
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set pll_ctrl [expr $pll_ctrl & ~0x0008] |
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mww $pll_ctrl_addr $pll_ctrl |
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# 9 - optional: write prediv, postdiv, and pllm |
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mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] |
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if { [dict exists $config prediv] } { |
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set div [dict get $config prediv] |
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set div [expr ($div - 1)] |
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mww [expr $pll_addr + 0x0114] $div |
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} |
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if { [dict exists $config postdiv] } { |
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set div [dict get $config postdiv] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0128] $div |
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} |
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# 10 - write start sequence to PLLSECCTL |
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mww $pll_secctrl_addr 0x00470000 |
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mww $pll_secctrl_addr 0x00460000 |
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mww $pll_secctrl_addr 0x00400000 |
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mww $pll_secctrl_addr 0x00410000 |
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# 11 - optional: set plldiv1, plldiv2, ... |
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# NOTE: this assumes some registers have their just-reset values: |
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# - PLLSTAT.GOSTAT is clear when we enter |
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# - ALNCTL has everything set |
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set aln 0 |
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if { [dict exists $config div1] } { |
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set div [dict get $config div1] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0118] $div |
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set aln [expr $aln | 0x1] |
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} |
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if { [dict exists $config div2] } { |
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set div [dict get $config div2] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x011c] $div |
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set aln [expr $aln | 0x2] |
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} |
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if { [dict exists $config div3] } { |
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set div [dict get $config div3] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0120] $div |
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set aln [expr $aln | 0x4] |
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} |
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if { [dict exists $config div4] } { |
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set div [dict get $config div4] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0160] $div |
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set aln [expr $aln | 0x8] |
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} |
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if { [dict exists $config div5] } { |
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set div [dict get $config div5] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0164] $div |
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set aln [expr $aln | 0x10] |
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} |
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if { [dict exists $config div6] } { |
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set div [dict get $config div6] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0168] $div |
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set aln [expr $aln | 0x20] |
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} |
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if { [dict exists $config div7] } { |
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set div [dict get $config div7] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x016c] $div |
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set aln [expr $aln | 0x40] |
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} |
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if { [dict exists $config div8] } { |
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set div [dict get $config div8] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0170] $div |
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set aln [expr $aln | 0x80] |
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} |
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if { [dict exists $config div9] } { |
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set div [dict get $config div9] |
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set div [expr 0x8000 | ($div - 1)] |
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mww [expr $pll_addr + 0x0174] $div |
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set aln [expr $aln | 0x100] |
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} |
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if {$aln != 0} { |
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# write alingment flags |
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mww [expr $pll_addr + 0x0140] $aln |
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# write pllcmd.GO; poll pllstat.GO |
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mww [expr $pll_addr + 0x0138] 0x01 |
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set pllstat [expr $pll_addr + 0x013c] |
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while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } |
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} |
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mww [expr $pll_addr + 0x0138] 0x00 |
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set addr [dict get $config ctladdr] |
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while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } |
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# 12 - set PLLEN (bit 0) ... leave bypass mode |
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set pll_ctrl [expr $pll_ctrl | 0x0001] |
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mww $pll_ctrl_addr $pll_ctrl |
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} |
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# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain |
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# modules can be enabled. |
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