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@@ -50,8 +50,12 @@ flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ |
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# JTAG clock should be CCLK/6 (unless using adaptive clocking) |
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# CCLK is 4 MHz after reset, and until board-specific code (like |
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# a reset-init handler) speeds it up. |
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jtag_rclk [ expr 4000 / 6 ] |
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$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] } |
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# |
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# Although rclk "appears to work", it turns out that this yields |
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# 4MHz whereas the "correct" rate is CCLK/6, which is not what |
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# you get with rclk. |
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jtag_khz [ expr 4000 / 6 ] |
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$_TARGETNAME configure -event reset-init { |
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