Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>tags/v0.4.0-rc1
@@ -1582,7 +1582,7 @@ int arm7_9_restore_context(struct target *target) | |||||
struct arm *armv4_5 = &arm7_9->armv4_5_common; | struct arm *armv4_5 = &arm7_9->armv4_5_common; | ||||
struct reg *reg; | struct reg *reg; | ||||
struct arm_reg *reg_arch_info; | struct arm_reg *reg_arch_info; | ||||
enum armv4_5_mode current_mode = armv4_5->core_mode; | |||||
enum arm_mode current_mode = armv4_5->core_mode; | |||||
int i, j; | int i, j; | ||||
int dirty; | int dirty; | ||||
int mode_change; | int mode_change; | ||||
@@ -2093,7 +2093,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle | |||||
} | } | ||||
static int arm7_9_read_core_reg(struct target *target, struct reg *r, | static int arm7_9_read_core_reg(struct target *target, struct reg *r, | ||||
int num, enum armv4_5_mode mode) | |||||
int num, enum arm_mode mode) | |||||
{ | { | ||||
uint32_t* reg_p[16]; | uint32_t* reg_p[16]; | ||||
uint32_t value; | uint32_t value; | ||||
@@ -2157,7 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, | |||||
} | } | ||||
static int arm7_9_write_core_reg(struct target *target, struct reg *r, | static int arm7_9_write_core_reg(struct target *target, struct reg *r, | ||||
int num, enum armv4_5_mode mode, uint32_t value) | |||||
int num, enum arm_mode mode, uint32_t value) | |||||
{ | { | ||||
uint32_t reg[16]; | uint32_t reg[16]; | ||||
struct arm_reg *areg = r->arch_info; | struct arm_reg *areg = r->arch_info; | ||||
@@ -102,7 +102,7 @@ static int dpm_mcr(struct target *target, int cpnum, | |||||
/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one. | /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one. | ||||
* Routines *must* restore the original mode before returning!! | * Routines *must* restore the original mode before returning!! | ||||
*/ | */ | ||||
static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode) | |||||
static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) | |||||
{ | { | ||||
int retval; | int retval; | ||||
uint32_t cpsr; | uint32_t cpsr; | ||||
@@ -348,7 +348,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) | |||||
* actually find anything to do... | * actually find anything to do... | ||||
*/ | */ | ||||
do { | do { | ||||
enum armv4_5_mode mode = ARM_MODE_ANY; | |||||
enum arm_mode mode = ARM_MODE_ANY; | |||||
did_write = false; | did_write = false; | ||||
@@ -370,7 +370,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) | |||||
/* may need to pick and set a mode */ | /* may need to pick and set a mode */ | ||||
if (!did_write) { | if (!did_write) { | ||||
enum armv4_5_mode tmode; | |||||
enum arm_mode tmode; | |||||
did_write = true; | did_write = true; | ||||
mode = tmode = r->mode; | mode = tmode = r->mode; | ||||
@@ -432,10 +432,10 @@ done: | |||||
* Caller already filtered out SPSR access; mode is never MODE_SYS | * Caller already filtered out SPSR access; mode is never MODE_SYS | ||||
* or MODE_ANY. | * or MODE_ANY. | ||||
*/ | */ | ||||
static enum armv4_5_mode dpm_mapmode(struct arm *arm, | |||||
unsigned num, enum armv4_5_mode mode) | |||||
static enum arm_mode dpm_mapmode(struct arm *arm, | |||||
unsigned num, enum arm_mode mode) | |||||
{ | { | ||||
enum armv4_5_mode amode = arm->core_mode; | |||||
enum arm_mode amode = arm->core_mode; | |||||
/* don't switch if the mode is already correct */ | /* don't switch if the mode is already correct */ | ||||
if (amode == ARM_MODE_SYS) | if (amode == ARM_MODE_SYS) | ||||
@@ -473,7 +473,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm, | |||||
*/ | */ | ||||
static int arm_dpm_read_core_reg(struct target *target, struct reg *r, | static int arm_dpm_read_core_reg(struct target *target, struct reg *r, | ||||
int regnum, enum armv4_5_mode mode) | |||||
int regnum, enum arm_mode mode) | |||||
{ | { | ||||
struct arm_dpm *dpm = target_to_arm(target)->dpm; | struct arm_dpm *dpm = target_to_arm(target)->dpm; | ||||
int retval; | int retval; | ||||
@@ -513,7 +513,7 @@ fail: | |||||
} | } | ||||
static int arm_dpm_write_core_reg(struct target *target, struct reg *r, | static int arm_dpm_write_core_reg(struct target *target, struct reg *r, | ||||
int regnum, enum armv4_5_mode mode, uint32_t value) | |||||
int regnum, enum arm_mode mode, uint32_t value) | |||||
{ | { | ||||
struct arm_dpm *dpm = target_to_arm(target)->dpm; | struct arm_dpm *dpm = target_to_arm(target)->dpm; | ||||
int retval; | int retval; | ||||
@@ -566,7 +566,7 @@ static int arm_dpm_full_context(struct target *target) | |||||
goto done; | goto done; | ||||
do { | do { | ||||
enum armv4_5_mode mode = ARM_MODE_ANY; | |||||
enum arm_mode mode = ARM_MODE_ANY; | |||||
did_read = false; | did_read = false; | ||||
@@ -665,7 +665,7 @@ int arm_simulate_step_core(struct target *target, | |||||
} | } | ||||
else | else | ||||
{ | { | ||||
enum armv4_5_mode mode = sim->get_mode(sim); | |||||
enum arm_mode mode = sim->get_mode(sim); | |||||
int update_cpsr = 0; | int update_cpsr = 0; | ||||
if (instruction.info.load_store_multiple.S) | if (instruction.info.load_store_multiple.S) | ||||
@@ -721,7 +721,7 @@ int arm_simulate_step_core(struct target *target, | |||||
uint32_t Rn = sim->get_reg_mode(sim, | uint32_t Rn = sim->get_reg_mode(sim, | ||||
instruction.info.load_store_multiple.Rn); | instruction.info.load_store_multiple.Rn); | ||||
int bits_set = 0; | int bits_set = 0; | ||||
enum armv4_5_mode mode = sim->get_mode(sim); | |||||
enum arm_mode mode = sim->get_mode(sim); | |||||
for (i = 0; i < 16; i++) | for (i = 0; i < 16; i++) | ||||
{ | { | ||||
@@ -839,7 +839,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state | |||||
} | } | ||||
static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) | |||||
static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) | |||||
{ | { | ||||
struct arm *armv4_5 = (struct arm *)sim->user_data; | struct arm *armv4_5 = (struct arm *)sim->user_data; | ||||
@@ -34,7 +34,7 @@ struct arm_sim_interface | |||||
uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits); | uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits); | ||||
enum armv4_5_state (*get_state)(struct arm_sim_interface *sim); | enum armv4_5_state (*get_state)(struct arm_sim_interface *sim); | ||||
void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode); | void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode); | ||||
enum armv4_5_mode (*get_mode)(struct arm_sim_interface *sim); | |||||
enum arm_mode (*get_mode)(struct arm_sim_interface *sim); | |||||
}; | }; | ||||
/* armv4_5 version */ | /* armv4_5 version */ | ||||
@@ -163,7 +163,7 @@ bool is_arm_mode(unsigned psr_mode) | |||||
} | } | ||||
/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */ | /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */ | ||||
int armv4_5_mode_to_number(enum armv4_5_mode mode) | |||||
int arm_mode_to_number(enum arm_mode mode) | |||||
{ | { | ||||
switch (mode) { | switch (mode) { | ||||
case ARM_MODE_ANY: | case ARM_MODE_ANY: | ||||
@@ -191,7 +191,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode) | |||||
} | } | ||||
/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */ | /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */ | ||||
enum armv4_5_mode armv4_5_number_to_mode(int number) | |||||
enum arm_mode armv4_5_number_to_mode(int number) | |||||
{ | { | ||||
switch (number) { | switch (number) { | ||||
case 0: | case 0: | ||||
@@ -243,7 +243,7 @@ static const struct { | |||||
* (Exception modes have both CPSR and SPSR registers ...) | * (Exception modes have both CPSR and SPSR registers ...) | ||||
*/ | */ | ||||
unsigned cookie; | unsigned cookie; | ||||
enum armv4_5_mode mode; | |||||
enum arm_mode mode; | |||||
} arm_core_regs[] = { | } arm_core_regs[] = { | ||||
/* IMPORTANT: we guarantee that the first eight cached registers | /* IMPORTANT: we guarantee that the first eight cached registers | ||||
* correspond to r0..r7, and the fifteenth to PC, so that callers | * correspond to r0..r7, and the fifteenth to PC, so that callers | ||||
@@ -346,7 +346,7 @@ const int armv4_5_core_reg_map[8][17] = | |||||
*/ | */ | ||||
void arm_set_cpsr(struct arm *arm, uint32_t cpsr) | void arm_set_cpsr(struct arm *arm, uint32_t cpsr) | ||||
{ | { | ||||
enum armv4_5_mode mode = cpsr & 0x1f; | |||||
enum arm_mode mode = cpsr & 0x1f; | |||||
int num; | int num; | ||||
/* NOTE: this may be called very early, before the register | /* NOTE: this may be called very early, before the register | ||||
@@ -362,7 +362,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) | |||||
arm->core_mode = mode; | arm->core_mode = mode; | ||||
/* mode_to_number() warned; set up a somewhat-sane mapping */ | /* mode_to_number() warned; set up a somewhat-sane mapping */ | ||||
num = armv4_5_mode_to_number(mode); | |||||
num = arm_mode_to_number(mode); | |||||
if (num < 0) { | if (num < 0) { | ||||
mode = ARM_MODE_USR; | mode = ARM_MODE_USR; | ||||
num = 0; | num = 0; | ||||
@@ -512,7 +512,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) | |||||
* it won't hurt since CPSR is always flushed anyway. | * it won't hurt since CPSR is always flushed anyway. | ||||
*/ | */ | ||||
if (armv4_5_target->core_mode != | if (armv4_5_target->core_mode != | ||||
(enum armv4_5_mode)(value & 0x1f)) { | |||||
(enum arm_mode)(value & 0x1f)) { | |||||
LOG_DEBUG("changing ARM core mode to '%s'", | LOG_DEBUG("changing ARM core mode to '%s'", | ||||
arm_mode_name(value & 0x1f)); | arm_mode_name(value & 0x1f)); | ||||
value &= ~((1 << 24) | (1 << 5)); | value &= ~((1 << 24) | (1 << 5)); | ||||
@@ -30,7 +30,7 @@ | |||||
#include <helper/command.h> | #include <helper/command.h> | ||||
typedef enum armv4_5_mode | |||||
typedef enum arm_mode | |||||
{ | { | ||||
ARM_MODE_USR = 16, | ARM_MODE_USR = 16, | ||||
ARM_MODE_FIQ = 17, | ARM_MODE_FIQ = 17, | ||||
@@ -41,13 +41,13 @@ typedef enum armv4_5_mode | |||||
ARM_MODE_UND = 27, | ARM_MODE_UND = 27, | ||||
ARM_MODE_SYS = 31, | ARM_MODE_SYS = 31, | ||||
ARM_MODE_ANY = -1 | ARM_MODE_ANY = -1 | ||||
} armv4_5_mode_t; | |||||
} arm_mode_t; | |||||
const char *arm_mode_name(unsigned psr_mode); | const char *arm_mode_name(unsigned psr_mode); | ||||
bool is_arm_mode(unsigned psr_mode); | bool is_arm_mode(unsigned psr_mode); | ||||
int armv4_5_mode_to_number(enum armv4_5_mode mode); | |||||
enum armv4_5_mode armv4_5_number_to_mode(int number); | |||||
int arm_mode_to_number(enum arm_mode mode); | |||||
enum arm_mode armv4_5_number_to_mode(int number); | |||||
typedef enum armv4_5_state | typedef enum armv4_5_state | ||||
{ | { | ||||
@@ -62,7 +62,7 @@ extern char* armv4_5_state_strings[]; | |||||
extern const int armv4_5_core_reg_map[8][17]; | extern const int armv4_5_core_reg_map[8][17]; | ||||
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ | #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ | ||||
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]] | |||||
cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]] | |||||
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ | /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ | ||||
enum { ARMV4_5_CPSR = 31, }; | enum { ARMV4_5_CPSR = 31, }; | ||||
@@ -95,9 +95,9 @@ struct arm | |||||
* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three | * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three | ||||
* more registers are shadowed, for "Secure Monitor" mode. | * more registers are shadowed, for "Secure Monitor" mode. | ||||
*/ | */ | ||||
enum armv4_5_mode core_type; | |||||
enum arm_mode core_type; | |||||
enum armv4_5_mode core_mode; | |||||
enum arm_mode core_mode; | |||||
enum armv4_5_state core_state; | enum armv4_5_state core_state; | ||||
/** Flag reporting unavailability of the BKPT instruction. */ | /** Flag reporting unavailability of the BKPT instruction. */ | ||||
@@ -122,9 +122,9 @@ struct arm | |||||
int (*full_context)(struct target *target); | int (*full_context)(struct target *target); | ||||
int (*read_core_reg)(struct target *target, struct reg *reg, | int (*read_core_reg)(struct target *target, struct reg *reg, | ||||
int num, enum armv4_5_mode mode); | |||||
int num, enum arm_mode mode); | |||||
int (*write_core_reg)(struct target *target, struct reg *reg, | int (*write_core_reg)(struct target *target, struct reg *reg, | ||||
int num, enum armv4_5_mode mode, uint32_t value); | |||||
int num, enum arm_mode mode, uint32_t value); | |||||
/** Read coprocessor register. */ | /** Read coprocessor register. */ | ||||
int (*mrc)(struct target *target, int cpnum, | int (*mrc)(struct target *target, int cpnum, | ||||
@@ -158,14 +158,14 @@ struct armv4_5_algorithm | |||||
{ | { | ||||
int common_magic; | int common_magic; | ||||
enum armv4_5_mode core_mode; | |||||
enum arm_mode core_mode; | |||||
enum armv4_5_state core_state; | enum armv4_5_state core_state; | ||||
}; | }; | ||||
struct arm_reg | struct arm_reg | ||||
{ | { | ||||
int num; | int num; | ||||
enum armv4_5_mode mode; | |||||
enum arm_mode mode; | |||||
struct target *target; | struct target *target; | ||||
struct arm *armv4_5_common; | struct arm *armv4_5_common; | ||||
uint32_t value; | uint32_t value; | ||||
@@ -118,14 +118,14 @@ struct armv7a_algorithm | |||||
{ | { | ||||
int common_magic; | int common_magic; | ||||
enum armv4_5_mode core_mode; | |||||
enum arm_mode core_mode; | |||||
enum armv4_5_state core_state; | enum armv4_5_state core_state; | ||||
}; | }; | ||||
struct armv7a_core_reg | struct armv7a_core_reg | ||||
{ | { | ||||
int num; | int num; | ||||
enum armv4_5_mode mode; | |||||
enum arm_mode mode; | |||||
struct target *target; | struct target *target; | ||||
struct armv7a_common *armv7a_common; | struct armv7a_common *armv7a_common; | ||||
}; | }; | ||||
@@ -1658,7 +1658,7 @@ static int xscale_deassert_reset(struct target *target) | |||||
} | } | ||||
static int xscale_read_core_reg(struct target *target, struct reg *r, | static int xscale_read_core_reg(struct target *target, struct reg *r, | ||||
int num, enum armv4_5_mode mode) | |||||
int num, enum arm_mode mode) | |||||
{ | { | ||||
/** \todo add debug handler support for core register reads */ | /** \todo add debug handler support for core register reads */ | ||||
LOG_ERROR("not implemented"); | LOG_ERROR("not implemented"); | ||||
@@ -1666,7 +1666,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r, | |||||
} | } | ||||
static int xscale_write_core_reg(struct target *target, struct reg *r, | static int xscale_write_core_reg(struct target *target, struct reg *r, | ||||
int num, enum armv4_5_mode mode, uint32_t value) | |||||
int num, enum arm_mode mode, uint32_t value) | |||||
{ | { | ||||
/** \todo add debug handler support for core register writes */ | /** \todo add debug handler support for core register writes */ | ||||
LOG_ERROR("not implemented"); | LOG_ERROR("not implemented"); | ||||
@@ -1697,7 +1697,7 @@ static int xscale_full_context(struct target *target) | |||||
*/ | */ | ||||
for (i = 1; i < 7; i++) | for (i = 1; i < 7; i++) | ||||
{ | { | ||||
enum armv4_5_mode mode = armv4_5_number_to_mode(i); | |||||
enum arm_mode mode = armv4_5_number_to_mode(i); | |||||
bool valid = true; | bool valid = true; | ||||
struct reg *r; | struct reg *r; | ||||
@@ -1774,7 +1774,7 @@ static int xscale_restore_banked(struct target *target) | |||||
*/ | */ | ||||
for (i = 1; i < 7; i++) | for (i = 1; i < 7; i++) | ||||
{ | { | ||||
enum armv4_5_mode mode = armv4_5_number_to_mode(i); | |||||
enum arm_mode mode = armv4_5_number_to_mode(i); | |||||
struct reg *r; | struct reg *r; | ||||
if (mode == ARM_MODE_USR) | if (mode == ARM_MODE_USR) | ||||