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@@ -299,7 +299,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, |
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if (dscr & DSCR_DTR_RX_FULL) |
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{ |
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LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); |
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/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ |
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/* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ |
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retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), |
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&dscr); |
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if (retval != ERROR_OK) |
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@@ -318,7 +318,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, |
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if (Rd < 15) |
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{ |
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/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ |
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/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ |
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retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), |
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&dscr); |
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if (retval != ERROR_OK) |
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@@ -326,7 +326,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, |
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} |
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else if (Rd == 15) |
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{ |
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/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 |
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/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 |
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* then "mov r15, r0" |
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*/ |
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retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), |
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@@ -339,7 +339,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, |
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} |
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else |
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{ |
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/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 |
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/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 |
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* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) |
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*/ |
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retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), |
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