target: disable armv6m unaligned memory access

Change-Id: I42704cf80939ab9c9d4f402d2cd51c196e2fadb3
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/645
Tested-by: jenkins

src/target/arm.h

@@ -125,6 +125,9 @@ struct arm {
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
+	/** Flag reporting armv6m based core. */
+	bool is_armv6m;
+
 	/** Flag reporting whether semihosting is active. */
 	bool is_semihosting;
 

src/target/cortex_m.c

@@ -1570,6 +1570,12 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = &armv7m->dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	/* cortex_m3 handles unaligned memory access */
 	if (count && buffer) {
 		switch (size) {
@@ -1595,6 +1601,12 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = &armv7m->dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	if (count && buffer) {
 		switch (size) {
 			case 4:
@@ -1812,6 +1824,9 @@ int cortex_m3_examine(struct target *target)
 				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
 				armv7m->fp_feature = FPv4_SP;
 			}
+		} else if (i == 0) {
+			/* Cortex-M0 does not support unaligned memory access */
+			armv7m->arm.is_armv6m = true;
 		}
 
 		/* NOTE: FPB and DWT are both optional. */