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  1. /***************************************************************************
  2. * Copyright (C) 2013 Andes Technology *
  3. * Hsiangkai Wang <hkwang@andestech.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>. *
  17. ***************************************************************************/
  18. #ifdef HAVE_CONFIG_H
  19. #include "config.h"
  20. #endif
  21. #include "breakpoints.h"
  22. #include "nds32_cmd.h"
  23. #include "nds32_aice.h"
  24. #include "nds32_v3m.h"
  25. #include "nds32_v3_common.h"
  26. static int nds32_v3m_activate_hardware_breakpoint(struct target *target)
  27. {
  28. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  29. struct aice_port_s *aice = target_to_aice(target);
  30. struct breakpoint *bp;
  31. unsigned brp_num = nds32_v3m->n_hbr - 1;
  32. for (bp = target->breakpoints; bp; bp = bp->next) {
  33. if (bp->type == BKPT_SOFT) {
  34. /* already set at nds32_v3m_add_breakpoint() */
  35. continue;
  36. } else if (bp->type == BKPT_HARD) {
  37. /* set address */
  38. aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + brp_num, bp->address);
  39. /* set mask */
  40. aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + brp_num, 0);
  41. if (nds32_v3m->nds32.memory.address_translation)
  42. /* enable breakpoint (virtual address) */
  43. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x2);
  44. else
  45. /* enable breakpoint (physical address) */
  46. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0xA);
  47. LOG_DEBUG("Add hardware BP %u at %08" TARGET_PRIxADDR, brp_num,
  48. bp->address);
  49. brp_num--;
  50. } else {
  51. return ERROR_FAIL;
  52. }
  53. }
  54. return ERROR_OK;
  55. }
  56. static int nds32_v3m_deactivate_hardware_breakpoint(struct target *target)
  57. {
  58. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  59. struct aice_port_s *aice = target_to_aice(target);
  60. struct breakpoint *bp;
  61. unsigned brp_num = nds32_v3m->n_hbr - 1;
  62. for (bp = target->breakpoints; bp; bp = bp->next) {
  63. if (bp->type == BKPT_SOFT)
  64. continue;
  65. else if (bp->type == BKPT_HARD)
  66. /* disable breakpoint */
  67. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x0);
  68. else
  69. return ERROR_FAIL;
  70. LOG_DEBUG("Remove hardware BP %u at %08" TARGET_PRIxADDR, brp_num,
  71. bp->address);
  72. brp_num--;
  73. }
  74. return ERROR_OK;
  75. }
  76. static int nds32_v3m_activate_hardware_watchpoint(struct target *target)
  77. {
  78. struct aice_port_s *aice = target_to_aice(target);
  79. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  80. struct watchpoint *wp;
  81. int32_t wp_num = 0;
  82. uint32_t wp_config = 0;
  83. bool ld_stop, st_stop;
  84. if (nds32_v3m->nds32.global_stop)
  85. ld_stop = st_stop = false;
  86. for (wp = target->watchpoints; wp; wp = wp->next) {
  87. if (wp_num < nds32_v3m->used_n_wp) {
  88. wp->mask = wp->length - 1;
  89. if ((wp->address % wp->length) != 0)
  90. wp->mask = (wp->mask << 1) + 1;
  91. if (wp->rw == WPT_READ)
  92. wp_config = 0x3;
  93. else if (wp->rw == WPT_WRITE)
  94. wp_config = 0x5;
  95. else if (wp->rw == WPT_ACCESS)
  96. wp_config = 0x7;
  97. /* set/unset physical address bit of BPCn according to PSW.DT */
  98. if (nds32_v3m->nds32.memory.address_translation == false)
  99. wp_config |= 0x8;
  100. /* set address */
  101. aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
  102. wp->address - (wp->address % wp->length));
  103. /* set mask */
  104. aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
  105. /* enable watchpoint */
  106. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
  107. LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR
  108. " mask %08" PRIx32, wp_num, wp->address, wp->mask);
  109. wp_num++;
  110. } else if (nds32_v3m->nds32.global_stop) {
  111. if (wp->rw == WPT_READ)
  112. ld_stop = true;
  113. else if (wp->rw == WPT_WRITE)
  114. st_stop = true;
  115. else if (wp->rw == WPT_ACCESS)
  116. ld_stop = st_stop = true;
  117. }
  118. }
  119. if (nds32_v3m->nds32.global_stop) {
  120. uint32_t edm_ctl;
  121. aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
  122. if (ld_stop)
  123. edm_ctl |= 0x10;
  124. if (st_stop)
  125. edm_ctl |= 0x20;
  126. aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
  127. }
  128. return ERROR_OK;
  129. }
  130. static int nds32_v3m_deactivate_hardware_watchpoint(struct target *target)
  131. {
  132. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  133. struct aice_port_s *aice = target_to_aice(target);
  134. struct watchpoint *wp;
  135. int32_t wp_num = 0;
  136. bool clean_global_stop = false;
  137. for (wp = target->watchpoints; wp; wp = wp->next) {
  138. if (wp_num < nds32_v3m->used_n_wp) {
  139. /* disable watchpoint */
  140. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
  141. LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR
  142. " mask %08" PRIx32, wp_num, wp->address, wp->mask);
  143. wp_num++;
  144. } else if (nds32_v3m->nds32.global_stop) {
  145. clean_global_stop = true;
  146. }
  147. }
  148. if (clean_global_stop) {
  149. uint32_t edm_ctl;
  150. aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
  151. edm_ctl = edm_ctl & (~0x30);
  152. aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
  153. }
  154. return ERROR_OK;
  155. }
  156. static int nds32_v3m_check_interrupt_stack(struct nds32 *nds32)
  157. {
  158. uint32_t val_ir0;
  159. uint32_t value;
  160. /* Save interrupt level */
  161. nds32_get_mapped_reg(nds32, IR0, &val_ir0);
  162. nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
  163. if (nds32_reach_max_interrupt_level(nds32))
  164. LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->",
  165. nds32->current_interrupt_level);
  166. /* backup $ir6 to avoid suppressed exception overwrite */
  167. nds32_get_mapped_reg(nds32, IR6, &value);
  168. return ERROR_OK;
  169. }
  170. static int nds32_v3m_restore_interrupt_stack(struct nds32 *nds32)
  171. {
  172. uint32_t value;
  173. /* get backup value from cache */
  174. /* then set back to make the register dirty */
  175. nds32_get_mapped_reg(nds32, IR0, &value);
  176. nds32_set_mapped_reg(nds32, IR0, value);
  177. nds32_get_mapped_reg(nds32, IR6, &value);
  178. nds32_set_mapped_reg(nds32, IR6, value);
  179. return ERROR_OK;
  180. }
  181. static int nds32_v3m_deassert_reset(struct target *target)
  182. {
  183. int retval;
  184. CHECK_RETVAL(nds32_poll(target));
  185. if (target->state != TARGET_HALTED) {
  186. /* reset only */
  187. LOG_WARNING("%s: ran after reset and before halt ...",
  188. target_name(target));
  189. retval = target_halt(target);
  190. if (retval != ERROR_OK)
  191. return retval;
  192. }
  193. return ERROR_OK;
  194. }
  195. static int nds32_v3m_add_breakpoint(struct target *target,
  196. struct breakpoint *breakpoint)
  197. {
  198. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  199. struct nds32 *nds32 = &(nds32_v3m->nds32);
  200. int result;
  201. if (breakpoint->type == BKPT_HARD) {
  202. /* check hardware resource */
  203. if (nds32_v3m->next_hbr_index < nds32_v3m->next_hwp_index) {
  204. LOG_WARNING("<-- TARGET WARNING! Insert too many "
  205. "hardware breakpoints/watchpoints! "
  206. "The limit of combined hardware "
  207. "breakpoints/watchpoints is %" PRId32 ". -->",
  208. nds32_v3m->n_hbr);
  209. LOG_WARNING("<-- TARGET STATUS: Inserted number of "
  210. "hardware breakpoint: %" PRId32 ", hardware "
  211. "watchpoints: %" PRId32 ". -->",
  212. nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1,
  213. nds32_v3m->used_n_wp);
  214. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  215. }
  216. /* update next place to put hardware breakpoint */
  217. nds32_v3m->next_hbr_index--;
  218. /* hardware breakpoint insertion occurs before 'continue' actually */
  219. return ERROR_OK;
  220. } else if (breakpoint->type == BKPT_SOFT) {
  221. result = nds32_add_software_breakpoint(target, breakpoint);
  222. if (result != ERROR_OK) {
  223. /* auto convert to hardware breakpoint if failed */
  224. if (nds32->auto_convert_hw_bp) {
  225. /* convert to hardware breakpoint */
  226. breakpoint->type = BKPT_HARD;
  227. return nds32_v3m_add_breakpoint(target, breakpoint);
  228. }
  229. }
  230. return result;
  231. } else /* unrecognized breakpoint type */
  232. return ERROR_FAIL;
  233. return ERROR_OK;
  234. }
  235. static int nds32_v3m_remove_breakpoint(struct target *target,
  236. struct breakpoint *breakpoint)
  237. {
  238. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  239. if (breakpoint->type == BKPT_HARD) {
  240. if (nds32_v3m->next_hbr_index >= nds32_v3m->n_hbr - 1)
  241. return ERROR_FAIL;
  242. /* update next place to put hardware breakpoint */
  243. nds32_v3m->next_hbr_index++;
  244. /* hardware breakpoint removal occurs after 'halted' actually */
  245. return ERROR_OK;
  246. } else if (breakpoint->type == BKPT_SOFT) {
  247. return nds32_remove_software_breakpoint(target, breakpoint);
  248. } else /* unrecognized breakpoint type */
  249. return ERROR_FAIL;
  250. return ERROR_OK;
  251. }
  252. static int nds32_v3m_add_watchpoint(struct target *target,
  253. struct watchpoint *watchpoint)
  254. {
  255. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  256. /* check hardware resource */
  257. if (nds32_v3m->next_hwp_index >= nds32_v3m->n_hwp) {
  258. /* No hardware resource */
  259. if (nds32_v3m->nds32.global_stop) {
  260. LOG_WARNING("<-- TARGET WARNING! The number of "
  261. "watchpoints exceeds the hardware "
  262. "resources. Stop at every load/store "
  263. "instruction to check for watchpoint matches. -->");
  264. return ERROR_OK;
  265. }
  266. LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
  267. "watchpoints! The limit of hardware watchpoints "
  268. "is %" PRId32 ". -->", nds32_v3m->n_hwp);
  269. LOG_WARNING("<-- TARGET STATUS: Inserted number of "
  270. "hardware watchpoint: %" PRId32 ". -->",
  271. nds32_v3m->used_n_wp);
  272. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  273. }
  274. if (nds32_v3m->next_hwp_index > nds32_v3m->next_hbr_index) {
  275. /* No hardware resource */
  276. if (nds32_v3m->nds32.global_stop) {
  277. LOG_WARNING("<-- TARGET WARNING! The number of "
  278. "watchpoints exceeds the hardware "
  279. "resources. Stop at every load/store "
  280. "instruction to check for watchpoint matches. -->");
  281. return ERROR_OK;
  282. }
  283. LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
  284. "breakpoints/watchpoints! The limit of combined "
  285. "hardware breakpoints/watchpoints is %" PRId32 ". -->",
  286. nds32_v3m->n_hbr);
  287. LOG_WARNING("<-- TARGET STATUS: Inserted number of "
  288. "hardware breakpoint: %" PRId32 ", hardware "
  289. "watchpoints: %" PRId32 ". -->",
  290. nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1,
  291. nds32_v3m->used_n_wp);
  292. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  293. }
  294. /* update next place to put hardware watchpoint */
  295. nds32_v3m->next_hwp_index++;
  296. nds32_v3m->used_n_wp++;
  297. return ERROR_OK;
  298. }
  299. static int nds32_v3m_remove_watchpoint(struct target *target,
  300. struct watchpoint *watchpoint)
  301. {
  302. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  303. if (nds32_v3m->next_hwp_index <= 0) {
  304. if (nds32_v3m->nds32.global_stop)
  305. return ERROR_OK;
  306. return ERROR_FAIL;
  307. }
  308. /* update next place to put hardware watchpoint */
  309. nds32_v3m->next_hwp_index--;
  310. nds32_v3m->used_n_wp--;
  311. return ERROR_OK;
  312. }
  313. static struct nds32_v3_common_callback nds32_v3m_common_callback = {
  314. .check_interrupt_stack = nds32_v3m_check_interrupt_stack,
  315. .restore_interrupt_stack = nds32_v3m_restore_interrupt_stack,
  316. .activate_hardware_breakpoint = nds32_v3m_activate_hardware_breakpoint,
  317. .activate_hardware_watchpoint = nds32_v3m_activate_hardware_watchpoint,
  318. .deactivate_hardware_breakpoint = nds32_v3m_deactivate_hardware_breakpoint,
  319. .deactivate_hardware_watchpoint = nds32_v3m_deactivate_hardware_watchpoint,
  320. };
  321. static int nds32_v3m_target_create(struct target *target, Jim_Interp *interp)
  322. {
  323. struct nds32_v3m_common *nds32_v3m;
  324. nds32_v3m = calloc(1, sizeof(*nds32_v3m));
  325. if (!nds32_v3m)
  326. return ERROR_FAIL;
  327. nds32_v3_common_register_callback(&nds32_v3m_common_callback);
  328. nds32_v3_target_create_common(target, &(nds32_v3m->nds32));
  329. return ERROR_OK;
  330. }
  331. /* talk to the target and set things up */
  332. static int nds32_v3m_examine(struct target *target)
  333. {
  334. struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
  335. struct nds32 *nds32 = &(nds32_v3m->nds32);
  336. struct aice_port_s *aice = target_to_aice(target);
  337. if (!target_was_examined(target)) {
  338. CHECK_RETVAL(nds32_edm_config(nds32));
  339. if (nds32->reset_halt_as_examine)
  340. CHECK_RETVAL(nds32_reset_halt(nds32));
  341. }
  342. uint32_t edm_cfg;
  343. aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
  344. /* get the number of hardware breakpoints */
  345. nds32_v3m->n_hbr = (edm_cfg & 0x7) + 1;
  346. nds32_v3m->used_n_wp = 0;
  347. /* get the number of hardware watchpoints */
  348. /* If the WP field is hardwired to zero, it means this is a
  349. * simple breakpoint. Otherwise, if the WP field is writable
  350. * then it means this is a regular watchpoints. */
  351. nds32_v3m->n_hwp = 0;
  352. for (int32_t i = 0 ; i < nds32_v3m->n_hbr ; i++) {
  353. /** check the hardware breakpoint is simple or not */
  354. uint32_t tmp_value;
  355. aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + i, 0x1);
  356. aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &tmp_value);
  357. if (tmp_value)
  358. nds32_v3m->n_hwp++;
  359. }
  360. /* hardware breakpoint is inserted from high index to low index */
  361. nds32_v3m->next_hbr_index = nds32_v3m->n_hbr - 1;
  362. /* hardware watchpoint is inserted from low index to high index */
  363. nds32_v3m->next_hwp_index = 0;
  364. LOG_INFO("%s: total hardware breakpoint %" PRId32 " (simple breakpoint %" PRId32 ")",
  365. target_name(target), nds32_v3m->n_hbr, nds32_v3m->n_hbr - nds32_v3m->n_hwp);
  366. LOG_INFO("%s: total hardware watchpoint %" PRId32, target_name(target), nds32_v3m->n_hwp);
  367. nds32->target->state = TARGET_RUNNING;
  368. nds32->target->debug_reason = DBG_REASON_NOTHALTED;
  369. target_set_examined(target);
  370. return ERROR_OK;
  371. }
  372. /** Holds methods for NDS32 V3m targets. */
  373. struct target_type nds32_v3m_target = {
  374. .name = "nds32_v3m",
  375. .poll = nds32_poll,
  376. .arch_state = nds32_arch_state,
  377. .target_request_data = nds32_v3_target_request_data,
  378. .halt = nds32_halt,
  379. .resume = nds32_resume,
  380. .step = nds32_step,
  381. .assert_reset = nds32_assert_reset,
  382. .deassert_reset = nds32_v3m_deassert_reset,
  383. /* register access */
  384. .get_gdb_reg_list = nds32_get_gdb_reg_list,
  385. /* memory access */
  386. .read_buffer = nds32_v3_read_buffer,
  387. .write_buffer = nds32_v3_write_buffer,
  388. .read_memory = nds32_v3_read_memory,
  389. .write_memory = nds32_v3_write_memory,
  390. .checksum_memory = nds32_v3_checksum_memory,
  391. /* breakpoint/watchpoint */
  392. .add_breakpoint = nds32_v3m_add_breakpoint,
  393. .remove_breakpoint = nds32_v3m_remove_breakpoint,
  394. .add_watchpoint = nds32_v3m_add_watchpoint,
  395. .remove_watchpoint = nds32_v3m_remove_watchpoint,
  396. .hit_watchpoint = nds32_v3_hit_watchpoint,
  397. /* MMU */
  398. .mmu = nds32_mmu,
  399. .virt2phys = nds32_virtual_to_physical,
  400. .read_phys_memory = nds32_read_phys_memory,
  401. .write_phys_memory = nds32_write_phys_memory,
  402. .run_algorithm = nds32_v3_run_algorithm,
  403. .commands = nds32_command_handlers,
  404. .target_create = nds32_v3m_target_create,
  405. .init_target = nds32_v3_init_target,
  406. .examine = nds32_v3m_examine,
  407. .get_gdb_fileio_info = nds32_get_gdb_fileio_info,
  408. .gdb_fileio_end = nds32_gdb_fileio_end,
  409. };