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openocd/src/flash/non_cfi.c

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  1. /***************************************************************************

  2.  *   Copyright (C) 2007 by Dominic Rath                                    *

  3.  *   Dominic.Rath@gmx.de                                                   *

  4.  *   Copyright (C) 2009 Michael Schwingen                                  *

  5.  *   michael@schwingen.org                                                 *

  6.  *                                                                         *

  7.  *   This program is free software; you can redistribute it and/or modify  *

  8.  *   it under the terms of the GNU General Public License as published by  *

  9.  *   the Free Software Foundation; either version 2 of the License, or     *

  10.  *   (at your option) any later version.                                   *

  11.  *                                                                         *

  12.  *   This program is distributed in the hope that it will be useful,       *

  13.  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

  14.  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

  15.  *   GNU General Public License for more details.                          *

  16.  *                                                                         *

  17.  *   You should have received a copy of the GNU General Public License     *

  18.  *   along with this program; if not, write to the                         *

  19.  *   Free Software Foundation, Inc.,                                       *

  20.  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *

  21.  ***************************************************************************/

  22. #ifdef HAVE_CONFIG_H

  23. #include "config.h"

  24. #endif

  25. 

  26. #include "non_cfi.h"

  27. #include "cfi.h"

  28. 

  29. 

  30. #define KB 1024

  31. #define MB (1024*1024)

  32. #define ERASE_REGION(num, size) (((size/256) << 16) | (num-1))

  33. 

  34. /* non-CFI compatible flashes */

  35. static non_cfi_t non_cfi_flashes[] = {

  36. 	{

  37. 		.mfr = CFI_MFR_SST,

  38. 		.id = 0xd4,

  39. 		.pri_id = 0x02,

  40. 		.dev_size = 64*KB,

  41. 		.interface_desc = 0x0,		/* x8 only device */

  42. 		.max_buf_write_size = 0x0,

  43. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  44. 		.num_erase_regions = 1,

  45. 		.erase_region_info =

  46. 		{

  47. 			ERASE_REGION(16, 4*KB)

  48. 		}

  49. 	},

  50. 	{

  51. 		.mfr = CFI_MFR_SST,

  52. 		.id = 0xd5,

  53. 		.pri_id = 0x02,

  54. 		.dev_size = 128*KB,

  55. 		.interface_desc = 0x0,		/* x8 only device */

  56. 		.max_buf_write_size = 0x0,

  57. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  58. 		.num_erase_regions = 1,

  59. 		.erase_region_info =

  60. 		{

  61. 			ERASE_REGION(32, 4*KB)

  62. 		}

  63. 	},

  64. 	{

  65. 		.mfr = CFI_MFR_SST,

  66. 		.id = 0xd6,

  67. 		.pri_id = 0x02,

  68. 		.dev_size = 256*KB,

  69. 		.interface_desc = 0x0,		/* x8 only device */

  70. 		.max_buf_write_size = 0x0,

  71. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  72. 		.num_erase_regions = 1,

  73. 		.erase_region_info =

  74. 		{

  75. 			ERASE_REGION(64, 4*KB)

  76. 		}

  77. 	},

  78. 	{

  79. 		.mfr = CFI_MFR_SST,

  80. 		.id = 0xd7,

  81. 		.pri_id = 0x02,

  82. 		.dev_size = 512*KB,

  83. 		.interface_desc = 0x0,		/* x8 only device */

  84. 		.max_buf_write_size = 0x0,

  85. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  86. 		.num_erase_regions = 1,

  87. 		.erase_region_info =

  88. 		{

  89. 			ERASE_REGION(128, 4*KB)

  90. 		}

  91. 	},

  92. 	{

  93. 		.mfr = CFI_MFR_SST,

  94. 		.id = 0x2780,

  95. 		.pri_id = 0x02,

  96. 		.dev_size = 512*KB,

  97. 		.interface_desc = 0x2,		/* x8 or x16 device */

  98. 		.max_buf_write_size = 0x0,

  99. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  100. 		.num_erase_regions = 1,

  101. 		.erase_region_info =

  102. 		{

  103. 			ERASE_REGION(128, 4*KB)

  104. 		}

  105. 	},

  106. 	{

  107. 		.mfr = CFI_MFR_ST,

  108. 		.id = 0xd6,					/* ST29F400BB */

  109. 		.pri_id = 0x02,

  110. 		.dev_size = 512*KB,

  111. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  112. 		.max_buf_write_size = 0x0,

  113. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  114. 		.num_erase_regions = 4,

  115. 		.erase_region_info =

  116. 		{

  117. 			ERASE_REGION(1, 16*KB),

  118. 			ERASE_REGION(2,  8*KB),

  119. 			ERASE_REGION(1, 32*KB),

  120. 			ERASE_REGION(7, 64*KB)

  121. 		}

  122. 	},

  123. 	{

  124. 		.mfr = CFI_MFR_ST,

  125. 		.id = 0xd5,					/* ST29F400BT */

  126. 		.pri_id = 0x02,

  127. 		.dev_size = 512*KB,

  128. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  129. 		.max_buf_write_size = 0x0,

  130. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  131. 		.num_erase_regions = 4,

  132. 		.erase_region_info =

  133. 		{

  134. 			ERASE_REGION(7, 64*KB),

  135. 			ERASE_REGION(1, 32*KB),

  136. 			ERASE_REGION(2,  8*KB),

  137. 			ERASE_REGION(1, 16*KB)

  138. 		}

  139. 	},

  140. 

  141. 	/* SST 39VF* do not support DQ5 status polling - this currently is

  142. 	   only supported by the host algorithm, not by the target code using

  143. 	   the work area.

  144.            Only true for 8-bit and 32-bit wide memories. 16-bit wide memories

  145.            without DQ5 status polling are supported by the target code.

  146.         */

  147. 	{

  148. 		.mfr = CFI_MFR_SST,

  149. 		.id = 0x2782,				/* SST39xF160 */

  150. 		.pri_id = 0x02,

  151. 		.dev_size = 2*MB,

  152. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  153. 		.max_buf_write_size = 0x0,

  154. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  155. 		.num_erase_regions = 1,

  156. 		.erase_region_info =

  157. 		{

  158. 			ERASE_REGION(512, 4*KB)

  159. 		}

  160. 	},

  161. 	{

  162. 		.mfr = CFI_MFR_SST,

  163. 		.id = 0x2783,				/* SST39VF320 */

  164. 		.pri_id = 0x02,

  165. 		.dev_size = 4*MB,

  166. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  167. 		.max_buf_write_size = 0x0,

  168. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  169. 		.num_erase_regions = 1,

  170. 		.erase_region_info =

  171. 		{

  172. 			ERASE_REGION(1024, 4*KB)

  173. 		}

  174. 	},

  175. 	{

  176. 		.mfr = CFI_MFR_SST,

  177. 		.id = 0x234b,				/* SST39VF1601 */

  178. 		.pri_id = 0x02,

  179. 		.dev_size = 2*MB,

  180. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  181. 		.max_buf_write_size = 0x0,

  182. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  183. 		.num_erase_regions = 1,

  184. 		.erase_region_info =

  185. 		{

  186. 			ERASE_REGION(512, 4*KB)

  187. 		}

  188. 	},

  189. 	{

  190. 		.mfr = CFI_MFR_SST,

  191. 		.id = 0x234a,				/* SST39VF1602 */

  192. 		.pri_id = 0x02,

  193. 		.dev_size = 2*MB,

  194. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  195. 		.max_buf_write_size = 0x0,

  196. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  197. 		.num_erase_regions = 1,

  198. 		.erase_region_info =

  199. 		{

  200. 			ERASE_REGION(512, 4*KB)

  201. 		}

  202. 	},

  203. 	{

  204. 		.mfr = CFI_MFR_SST,

  205. 		.id = 0x235b,				/* SST39VF3201 */

  206. 		.pri_id = 0x02,

  207. 		.dev_size = 4*MB,

  208. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  209. 		.max_buf_write_size = 0x0,

  210. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  211. 		.num_erase_regions = 1,

  212. 		.erase_region_info =

  213. 		{

  214. 			ERASE_REGION(1024, 4*KB)

  215. 		}

  216. 	},

  217. 	{

  218. 		.mfr = CFI_MFR_SST,

  219. 		.id = 0x235a,				/* SST39VF3202 */

  220. 		.pri_id = 0x02,

  221. 		.dev_size = 4*MB,

  222. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  223. 		.max_buf_write_size = 0x0,

  224. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,

  225. 		.num_erase_regions = 1,

  226. 		.erase_region_info =

  227. 		{

  228. 			ERASE_REGION(1024, 4*KB)

  229. 		}

  230. 	},

  231. 	{

  232. 		.mfr = CFI_MFR_AMD,

  233. 		.id = 0x22ab,				/* AM29F400BB */

  234. 		.pri_id = 0x02,

  235. 		.dev_size = 512*KB,

  236. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  237. 		.max_buf_write_size = 0x0,

  238. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  239. 		.num_erase_regions = 4,

  240. 		.erase_region_info =

  241. 		{

  242. 			ERASE_REGION(1, 16*KB),

  243. 			ERASE_REGION(2,  8*KB),

  244. 			ERASE_REGION(1, 32*KB),

  245. 			ERASE_REGION(7, 64*KB)

  246. 		}

  247. 	},

  248. 	{

  249. 		.mfr = CFI_MFR_AMD,

  250. 		.id = 0x2223,				/* AM29F400BT */

  251. 		.pri_id = 0x02,

  252. 		.dev_size = 512*KB,

  253. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  254. 		.max_buf_write_size = 0x0,

  255. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  256. 		.num_erase_regions = 4,

  257. 		.erase_region_info =

  258. 		{

  259. 			ERASE_REGION(7, 64*KB),

  260. 			ERASE_REGION(1, 32*KB),

  261. 			ERASE_REGION(2,  8*KB),

  262. 			ERASE_REGION(1, 16*KB)

  263. 		}

  264. 	},

  265. 	{

  266. 		.mfr = CFI_MFR_FUJITSU,

  267. 		.id = 0x226b,				/* AM29SL800DB */

  268. 		.pri_id = 0x02,

  269. 		.dev_size = 1*MB,

  270. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  271. 		.max_buf_write_size = 0x0,

  272. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  273. 		.num_erase_regions = 4,

  274. 		.erase_region_info =

  275. 		{

  276. 			ERASE_REGION(1, 16*KB),

  277. 			ERASE_REGION(2,  8*KB),

  278. 			ERASE_REGION(1, 32*KB),

  279. 			ERASE_REGION(15, 64*KB)

  280. 		}

  281. 	},

  282. 	{

  283. 		.mfr = CFI_MFR_AMIC,

  284. 		.id = 0xb31a,				/* A29L800A */

  285. 		.pri_id = 0x02,

  286. 		.dev_size = 1*MB,

  287. 		.interface_desc = 0x2,

  288. 		.max_buf_write_size = 0x0,

  289. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  290. 		.num_erase_regions = 4,

  291. 		.erase_region_info =

  292. 		{

  293. 			ERASE_REGION(1, 16*KB),

  294. 			ERASE_REGION(2,  8*KB),

  295. 			ERASE_REGION(1, 32*KB),

  296. 			ERASE_REGION(15, 64*KB)

  297. 		}

  298. 	},

  299. 	{

  300. 		.mfr = CFI_MFR_MX,

  301. 		.id = 0x225b,				/* MX29LV800B */

  302. 		.pri_id = 0x02,

  303. 		.dev_size = 1*MB,

  304. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  305. 		.max_buf_write_size = 0x0,

  306. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  307. 		.num_erase_regions = 4,

  308. 		.erase_region_info =

  309. 		{

  310. 			ERASE_REGION(1, 16*KB),

  311. 			ERASE_REGION(2, 8*KB),

  312. 			ERASE_REGION(1, 32*KB),

  313. 			ERASE_REGION(15, 64*KB)

  314. 		}

  315. 	},

  316. 

  317. 	{

  318. 		.mfr = CFI_MFR_MX,

  319. 		.id = 0x2249,				/* MX29LV160AB: 2MB */

  320. 		.pri_id = 0x02,

  321. 		.dev_size = 2*MB,

  322. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  323. 		.max_buf_write_size = 0x0,

  324. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  325. 		.num_erase_regions = 4,

  326. 		.erase_region_info =

  327. 		{

  328. 			ERASE_REGION(1, 16*KB),

  329. 			ERASE_REGION(2, 8*KB),

  330. 			ERASE_REGION(1, 32*KB),

  331. 			ERASE_REGION(31, 64*KB)

  332. 		}

  333. 	},

  334. 	{

  335. 		.mfr = CFI_MFR_MX,

  336. 		.id = 0x22C4,				/* MX29LV160AT: 2MB */

  337. 		.pri_id = 0x02,

  338. 		.dev_size = 2*MB,

  339. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  340. 		.max_buf_write_size = 0x0,

  341. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  342. 		.num_erase_regions = 4,

  343. 		.erase_region_info =

  344. 		{

  345. 			ERASE_REGION(31, 64*KB),

  346. 			ERASE_REGION(1, 32*KB),

  347. 			ERASE_REGION(2, 8*KB),

  348. 			ERASE_REGION(1, 16*KB)

  349. 		}

  350. 	},

  351. 	{

  352. 		.mfr = CFI_MFR_ATMEL,

  353. 		.id = 0x00c0,				/* Atmel 49BV1614 */

  354. 		.pri_id = 0x02,

  355. 		.dev_size = 2*MB,

  356. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  357. 		.max_buf_write_size = 0x0,

  358. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  359. 		.num_erase_regions = 3,

  360. 		.erase_region_info =

  361. 		{

  362. 			ERASE_REGION(8,  8*KB),

  363. 			ERASE_REGION(2, 32*KB),

  364. 			ERASE_REGION(30, 64*KB)

  365. 		}

  366. 	},

  367. 	{

  368. 		.mfr = CFI_MFR_ATMEL,

  369. 		.id = 0xC2,					/* Atmel 49BV1614T */

  370. 		.pri_id = 0x02,

  371. 		.dev_size = 2*MB,

  372. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  373. 		.max_buf_write_size = 0x0,

  374. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  375. 		.num_erase_regions = 3,

  376. 		.erase_region_info =

  377. 		{

  378. 			ERASE_REGION(30, 64*KB),

  379. 			ERASE_REGION(2, 32*KB),

  380. 			ERASE_REGION(8,  8*KB)

  381. 		}

  382. 	},

  383. 	{

  384. 		.mfr = CFI_MFR_AMD,

  385. 		.id = 0x225b,				/* S29AL008D */

  386. 		.pri_id = 0x02,

  387. 		.dev_size = 1*MB,

  388. 		.interface_desc = 0x2,		/* x8 or x16 device with nBYTE */

  389. 		.max_buf_write_size = 0x0,

  390. 		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,

  391. 		.num_erase_regions = 4,

  392. 		.erase_region_info =

  393. 		{

  394. 			ERASE_REGION(1, 16*KB),

  395. 			ERASE_REGION(2, 8*KB),

  396. 			ERASE_REGION(1, 32*KB),

  397. 			ERASE_REGION(15, 64*KB)

  398. 		}

  399. 	},

  400. 	{

  401. 		.mfr = 0,

  402. 		.id = 0,

  403. 	}

  404. };

  405. 

  406. void cfi_fixup_non_cfi(flash_bank_t *bank)

  407. {

  408. 	struct cfi_flash_bank *cfi_info = bank->driver_priv;

  409. 	non_cfi_t *non_cfi = non_cfi_flashes;

  410. 

  411. 	for (non_cfi = non_cfi_flashes; non_cfi->mfr; non_cfi++)

  412. 	{

  413. 		if ((cfi_info->manufacturer == non_cfi->mfr)

  414. 			&& (cfi_info->device_id == non_cfi->id))

  415. 		{

  416. 			break;

  417. 		}

  418. 	}

  419. 

  420. 	/* only fixup jedec flashs found in table */

  421. 	if (!non_cfi->mfr)

  422. 		return;

  423. 

  424. 	cfi_info->not_cfi = 1;

  425. 

  426. 	/* fill in defaults for non-critical data */

  427. 	cfi_info->vcc_min = 0x0;

  428. 	cfi_info->vcc_max = 0x0;

  429. 	cfi_info->vpp_min = 0x0;

  430. 	cfi_info->vpp_max = 0x0;

  431. 	cfi_info->word_write_timeout_typ = 0x0;

  432. 	cfi_info->buf_write_timeout_typ = 0x0;

  433. 	cfi_info->block_erase_timeout_typ = 0x0;

  434. 	cfi_info->chip_erase_timeout_typ = 0x0;

  435. 	cfi_info->word_write_timeout_max = 0x0;

  436. 	cfi_info->buf_write_timeout_max = 0x0;

  437. 	cfi_info->block_erase_timeout_max = 0x0;

  438. 	cfi_info->chip_erase_timeout_max = 0x0;

  439. 

  440. 	cfi_info->qry[0] = 'Q';

  441. 	cfi_info->qry[1] = 'R';

  442. 	cfi_info->qry[2] = 'Y';

  443. 

  444. 	cfi_info->pri_id = non_cfi->pri_id;

  445. 	cfi_info->pri_addr = 0x0;

  446. 	cfi_info->alt_id = 0x0;

  447. 	cfi_info->alt_addr = 0x0;

  448. 	cfi_info->alt_ext = NULL;

  449. 

  450. 	cfi_info->interface_desc = non_cfi->interface_desc;

  451. 	cfi_info->max_buf_write_size = non_cfi->max_buf_write_size;

  452. 	cfi_info->status_poll_mask = non_cfi->status_poll_mask;

  453. 	cfi_info->num_erase_regions = non_cfi->num_erase_regions;

  454. 	cfi_info->erase_region_info = non_cfi->erase_region_info;

  455. 	cfi_info->dev_size = non_cfi->dev_size;

  456. 

  457. 	if (cfi_info->pri_id == 0x2)

  458. 	{

  459. 		struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));

  460. 

  461. 		pri_ext->pri[0] = 'P';

  462. 		pri_ext->pri[1] = 'R';

  463. 		pri_ext->pri[2] = 'I';

  464. 

  465. 		pri_ext->major_version = '1';

  466. 		pri_ext->minor_version = '0';

  467. 

  468. 		pri_ext->SiliconRevision = 0x0;

  469. 		pri_ext->EraseSuspend = 0x0;

  470. 		pri_ext->EraseSuspend = 0x0;

  471. 		pri_ext->BlkProt = 0x0;

  472. 		pri_ext->TmpBlkUnprotect = 0x0;

  473. 		pri_ext->BlkProtUnprot = 0x0;

  474. 		pri_ext->SimultaneousOps = 0x0;

  475. 		pri_ext->BurstMode = 0x0;

  476. 		pri_ext->PageMode = 0x0;

  477. 		pri_ext->VppMin = 0x0;

  478. 		pri_ext->VppMax = 0x0;

  479. 		pri_ext->TopBottom = 0x0;

  480. 

  481. 		pri_ext->_unlock1 = 0x5555;

  482. 		pri_ext->_unlock2 = 0x2AAA;

  483. 		pri_ext->_reversed_geometry = 0;

  484. 

  485. 		cfi_info->pri_ext = pri_ext;

  486. 	} else if ((cfi_info->pri_id == 0x1) || (cfi_info->pri_id == 0x3))

  487. 	{

  488. 		LOG_ERROR("BUG: non-CFI flashes using the Intel commandset are not yet supported");

  489. 		exit(-1);

  490. 	}

  491. }