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  1. /***************************************************************************
  2. * Copyright (C) 2005, 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * Copyright (C) 2010 Spencer Oliver *
  5. * spen@spen-soft.co.uk *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ***************************************************************************/
  22. .text
  23. .arm
  24. .arch armv4
  25. .section .init
  26. /* algorithm register usage:
  27. * r0: source address (in RAM)
  28. * r1: target address (in Flash)
  29. * r2: count
  30. * r3: flash write command
  31. * r4: status byte (returned to host)
  32. * r5: busy test pattern
  33. * r6: error test pattern
  34. */
  35. loop:
  36. ldrh r4, [r0], #2
  37. strh r3, [r1]
  38. strh r4, [r1]
  39. busy:
  40. ldrh r4, [r1]
  41. and r7, r4, r5
  42. cmp r7, r5
  43. bne busy
  44. tst r4, r6
  45. bne done
  46. subs r2, r2, #1
  47. beq done
  48. add r1, r1, #2
  49. b loop
  50. done:
  51. b done
  52. .end