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  1. /***************************************************************************
  2. * Copyright (C) 2005, 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * Copyright (C) 2010 Spencer Oliver *
  5. * spen@spen-soft.co.uk *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ***************************************************************************/
  22. .text
  23. .arm
  24. .arch armv4
  25. .section .init
  26. /* input parameters - */
  27. /* R0 = source address */
  28. /* R1 = destination address */
  29. /* R2 = number of writes */
  30. /* R3 = flash write command */
  31. /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
  32. /* output parameters - */
  33. /* R5 = 0x80 ok 0x00 bad */
  34. /* temp registers - */
  35. /* R6 = value read from flash to test status */
  36. /* R7 = holding register */
  37. /* unlock registers - */
  38. /* R8 = unlock1_addr */
  39. /* R9 = unlock1_cmd */
  40. /* R10 = unlock2_addr */
  41. /* R11 = unlock2_cmd */
  42. code:
  43. ldrh r5, [r0], #2
  44. strh r9, [r8]
  45. strh r11, [r10]
  46. strh r3, [r8]
  47. strh r5, [r1]
  48. nop
  49. busy:
  50. ldrh r6, [r1]
  51. eor r7, r5, r6
  52. ands r7, r4, r7
  53. beq cont /* b if DQ7 == Data7 */
  54. ands r6, r6, r4, lsr #2
  55. beq busy /* b if DQ5 low */
  56. ldrh r6, [r1]
  57. eor r7, r5, r6
  58. ands r7, r4, r7
  59. beq cont /* b if DQ7 == Data7 */
  60. mov r5, #0 /* 0x0 - return 0x00, error */
  61. bne done
  62. cont:
  63. subs r2, r2, #1 /* 0x1 */
  64. moveq r5, #128 /* 0x80 */
  65. beq done
  66. add r1, r1, #2 /* 0x2 */
  67. b code
  68. done:
  69. b done
  70. .end