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  1. /***************************************************************************
  2. * Copyright (C) 2011 by Andreas Fritiofson *
  3. * andreas.fritiofson@gmail.com *
  4. * Copyright (C) 2013 by Roman Dmitrienko *
  5. * me@iamroman.org *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ***************************************************************************/
  22. .text
  23. .syntax unified
  24. .cpu cortex-m0
  25. .thumb
  26. .thumb_func
  27. /* Params:
  28. * r0 - flash base (in), status (out)
  29. * r1 - count (word-32bit)
  30. * r2 - workarea start
  31. * r3 - workarea end
  32. * r4 - target address
  33. * Clobbered:
  34. * r5 - rp
  35. * r6 - wp, tmp
  36. * r7 - tmp
  37. */
  38. /* offsets of registers from flash reg base */
  39. #define EFM32_MSC_WRITECTRL_OFFSET 0x008
  40. #define EFM32_MSC_WRITECMD_OFFSET 0x00c
  41. #define EFM32_MSC_ADDRB_OFFSET 0x010
  42. #define EFM32_MSC_WDATA_OFFSET 0x018
  43. #define EFM32_MSC_STATUS_OFFSET 0x01c
  44. #define EFM32_MSC_LOCK_OFFSET 0x03c
  45. /* unlock MSC */
  46. ldr r6, =#0x1b71
  47. str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
  48. /* set WREN to 1 */
  49. movs r6, #1
  50. str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
  51. wait_fifo:
  52. ldr r6, [r2, #0] /* read wp */
  53. cmp r6, #0 /* abort if wp == 0 */
  54. beq exit
  55. ldr r5, [r2, #4] /* read rp */
  56. cmp r5, r6 /* wait until rp != wp */
  57. beq wait_fifo
  58. /* store address in MSC_ADDRB */
  59. str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
  60. /* set LADDRIM bit */
  61. movs r6, #1
  62. str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
  63. /* check status for INVADDR and/or LOCKED */
  64. ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  65. movs r7, #6
  66. tst r6, r7
  67. bne error
  68. /* wait for WDATAREADY */
  69. wait_wdataready:
  70. ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  71. movs r7, #8
  72. tst r6, r7
  73. beq wait_wdataready
  74. /* load data to WDATA */
  75. ldr r6, [r5]
  76. str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
  77. /* set WRITEONCE bit */
  78. movs r6, #8
  79. str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
  80. adds r5, #4 /* rp++ */
  81. adds r4, #4 /* target_address++ */
  82. /* wait until BUSY flag is reset */
  83. busy:
  84. ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  85. movs r7, #1
  86. tst r6, r7
  87. bne busy
  88. cmp r5, r3 /* wrap rp at end of buffer */
  89. bcc no_wrap
  90. mov r5, r2
  91. adds r5, #8
  92. no_wrap:
  93. str r5, [r2, #4] /* store rp */
  94. subs r1, r1, #1 /* decrement word count */
  95. cmp r1, #0
  96. beq exit /* loop if not done */
  97. b wait_fifo
  98. error:
  99. movs r0, #0
  100. str r0, [r2, #4] /* set rp = 0 on error */
  101. exit:
  102. mov r0, r6 /* return status in r0 */
  103. bkpt #0