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  1. /***************************************************************************
  2. * Copyright (C) 2012 by George Harris *
  3. * george@luminairecoffee.com *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. /***************************************************************************
  21. * This is an algorithm for the LPC43xx family (and probably the LPC18xx *
  22. * family as well, though they have not been tested) that will initialize *
  23. * memory-mapped SPI flash accesses. Unfortunately NXP has published *
  24. * neither the ROM source code that performs this initialization nor the *
  25. * register descriptions necessary to do so, so this code is necessary to *
  26. * call into the ROM SPIFI API. *
  27. ***************************************************************************/
  28. .text
  29. .syntax unified
  30. .arch armv7-m
  31. .thumb
  32. .thumb_func
  33. .align 2
  34. /*
  35. * Params :
  36. * r0 = spifi clock speed
  37. */
  38. #define IOCONFIG_BASE_HIGH 0x4008
  39. #define IOCONFIG_BASE_LOW 0x6000
  40. #define IOCONFIG_SCK_OFFSET 0x18c
  41. #define IOCONFIG_HOLD_OFFSET 0x190
  42. #define IOCONFIG_WP_OFFSET 0x194
  43. #define IOCONFIG_MISO_OFFSET 0x198
  44. #define IOCONFIG_MOSI_OFFSET 0x19c
  45. #define IOCONFIG_CS_OFFSET 0x1a0
  46. #define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
  47. #define SPIFI_ROM_TABLE_BASE_LOW 0x0118
  48. code:
  49. mov.w r8, r0
  50. sub sp, #0x84
  51. add r7, sp, #0x0
  52. /* Initialize SPIFI pins */
  53. mov.w r3, #IOCONFIG_BASE_LOW
  54. movt r3, #IOCONFIG_BASE_HIGH
  55. mov.w r2, #0xf3
  56. str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
  57. mov.w r3, #IOCONFIG_BASE_LOW
  58. movt r3, #IOCONFIG_BASE_HIGH
  59. mov.w r2, #IOCONFIG_BASE_LOW
  60. movt r2, #IOCONFIG_BASE_HIGH
  61. mov.w r1, #IOCONFIG_BASE_LOW
  62. movt r1, #IOCONFIG_BASE_HIGH
  63. mov.w r0, #IOCONFIG_BASE_LOW
  64. movt r0, #IOCONFIG_BASE_HIGH
  65. mov.w r4, #0xd3
  66. str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
  67. mov r0, r4
  68. str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
  69. mov r1, r0
  70. str.w r1, [r2, #IOCONFIG_WP_OFFSET]
  71. str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
  72. mov.w r3, #IOCONFIG_BASE_LOW
  73. movt r3, #IOCONFIG_BASE_HIGH
  74. mov.w r2, #0x13
  75. str.w r2, [r3, #IOCONFIG_CS_OFFSET]
  76. /* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
  77. /* on initialization arguments. */
  78. movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
  79. movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
  80. ldr r3, [r3, #0x0]
  81. ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
  82. /* Set up function arguments */
  83. movw r0, #0x3b4
  84. movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
  85. mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
  86. mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
  87. mov.w r3, r8 /* SPIFI clock speed (12MHz) */
  88. blx r4 /* Call the init function */
  89. b done
  90. done:
  91. bkpt #0
  92. .end