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  1. /***************************************************************************
  2. * Copyright (C) 2010 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2011 √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  22. ***************************************************************************/
  23. .text
  24. .syntax unified
  25. .cpu cortex-m3
  26. .thumb
  27. .thumb_func
  28. /*
  29. * Params :
  30. * r0 = workarea start, status (out)
  31. * r1 = workarea end
  32. * r2 = target address
  33. * r3 = count (16bit words)
  34. * r4 = flash base
  35. *
  36. * Clobbered:
  37. * r6 - temp
  38. * r7 - rp
  39. * r8 - wp, tmp
  40. */
  41. #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
  42. #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
  43. wait_fifo:
  44. ldr r8, [r0, #0] /* read wp */
  45. cmp r8, #0 /* abort if wp == 0 */
  46. beq exit
  47. ldr r7, [r0, #4] /* read rp */
  48. cmp r7, r8 /* wait until rp != wp */
  49. beq wait_fifo
  50. ldr r6, STM32_PROG16
  51. str r6, [r4, #STM32_FLASH_CR_OFFSET]
  52. ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
  53. strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
  54. busy:
  55. ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
  56. tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
  57. bne busy /* wait more... */
  58. tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
  59. bne error /* fail... */
  60. cmp r7, r1 /* wrap rp at end of buffer */
  61. it cs
  62. addcs r7, r0, #8 /* skip loader args */
  63. str r7, [r0, #4] /* store rp */
  64. subs r3, r3, #1 /* decrement halfword count */
  65. cbz r3, exit /* loop if not done */
  66. b wait_fifo
  67. error:
  68. movs r1, #0
  69. str r1, [r0, #4] /* set rp = 0 on error */
  70. exit:
  71. mov r0, r6 /* return status in r0 */
  72. bkpt #0x00
  73. STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/