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  1. /***************************************************************************
  2. * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  18. ***************************************************************************/
  19. #ifndef _MFLASH_H
  20. #define _MFLASH_H
  21. struct command_context;
  22. typedef unsigned long mg_io_uint32;
  23. typedef unsigned short mg_io_uint16;
  24. typedef unsigned char mg_io_uint8;
  25. struct mflash_gpio_num {
  26. char port[2];
  27. signed short num;
  28. };
  29. struct mflash_gpio_drv {
  30. const char *name;
  31. int (*set_gpio_to_output)(struct mflash_gpio_num gpio);
  32. int (*set_gpio_output_val)(struct mflash_gpio_num gpio, uint8_t val);
  33. };
  34. typedef struct _mg_io_type_drv_info {
  35. mg_io_uint16 general_configuration; /* 00 */
  36. mg_io_uint16 number_of_cylinders; /* 01 */
  37. mg_io_uint16 reserved1; /* 02 */
  38. mg_io_uint16 number_of_heads; /* 03 */
  39. mg_io_uint16 unformatted_bytes_per_track; /* 04 */
  40. mg_io_uint16 unformatted_bytes_per_sector; /* 05 */
  41. mg_io_uint16 sectors_per_track; /* 06 */
  42. mg_io_uint16 vendor_unique1[3]; /* 07/08/09 */
  43. mg_io_uint8 serial_number[20]; /* 10~19 */
  44. mg_io_uint16 buffer_type; /* 20 */
  45. mg_io_uint16 buffer_sector_size; /* 21 */
  46. mg_io_uint16 number_of_ecc_bytes; /* 22 */
  47. mg_io_uint8 firmware_revision[8]; /* 23~26 */
  48. mg_io_uint8 model_number[40]; /* 27 */
  49. mg_io_uint8 maximum_block_transfer; /* 47 low byte */
  50. mg_io_uint8 vendor_unique2; /* 47 high byte */
  51. mg_io_uint16 dword_io; /* 48 */
  52. mg_io_uint16 capabilities; /* 49 */
  53. mg_io_uint16 reserved2; /* 50 */
  54. mg_io_uint8 vendor_unique3; /* 51 low byte */
  55. mg_io_uint8 pio_cycle_timing_mode; /* 51 high byte */
  56. mg_io_uint8 vendor_unique4; /* 52 low byte */
  57. mg_io_uint8 dma_cycle_timing_mode; /* 52 high byte */
  58. mg_io_uint16 translation_fields_valid; /* 53 (low bit) */
  59. mg_io_uint16 number_of_current_cylinders; /* 54 */
  60. mg_io_uint16 number_of_current_heads; /* 55 */
  61. mg_io_uint16 current_sectors_per_track; /* 56 */
  62. mg_io_uint16 current_sector_capacity_lo; /* 57 & 58 */
  63. mg_io_uint16 current_sector_capacity_hi; /* 57 & 58 */
  64. mg_io_uint8 multi_sector_count; /* 59 low */
  65. mg_io_uint8 multi_sector_setting_valid; /* 59 high (low bit) */
  66. mg_io_uint16 total_user_addressable_sectors_lo; /* 60 & 61 */
  67. mg_io_uint16 total_user_addressable_sectors_hi; /* 60 & 61 */
  68. mg_io_uint8 single_dma_modes_supported; /* 62 low byte */
  69. mg_io_uint8 single_dma_transfer_active; /* 62 high byte */
  70. mg_io_uint8 multi_dma_modes_supported; /* 63 low byte */
  71. mg_io_uint8 multi_dma_transfer_active; /* 63 high byte */
  72. mg_io_uint16 adv_pio_mode;
  73. mg_io_uint16 min_dma_cyc;
  74. mg_io_uint16 recommend_dma_cyc;
  75. mg_io_uint16 min_pio_cyc_no_iordy;
  76. mg_io_uint16 min_pio_cyc_with_iordy;
  77. mg_io_uint8 reserved3[22];
  78. mg_io_uint16 major_ver_num;
  79. mg_io_uint16 minor_ver_num;
  80. mg_io_uint16 feature_cmd_set_suprt0;
  81. mg_io_uint16 feature_cmd_set_suprt1;
  82. mg_io_uint16 feature_cmd_set_suprt2;
  83. mg_io_uint16 feature_cmd_set_en0;
  84. mg_io_uint16 feature_cmd_set_en1;
  85. mg_io_uint16 feature_cmd_set_en2;
  86. mg_io_uint16 reserved4;
  87. mg_io_uint16 req_time_for_security_er_done;
  88. mg_io_uint16 req_time_for_enhan_security_er_done;
  89. mg_io_uint16 adv_pwr_mgm_lvl_val;
  90. mg_io_uint16 reserved5;
  91. mg_io_uint16 re_of_hw_rst;
  92. mg_io_uint8 reserved6[68];
  93. mg_io_uint16 security_stas;
  94. mg_io_uint8 vendor_uniq_bytes[62];
  95. mg_io_uint16 cfa_pwr_mode;
  96. mg_io_uint8 reserved7[186];
  97. mg_io_uint16 scts_per_secure_data_unit;
  98. mg_io_uint16 integrity_word;
  99. } mg_io_type_drv_info;
  100. typedef struct _mg_pll_t {
  101. unsigned int lock_cyc;
  102. unsigned short feedback_div; /* 9bit divider */
  103. unsigned char input_div; /* 5bit divider */
  104. unsigned char output_div; /* 2bit divider */
  105. } mg_pll_t;
  106. struct mg_drv_info {
  107. mg_io_type_drv_info drv_id;
  108. uint32_t tot_sects;
  109. };
  110. struct mflash_bank {
  111. uint32_t base;
  112. struct mflash_gpio_num rst_pin;
  113. struct mflash_gpio_drv *gpio_drv;
  114. struct target *target;
  115. struct mg_drv_info *drv_info;
  116. };
  117. int mflash_register_commands(struct command_context *cmd_ctx);
  118. #define MG_MFLASH_SECTOR_SIZE (0x200) /* 512Bytes = 2^9 */
  119. #define MG_MFLASH_SECTOR_SIZE_MASK (0x200-1)
  120. #define MG_MFLASH_SECTOR_SIZE_SHIFT (9)
  121. #define MG_BUFFER_OFFSET 0x8000
  122. #define MG_REG_OFFSET 0xC000
  123. #define MG_REG_FEATURE 0x2 /* write case */
  124. #define MG_REG_ERROR 0x2 /* read case */
  125. #define MG_REG_SECT_CNT 0x4
  126. #define MG_REG_SECT_NUM 0x6
  127. #define MG_REG_CYL_LOW 0x8
  128. #define MG_REG_CYL_HIGH 0xA
  129. #define MG_REG_DRV_HEAD 0xC
  130. #define MG_REG_COMMAND 0xE /* write case */
  131. #define MG_REG_STATUS 0xE /* read case */
  132. #define MG_REG_DRV_CTRL 0x10
  133. #define MG_REG_BURST_CTRL 0x12
  134. #define MG_OEM_DISK_WAIT_TIME_LONG 15000 /* msec */
  135. #define MG_OEM_DISK_WAIT_TIME_NORMAL 3000 /* msec */
  136. #define MG_OEM_DISK_WAIT_TIME_SHORT 1000 /* msec */
  137. #define MG_PLL_CLK_OUT 66000000.0 /* 66Mhz */
  138. #define MG_PLL_MAX_FEEDBACKDIV_VAL 512
  139. #define MG_PLL_MAX_INPUTDIV_VAL 32
  140. #define MG_PLL_MAX_OUTPUTDIV_VAL 4
  141. #define MG_PLL_STD_INPUTCLK 12000000.0 /* 12Mhz */
  142. #define MG_PLL_STD_LOCKCYCLE 10000
  143. #define MG_UNLOCK_OTP_AREA 0xFF
  144. #define MG_FILEIO_CHUNK 1048576
  145. #define ERROR_MG_IO (-1600)
  146. #define ERROR_MG_TIMEOUT (-1601)
  147. #define ERROR_MG_INVALID_PLL (-1603)
  148. #define ERROR_MG_INTERFACE (-1604)
  149. #define ERROR_MG_INVALID_OSC (-1605)
  150. #define ERROR_MG_UNSUPPORTED_SOC (-1606)
  151. typedef enum _mg_io_type_wait {
  152. mg_io_wait_bsy = 1,
  153. mg_io_wait_not_bsy = 2,
  154. mg_io_wait_rdy = 3,
  155. mg_io_wait_drq = 4, /* wait for data request */
  156. mg_io_wait_drq_noerr = 5, /* wait for DRQ but ignore the error status bit */
  157. mg_io_wait_rdy_noerr = 6 /* wait for ready, but ignore error status bit */
  158. } mg_io_type_wait;
  159. /*= "Status Register" bit masks. */
  160. typedef enum _mg_io_type_rbit_status {
  161. mg_io_rbit_status_error = 0x01, /* error bit in status register */
  162. mg_io_rbit_status_corrected_error = 0x04, /* corrected error in status register */
  163. mg_io_rbit_status_data_req = 0x08, /* data request bit in status register */
  164. mg_io_rbit_status_seek_done = 0x10, /* DSC - Drive Seek Complete */
  165. mg_io_rbit_status_write_fault = 0x20, /* DWF - Drive Write Fault */
  166. mg_io_rbit_status_ready = 0x40,
  167. mg_io_rbit_status_busy = 0x80
  168. } mg_io_type_rbit_status;
  169. /*= "Error Register" bit masks. */
  170. typedef enum _mg_io_type_rbit_error {
  171. mg_io_rbit_err_general = 0x01,
  172. mg_io_rbit_err_aborted = 0x04,
  173. mg_io_rbit_err_bad_sect_num = 0x10,
  174. mg_io_rbit_err_uncorrectable = 0x40,
  175. mg_io_rbit_err_bad_block = 0x80
  176. } mg_io_type_rbit_error;
  177. /* = "Device Control Register" bit. */
  178. typedef enum _mg_io_type_rbit_devc {
  179. mg_io_rbit_devc_intr = 0x02, /* interrupt enable bit (1:disable, 0:enable) */
  180. mg_io_rbit_devc_srst = 0x04 /* softwrae reset bit (1:assert, 0:de-assert) */
  181. } mg_io_type_rbit_devc;
  182. /* "Drive Select/Head Register" values. */
  183. typedef enum _mg_io_type_rval_dev {
  184. mg_io_rval_dev_must_be_on = 0x80, /* These 1 bits are always on */
  185. mg_io_rval_dev_drv_master = (0x00 | mg_io_rval_dev_must_be_on), /* Master */
  186. mg_io_rval_dev_drv_slave0 = (0x10 | mg_io_rval_dev_must_be_on), /* Slave0 */
  187. mg_io_rval_dev_drv_slave1 = (0x20 | mg_io_rval_dev_must_be_on), /* Slave1 */
  188. mg_io_rval_dev_drv_slave2 = (0x30 | mg_io_rval_dev_must_be_on), /* Slave2 */
  189. mg_io_rval_dev_lba_mode = (0x40 | mg_io_rval_dev_must_be_on)
  190. } mg_io_type_rval_dev;
  191. typedef enum _mg_io_type_cmd {
  192. mg_io_cmd_read = 0x20,
  193. mg_io_cmd_write = 0x30,
  194. mg_io_cmd_setmul = 0xC6,
  195. mg_io_cmd_readmul = 0xC4,
  196. mg_io_cmd_writemul = 0xC5,
  197. mg_io_cmd_idle = 0x97, /* 0xE3 */
  198. mg_io_cmd_idle_immediate = 0x95, /* 0xE1 */
  199. mg_io_cmd_setsleep = 0x99, /* 0xE6 */
  200. mg_io_cmd_stdby = 0x96, /* 0xE2 */
  201. mg_io_cmd_stdby_immediate = 0x94, /* 0xE0 */
  202. mg_io_cmd_identify = 0xEC,
  203. mg_io_cmd_set_feature = 0xEF,
  204. mg_io_cmd_confirm_write = 0x3C,
  205. mg_io_cmd_confirm_read = 0x40,
  206. mg_io_cmd_wakeup = 0xC3
  207. } mg_io_type_cmd;
  208. typedef enum _mg_feature_id {
  209. mg_feature_id_transmode = 0x3
  210. } mg_feature_id;
  211. typedef enum _mg_feature_val {
  212. mg_feature_val_trans_default = 0x0,
  213. mg_feature_val_trans_vcmd = 0x3,
  214. mg_feature_val_trand_vcmds = 0x2
  215. } mg_feature_val;
  216. typedef enum _mg_vcmd {
  217. mg_vcmd_update_xipinfo = 0xFA, /* FWPATCH commmand through IOM I/O */
  218. mg_vcmd_verify_fwpatch = 0xFB, /* FWPATCH commmand through IOM I/O */
  219. mg_vcmd_update_stgdrvinfo = 0xFC, /* IOM identificatin info program command */
  220. mg_vcmd_prep_fwpatch = 0xFD, /* FWPATCH commmand through IOM I/O */
  221. mg_vcmd_exe_fwpatch = 0xFE, /* FWPATCH commmand through IOM I/O */
  222. mg_vcmd_wr_pll = 0x8B,
  223. mg_vcmd_purge_nand = 0x8C, /* Only for Seagle */
  224. mg_vcmd_lock_otp = 0x8D,
  225. mg_vcmd_rd_otp = 0x8E,
  226. mg_vcmd_wr_otp = 0x8F
  227. } mg_vcmd;
  228. typedef enum _mg_opmode {
  229. mg_op_mode_xip = 1, /* TRUE XIP */
  230. mg_op_mode_snd = 2, /* BOOT + Storage */
  231. mg_op_mode_stg = 0 /* Only Storage */
  232. } mg_opmode;
  233. #endif