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  1. /*
  2. * Copyright (C) 2009 by Dean Glazeski
  3. * dnglaze@gmail.com
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the
  17. * Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. */
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include <target/arm.h>
  24. #include <helper/log.h>
  25. #include "imp.h"
  26. #include "arm_io.h"
  27. #define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
  28. #define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
  29. #define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
  30. #define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
  31. #define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
  32. #define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
  33. #define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
  34. /**
  35. * Representation of a pin on an AT91SAM9 chip.
  36. */
  37. struct at91sam9_pin {
  38. /** Address of the PIO controller. */
  39. uint32_t pioc;
  40. /** Pin number. */
  41. uint32_t num;
  42. };
  43. /**
  44. * Private data for the controller that is stored in the NAND device structure.
  45. */
  46. struct at91sam9_nand {
  47. /** Address of the ECC controller for NAND. */
  48. uint32_t ecc;
  49. /** Address data is written to. */
  50. uint32_t data;
  51. /** Address commands are written to. */
  52. uint32_t cmd;
  53. /** Address addresses are written to. */
  54. uint32_t addr;
  55. /** I/O structure for hosted reads/writes. */
  56. struct arm_nand_data io;
  57. /** Pin representing the ready/~busy line. */
  58. struct at91sam9_pin busy;
  59. /** Pin representing the chip enable. */
  60. struct at91sam9_pin ce;
  61. };
  62. /**
  63. * Checks if the target is halted and prints an error message if it isn't.
  64. *
  65. * @param target Target to be checked.
  66. * @param label String label for where function is called from.
  67. * @return True if the target is halted.
  68. */
  69. static int at91sam9_halted(struct target *target, const char *label)
  70. {
  71. if (target->state == TARGET_HALTED)
  72. return true;
  73. LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  74. return false;
  75. }
  76. /**
  77. * Initialize the AT91SAM9 NAND controller.
  78. *
  79. * @param nand NAND device the controller is attached to.
  80. * @return Success or failure of initialization.
  81. */
  82. static int at91sam9_init(struct nand_device *nand)
  83. {
  84. struct target *target = nand->target;
  85. if (!at91sam9_halted(target, "init"))
  86. return ERROR_NAND_OPERATION_FAILED;
  87. return ERROR_OK;
  88. }
  89. /**
  90. * Enable NAND device attached to a controller.
  91. *
  92. * @param info NAND controller information for controlling NAND device.
  93. * @return Success or failure of the enabling.
  94. */
  95. static int at91sam9_enable(struct nand_device *nand)
  96. {
  97. struct at91sam9_nand *info = nand->controller_priv;
  98. struct target *target = nand->target;
  99. return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
  100. }
  101. /**
  102. * Disable NAND device attached to a controller.
  103. *
  104. * @param info NAND controller information for controlling NAND device.
  105. * @return Success or failure of the disabling.
  106. */
  107. static int at91sam9_disable(struct nand_device *nand)
  108. {
  109. struct at91sam9_nand *info = nand->controller_priv;
  110. struct target *target = nand->target;
  111. return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
  112. }
  113. /**
  114. * Send a command to the NAND device.
  115. *
  116. * @param nand NAND device to write the command to.
  117. * @param command Command to be written.
  118. * @return Success or failure of writing the command.
  119. */
  120. static int at91sam9_command(struct nand_device *nand, uint8_t command)
  121. {
  122. struct at91sam9_nand *info = nand->controller_priv;
  123. struct target *target = nand->target;
  124. if (!at91sam9_halted(target, "command"))
  125. return ERROR_NAND_OPERATION_FAILED;
  126. at91sam9_enable(nand);
  127. return target_write_u8(target, info->cmd, command);
  128. }
  129. /**
  130. * Reset the AT91SAM9 NAND controller.
  131. *
  132. * @param nand NAND device to be reset.
  133. * @return Success or failure of reset.
  134. */
  135. static int at91sam9_reset(struct nand_device *nand)
  136. {
  137. if (!at91sam9_halted(nand->target, "reset"))
  138. return ERROR_NAND_OPERATION_FAILED;
  139. return at91sam9_disable(nand);
  140. }
  141. /**
  142. * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
  143. *
  144. * @param nand NAND device to send the address to.
  145. * @param address Address to be sent.
  146. * @return Success or failure of sending the address.
  147. */
  148. static int at91sam9_address(struct nand_device *nand, uint8_t address)
  149. {
  150. struct at91sam9_nand *info = nand->controller_priv;
  151. struct target *target = nand->target;
  152. if (!at91sam9_halted(nand->target, "address"))
  153. return ERROR_NAND_OPERATION_FAILED;
  154. return target_write_u8(target, info->addr, address);
  155. }
  156. /**
  157. * Read data directly from the NAND device attached to an AT91SAM9 NAND
  158. * controller.
  159. *
  160. * @param nand NAND device to read from.
  161. * @param data Pointer to where the data should be put.
  162. * @return Success or failure of reading the data.
  163. */
  164. static int at91sam9_read_data(struct nand_device *nand, void *data)
  165. {
  166. struct at91sam9_nand *info = nand->controller_priv;
  167. struct target *target = nand->target;
  168. if (!at91sam9_halted(nand->target, "read data"))
  169. return ERROR_NAND_OPERATION_FAILED;
  170. return target_read_u8(target, info->data, data);
  171. }
  172. /**
  173. * Write data directly to the NAND device attached to an AT91SAM9 NAND
  174. * controller.
  175. *
  176. * @param nand NAND device to be written to.
  177. * @param data Data to be written.
  178. * @return Success or failure of the data write.
  179. */
  180. static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
  181. {
  182. struct at91sam9_nand *info = nand->controller_priv;
  183. struct target *target = nand->target;
  184. if (!at91sam9_halted(target, "write data"))
  185. return ERROR_NAND_OPERATION_FAILED;
  186. return target_write_u8(target, info->data, data);
  187. }
  188. /**
  189. * Determine if the NAND device is ready by looking at the ready/~busy pin.
  190. *
  191. * @param nand NAND device to check.
  192. * @param timeout Time in milliseconds to wait for NAND to be ready.
  193. * @return True if the NAND is ready in the timeout period.
  194. */
  195. static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
  196. {
  197. struct at91sam9_nand *info = nand->controller_priv;
  198. struct target *target = nand->target;
  199. uint32_t status;
  200. if (!at91sam9_halted(target, "nand ready"))
  201. return 0;
  202. do {
  203. target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
  204. if (status & (1 << info->busy.num))
  205. return 1;
  206. alive_sleep(1);
  207. } while (timeout-- > 0);
  208. return 0;
  209. }
  210. /**
  211. * Read a block of data from the NAND device attached to an AT91SAM9. This
  212. * utilizes the ARM hosted NAND read function.
  213. *
  214. * @param nand NAND device to read from.
  215. * @param data Pointer to where the read data should be placed.
  216. * @param size Size of the data being read.
  217. * @return Success or failure of the hosted read.
  218. */
  219. static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
  220. {
  221. struct at91sam9_nand *info = nand->controller_priv;
  222. struct arm_nand_data *io = &info->io;
  223. int status;
  224. if (!at91sam9_halted(nand->target, "read block"))
  225. return ERROR_NAND_OPERATION_FAILED;
  226. io->chunk_size = nand->page_size;
  227. status = arm_nandread(io, data, size);
  228. return status;
  229. }
  230. /**
  231. * Write a block of data to a NAND device attached to an AT91SAM9. This uses
  232. * the ARM hosted write function to write the data.
  233. *
  234. * @param nand NAND device to write to.
  235. * @param data Data to be written to device.
  236. * @param size Size of the data being written.
  237. * @return Success or failure of the hosted write.
  238. */
  239. static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
  240. {
  241. struct at91sam9_nand *info = nand->controller_priv;
  242. struct arm_nand_data *io = &info->io;
  243. int status;
  244. if (!at91sam9_halted(nand->target, "write block"))
  245. return ERROR_NAND_OPERATION_FAILED;
  246. io->chunk_size = nand->page_size;
  247. status = arm_nandwrite(io, data, size);
  248. return status;
  249. }
  250. /**
  251. * Initialize the ECC controller on the AT91SAM9.
  252. *
  253. * @param target Target to configure ECC on.
  254. * @param info NAND controller information for where the ECC is.
  255. * @return Success or failure of initialization.
  256. */
  257. static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
  258. {
  259. if (!info->ecc) {
  260. LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
  261. return ERROR_NAND_OPERATION_FAILED;
  262. }
  263. /* reset ECC parity registers */
  264. return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
  265. }
  266. /**
  267. * Initialize an area for the OOB based on whether a user is requesting the OOB
  268. * data. This determines the size of the OOB and allocates the space in case
  269. * the user has not requested the OOB data.
  270. *
  271. * @param nand NAND device we are creating an OOB for.
  272. * @param oob Pointer to the user supplied OOB area.
  273. * @param size Size of the OOB.
  274. * @return Pointer to an area to store OOB data.
  275. */
  276. static uint8_t *at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
  277. {
  278. if (!oob) {
  279. /* user doesn't want OOB, allocate it */
  280. if (nand->page_size == 512)
  281. *size = 16;
  282. else if (nand->page_size == 2048)
  283. *size = 64;
  284. oob = malloc(*size);
  285. if (!oob) {
  286. LOG_ERROR("Unable to allocate space for OOB");
  287. return NULL;
  288. }
  289. memset(oob, 0xFF, *size);
  290. }
  291. return oob;
  292. }
  293. /**
  294. * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
  295. * controller on chip. This makes an attempt to correct any errors that are
  296. * encountered while reading the page of data.
  297. *
  298. * @param nand NAND device to read from
  299. * @param page Page to be read.
  300. * @param data Pointer to where data should be read to.
  301. * @param data_size Size of the data to be read.
  302. * @param oob Pointer to where OOB data should be read to.
  303. * @param oob_size Size of the OOB data to be read.
  304. * @return Success or failure of reading the NAND page.
  305. */
  306. static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
  307. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  308. {
  309. int retval;
  310. struct at91sam9_nand *info = nand->controller_priv;
  311. struct target *target = nand->target;
  312. uint8_t *oob_data;
  313. uint32_t status;
  314. retval = at91sam9_ecc_init(target, info);
  315. if (ERROR_OK != retval)
  316. return retval;
  317. retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
  318. if (ERROR_OK != retval)
  319. return retval;
  320. if (data) {
  321. retval = nand_read_data_page(nand, data, data_size);
  322. if (ERROR_OK != retval)
  323. return retval;
  324. }
  325. oob_data = at91sam9_oob_init(nand, oob, &oob_size);
  326. retval = nand_read_data_page(nand, oob_data, oob_size);
  327. if (ERROR_OK == retval && data) {
  328. target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
  329. if (status & 1) {
  330. LOG_ERROR("Error detected!");
  331. if (status & 4)
  332. LOG_ERROR("Multiple errors encountered; unrecoverable!");
  333. else {
  334. /* attempt recovery */
  335. uint32_t parity;
  336. target_read_u32(target,
  337. info->ecc + AT91C_ECCx_PR,
  338. &parity);
  339. uint32_t word = (parity & 0x0000FFF0) >> 4;
  340. uint32_t bit = parity & 0x0F;
  341. data[word] ^= (0x1) << bit;
  342. LOG_INFO("Data word %d, bit %d corrected.",
  343. (unsigned) word,
  344. (unsigned) bit);
  345. }
  346. }
  347. if (status & 2) {
  348. /* we could write back correct ECC data */
  349. LOG_ERROR("Error in ECC bytes detected");
  350. }
  351. }
  352. if (!oob) {
  353. /* if it wasn't asked for, free it */
  354. free(oob_data);
  355. }
  356. return retval;
  357. }
  358. /**
  359. * Write a page of data including 1-bit ECC information to a NAND device
  360. * attached to an AT91SAM9 controller. If there is OOB data to be written,
  361. * this will ignore the computed ECC from the ECC controller.
  362. *
  363. * @param nand NAND device to write to.
  364. * @param page Page to write.
  365. * @param data Pointer to data being written.
  366. * @param data_size Size of the data being written.
  367. * @param oob Pointer to OOB data being written.
  368. * @param oob_size Size of the OOB data.
  369. * @return Success or failure of the page write.
  370. */
  371. static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
  372. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  373. {
  374. struct at91sam9_nand *info = nand->controller_priv;
  375. struct target *target = nand->target;
  376. int retval;
  377. uint8_t *oob_data = oob;
  378. uint32_t parity, nparity;
  379. retval = at91sam9_ecc_init(target, info);
  380. if (ERROR_OK != retval)
  381. return retval;
  382. retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
  383. if (ERROR_OK != retval)
  384. return retval;
  385. if (data) {
  386. retval = nand_write_data_page(nand, data, data_size);
  387. if (ERROR_OK != retval) {
  388. LOG_ERROR("Unable to write data to NAND device");
  389. return retval;
  390. }
  391. }
  392. oob_data = at91sam9_oob_init(nand, oob, &oob_size);
  393. if (!oob) {
  394. /* no OOB given, so read in the ECC parity from the ECC controller */
  395. target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
  396. target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
  397. oob_data[0] = (uint8_t) parity;
  398. oob_data[1] = (uint8_t) (parity >> 8);
  399. oob_data[2] = (uint8_t) nparity;
  400. oob_data[3] = (uint8_t) (nparity >> 8);
  401. }
  402. retval = nand_write_data_page(nand, oob_data, oob_size);
  403. if (!oob)
  404. free(oob_data);
  405. if (ERROR_OK != retval) {
  406. LOG_ERROR("Unable to write OOB data to NAND");
  407. return retval;
  408. }
  409. retval = nand_write_finish(nand);
  410. return retval;
  411. }
  412. /**
  413. * Handle the initial NAND device command for AT91SAM9 controllers. This
  414. * initializes much of the controller information struct to be ready for future
  415. * reads and writes.
  416. */
  417. NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
  418. {
  419. unsigned long chip = 0, ecc = 0;
  420. struct at91sam9_nand *info = NULL;
  421. LOG_DEBUG("AT91SAM9 NAND Device Command");
  422. if (CMD_ARGC < 3 || CMD_ARGC > 4) {
  423. LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
  424. return ERROR_NAND_OPERATION_FAILED;
  425. }
  426. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
  427. if (chip == 0) {
  428. LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
  429. return ERROR_NAND_OPERATION_FAILED;
  430. }
  431. if (CMD_ARGC == 4) {
  432. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
  433. if (ecc == 0) {
  434. LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
  435. return ERROR_NAND_OPERATION_FAILED;
  436. }
  437. }
  438. info = calloc(1, sizeof(*info));
  439. if (!info) {
  440. LOG_ERROR("unable to allocate space for controller private data");
  441. return ERROR_NAND_OPERATION_FAILED;
  442. }
  443. info->data = chip;
  444. info->cmd = chip | (1 << 22);
  445. info->addr = chip | (1 << 21);
  446. info->ecc = ecc;
  447. nand->controller_priv = info;
  448. info->io.target = nand->target;
  449. info->io.data = info->data;
  450. info->io.op = ARM_NAND_NONE;
  451. return ERROR_OK;
  452. }
  453. /**
  454. * Handle the AT91SAM9 CLE command for specifying the address line to use for
  455. * writing commands to a NAND device.
  456. */
  457. COMMAND_HANDLER(handle_at91sam9_cle_command)
  458. {
  459. struct nand_device *nand = NULL;
  460. struct at91sam9_nand *info = NULL;
  461. unsigned num, address_line;
  462. if (CMD_ARGC != 2) {
  463. command_print(CMD_CTX, "incorrect number of arguments for 'at91sam9 cle' command");
  464. return ERROR_OK;
  465. }
  466. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  467. nand = get_nand_device_by_num(num);
  468. if (!nand) {
  469. command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
  470. return ERROR_OK;
  471. }
  472. info = nand->controller_priv;
  473. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
  474. info->cmd = info->data | (1 << address_line);
  475. return ERROR_OK;
  476. }
  477. /**
  478. * Handle the AT91SAM9 ALE command for specifying the address line to use for
  479. * writing addresses to the NAND device.
  480. */
  481. COMMAND_HANDLER(handle_at91sam9_ale_command)
  482. {
  483. struct nand_device *nand = NULL;
  484. struct at91sam9_nand *info = NULL;
  485. unsigned num, address_line;
  486. if (CMD_ARGC != 2)
  487. return ERROR_COMMAND_SYNTAX_ERROR;
  488. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  489. nand = get_nand_device_by_num(num);
  490. if (!nand) {
  491. command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
  492. return ERROR_COMMAND_ARGUMENT_INVALID;
  493. }
  494. info = nand->controller_priv;
  495. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
  496. info->addr = info->data | (1 << address_line);
  497. return ERROR_OK;
  498. }
  499. /**
  500. * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
  501. * RDY/~BUSY line from the NAND device.
  502. */
  503. COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
  504. {
  505. struct nand_device *nand = NULL;
  506. struct at91sam9_nand *info = NULL;
  507. unsigned num, base_pioc, pin_num;
  508. if (CMD_ARGC != 3)
  509. return ERROR_COMMAND_SYNTAX_ERROR;
  510. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  511. nand = get_nand_device_by_num(num);
  512. if (!nand) {
  513. command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
  514. return ERROR_COMMAND_ARGUMENT_INVALID;
  515. }
  516. info = nand->controller_priv;
  517. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
  518. info->busy.pioc = base_pioc;
  519. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
  520. info->busy.num = pin_num;
  521. return ERROR_OK;
  522. }
  523. /**
  524. * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
  525. * or disable the NAND device.
  526. */
  527. COMMAND_HANDLER(handle_at91sam9_ce_command)
  528. {
  529. struct nand_device *nand = NULL;
  530. struct at91sam9_nand *info = NULL;
  531. unsigned num, base_pioc, pin_num;
  532. if (CMD_ARGC != 3)
  533. return ERROR_COMMAND_SYNTAX_ERROR;
  534. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  535. nand = get_nand_device_by_num(num);
  536. if (!nand) {
  537. command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
  538. return ERROR_COMMAND_ARGUMENT_INVALID;
  539. }
  540. info = nand->controller_priv;
  541. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
  542. info->ce.pioc = base_pioc;
  543. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
  544. info->ce.num = pin_num;
  545. return ERROR_OK;
  546. }
  547. static const struct command_registration at91sam9_sub_command_handlers[] = {
  548. {
  549. .name = "cle",
  550. .handler = handle_at91sam9_cle_command,
  551. .mode = COMMAND_CONFIG,
  552. .help = "set command latch enable address line (default is 22)",
  553. .usage = "bank_id address_line",
  554. },
  555. {
  556. .name = "ale",
  557. .handler = handle_at91sam9_ale_command,
  558. .mode = COMMAND_CONFIG,
  559. .help = "set address latch enable address line (default is 21)",
  560. .usage = "bank_id address_line",
  561. },
  562. {
  563. .name = "rdy_busy",
  564. .handler = handle_at91sam9_rdy_busy_command,
  565. .mode = COMMAND_CONFIG,
  566. .help = "set the GPIO input pin connected to "
  567. "the RDY/~BUSY signal (no default)",
  568. .usage = "bank_id pio_base_addr pin_num",
  569. },
  570. {
  571. .name = "ce",
  572. .handler = handle_at91sam9_ce_command,
  573. .mode = COMMAND_CONFIG,
  574. .help = "set the GPIO output pin connected to "
  575. "the chip enable signal (no default)",
  576. .usage = "bank_id pio_base_addr pin_num",
  577. },
  578. COMMAND_REGISTRATION_DONE
  579. };
  580. static const struct command_registration at91sam9_command_handler[] = {
  581. {
  582. .name = "at91sam9",
  583. .mode = COMMAND_ANY,
  584. .help = "AT91SAM9 NAND flash controller commands",
  585. .usage = "",
  586. .chain = at91sam9_sub_command_handlers,
  587. },
  588. COMMAND_REGISTRATION_DONE
  589. };
  590. /**
  591. * Structure representing the AT91SAM9 NAND controller.
  592. */
  593. struct nand_flash_controller at91sam9_nand_controller = {
  594. .name = "at91sam9",
  595. .nand_device_command = at91sam9_nand_device_command,
  596. .commands = at91sam9_command_handler,
  597. .init = at91sam9_init,
  598. .command = at91sam9_command,
  599. .reset = at91sam9_reset,
  600. .address = at91sam9_address,
  601. .read_data = at91sam9_read_data,
  602. .write_data = at91sam9_write_data,
  603. .nand_ready = at91sam9_nand_ready,
  604. .read_block_data = at91sam9_read_block_data,
  605. .write_block_data = at91sam9_write_block_data,
  606. .read_page = at91sam9_read_page,
  607. .write_page = at91sam9_write_page,
  608. };