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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
  3. * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
  4. * *
  5. * Partially based on linux/include/linux/mtd/nand.h *
  6. * Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
  7. * Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
  8. * Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
  9. * *
  10. * This program is free software; you can redistribute it and/or modify *
  11. * it under the terms of the GNU General Public License as published by *
  12. * the Free Software Foundation; either version 2 of the License, or *
  13. * (at your option) any later version. *
  14. * *
  15. * This program is distributed in the hope that it will be useful, *
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  18. * GNU General Public License for more details. *
  19. * *
  20. * You should have received a copy of the GNU General Public License *
  21. * along with this program; if not, write to the *
  22. * Free Software Foundation, Inc., *
  23. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  24. ***************************************************************************/
  25. #ifndef FLASH_NAND_CORE_H
  26. #define FLASH_NAND_CORE_H
  27. #include <flash/common.h>
  28. /**
  29. * Representation of a single NAND block in a NAND device.
  30. */
  31. struct nand_block {
  32. /** Offset to the block. */
  33. uint32_t offset;
  34. /** Size of the block. */
  35. uint32_t size;
  36. /** True if the block has been erased. */
  37. int is_erased;
  38. /** True if the block is bad. */
  39. int is_bad;
  40. };
  41. struct nand_oobfree {
  42. int offset;
  43. int length;
  44. };
  45. struct nand_ecclayout {
  46. int eccbytes;
  47. int eccpos[64];
  48. int oobavail;
  49. struct nand_oobfree oobfree[2];
  50. };
  51. struct nand_device {
  52. const char *name;
  53. struct target *target;
  54. struct nand_flash_controller *controller;
  55. void *controller_priv;
  56. struct nand_manufacturer *manufacturer;
  57. struct nand_info *device;
  58. int bus_width;
  59. int address_cycles;
  60. int page_size;
  61. int erase_size;
  62. int use_raw;
  63. int num_blocks;
  64. struct nand_block *blocks;
  65. struct nand_device *next;
  66. };
  67. /* NAND Flash Manufacturer ID Codes
  68. */
  69. enum {
  70. NAND_MFR_TOSHIBA = 0x98,
  71. NAND_MFR_SAMSUNG = 0xec,
  72. NAND_MFR_FUJITSU = 0x04,
  73. NAND_MFR_NATIONAL = 0x8f,
  74. NAND_MFR_RENESAS = 0x07,
  75. NAND_MFR_STMICRO = 0x20,
  76. NAND_MFR_HYNIX = 0xad,
  77. NAND_MFR_MICRON = 0x2c,
  78. };
  79. struct nand_manufacturer {
  80. int id;
  81. const char *name;
  82. };
  83. struct nand_info {
  84. int mfr_id;
  85. int id;
  86. int page_size;
  87. int chip_size;
  88. int erase_size;
  89. int options;
  90. const char *name;
  91. };
  92. /* Option constants for bizarre disfunctionality and real features
  93. */
  94. enum {
  95. /* Chip can not auto increment pages */
  96. NAND_NO_AUTOINCR = 0x00000001,
  97. /* Buswitdh is 16 bit */
  98. NAND_BUSWIDTH_16 = 0x00000002,
  99. /* Device supports partial programming without padding */
  100. NAND_NO_PADDING = 0x00000004,
  101. /* Chip has cache program function */
  102. NAND_CACHEPRG = 0x00000008,
  103. /* Chip has copy back function */
  104. NAND_COPYBACK = 0x00000010,
  105. /* AND Chip which has 4 banks and a confusing page / block
  106. * assignment. See Renesas datasheet for further information */
  107. NAND_IS_AND = 0x00000020,
  108. /* Chip has a array of 4 pages which can be read without
  109. * additional ready /busy waits */
  110. NAND_4PAGE_ARRAY = 0x00000040,
  111. /* Chip requires that BBT is periodically rewritten to prevent
  112. * bits from adjacent blocks from 'leaking' in altering data.
  113. * This happens with the Renesas AG-AND chips, possibly others. */
  114. BBT_AUTO_REFRESH = 0x00000080,
  115. /* Chip does not require ready check on read. True
  116. * for all large page devices, as they do not support
  117. * autoincrement.*/
  118. NAND_NO_READRDY = 0x00000100,
  119. /* Options valid for Samsung large page devices */
  120. NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
  121. /* Options for new chips with large page size. The pagesize and the
  122. * erasesize is determined from the extended id bytes
  123. */
  124. LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
  125. LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
  126. };
  127. enum {
  128. /* Standard NAND flash commands */
  129. NAND_CMD_READ0 = 0x0,
  130. NAND_CMD_READ1 = 0x1,
  131. NAND_CMD_RNDOUT = 0x5,
  132. NAND_CMD_PAGEPROG = 0x10,
  133. NAND_CMD_READOOB = 0x50,
  134. NAND_CMD_ERASE1 = 0x60,
  135. NAND_CMD_STATUS = 0x70,
  136. NAND_CMD_STATUS_MULTI = 0x71,
  137. NAND_CMD_SEQIN = 0x80,
  138. NAND_CMD_RNDIN = 0x85,
  139. NAND_CMD_READID = 0x90,
  140. NAND_CMD_ERASE2 = 0xd0,
  141. NAND_CMD_RESET = 0xff,
  142. /* Extended commands for large page devices */
  143. NAND_CMD_READSTART = 0x30,
  144. NAND_CMD_RNDOUTSTART = 0xE0,
  145. NAND_CMD_CACHEDPROG = 0x15,
  146. };
  147. /* Status bits */
  148. enum {
  149. NAND_STATUS_FAIL = 0x01,
  150. NAND_STATUS_FAIL_N1 = 0x02,
  151. NAND_STATUS_TRUE_READY = 0x20,
  152. NAND_STATUS_READY = 0x40,
  153. NAND_STATUS_WP = 0x80,
  154. };
  155. /* OOB (spare) data formats */
  156. enum oob_formats {
  157. NAND_OOB_NONE = 0x0, /* no OOB data at all */
  158. NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for
  159. *2048b page sizes) */
  160. NAND_OOB_ONLY = 0x2, /* only OOB data */
  161. NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
  162. NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
  163. NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
  164. NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
  165. NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
  166. };
  167. struct nand_device *get_nand_device_by_num(int num);
  168. int nand_page_command(struct nand_device *nand, uint32_t page,
  169. uint8_t cmd, bool oob_only);
  170. int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
  171. int nand_write_data_page(struct nand_device *nand,
  172. uint8_t *data, uint32_t size);
  173. int nand_write_finish(struct nand_device *nand);
  174. int nand_read_page_raw(struct nand_device *nand, uint32_t page,
  175. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  176. int nand_write_page_raw(struct nand_device *nand, uint32_t page,
  177. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  178. int nand_read_status(struct nand_device *nand, uint8_t *status);
  179. int nand_calculate_ecc(struct nand_device *nand,
  180. const uint8_t *dat, uint8_t *ecc_code);
  181. int nand_calculate_ecc_kw(struct nand_device *nand,
  182. const uint8_t *dat, uint8_t *ecc_code);
  183. int nand_register_commands(struct command_context *cmd_ctx);
  184. /** helper for parsing a nand device command argument string */
  185. COMMAND_HELPER(nand_command_get_device, unsigned name_index,
  186. struct nand_device **nand);
  187. #define ERROR_NAND_DEVICE_INVALID (-1100)
  188. #define ERROR_NAND_OPERATION_FAILED (-1101)
  189. #define ERROR_NAND_OPERATION_TIMEOUT (-1102)
  190. #define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
  191. #define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
  192. #define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
  193. #define ERROR_NAND_NO_BUFFER (-1106)
  194. #endif /* FLASH_NAND_CORE_H */