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  1. /***************************************************************************
  2. * Copyright (C) 2009 by David Brownell *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  18. ***************************************************************************/
  19. /*
  20. * DaVinci family NAND controller support for OpenOCD.
  21. *
  22. * This driver uses hardware ECC (1-bit or 4-bit) unless
  23. * the chip is accessed in "raw" mode.
  24. */
  25. #ifdef HAVE_CONFIG_H
  26. #include "config.h"
  27. #endif
  28. #include "imp.h"
  29. #include "arm_io.h"
  30. #include <target/target.h>
  31. enum ecc {
  32. HWECC1, /* all controllers support 1-bit ECC */
  33. HWECC4, /* newer chips also have 4-bit ECC hardware */
  34. HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
  35. };
  36. struct davinci_nand {
  37. uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
  38. uint8_t eccmode;
  39. /* Async EMIF controller base */
  40. uint32_t aemif;
  41. /* NAND chip addresses */
  42. uint32_t data; /* without CLE or ALE */
  43. uint32_t cmd; /* with CLE */
  44. uint32_t addr; /* with ALE */
  45. /* write acceleration */
  46. struct arm_nand_data io;
  47. /* page i/o for the relevant flavor of hardware ECC */
  48. int (*read_page)(struct nand_device *nand, uint32_t page,
  49. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  50. int (*write_page)(struct nand_device *nand, uint32_t page,
  51. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  52. };
  53. #define NANDFCR 0x60 /* flash control register */
  54. #define NANDFSR 0x64 /* flash status register */
  55. #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
  56. #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
  57. #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
  58. #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
  59. #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
  60. static int halted(struct target *target, const char *label)
  61. {
  62. if (target->state == TARGET_HALTED)
  63. return true;
  64. LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  65. return false;
  66. }
  67. static int davinci_init(struct nand_device *nand)
  68. {
  69. struct davinci_nand *info = nand->controller_priv;
  70. struct target *target = nand->target;
  71. uint32_t nandfcr;
  72. if (!halted(target, "init"))
  73. return ERROR_NAND_OPERATION_FAILED;
  74. /* We require something else to have configured AEMIF to talk
  75. * to NAND chip in this range (including timings and width).
  76. */
  77. target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
  78. if (!(nandfcr & (1 << info->chipsel))) {
  79. LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
  80. return ERROR_NAND_OPERATION_FAILED;
  81. }
  82. /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
  83. * tested. 16 bit support should work too; but not with 4-bit ECC.
  84. */
  85. return ERROR_OK;
  86. }
  87. static int davinci_reset(struct nand_device *nand)
  88. {
  89. return ERROR_OK;
  90. }
  91. static int davinci_nand_ready(struct nand_device *nand, int timeout)
  92. {
  93. struct davinci_nand *info = nand->controller_priv;
  94. struct target *target = nand->target;
  95. uint32_t nandfsr;
  96. /* NOTE: return code is zero/error, else success; not ERROR_* */
  97. if (!halted(target, "ready"))
  98. return 0;
  99. do {
  100. target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
  101. if (nandfsr & 0x01)
  102. return 1;
  103. alive_sleep(1);
  104. } while (timeout-- > 0);
  105. return 0;
  106. }
  107. static int davinci_command(struct nand_device *nand, uint8_t command)
  108. {
  109. struct davinci_nand *info = nand->controller_priv;
  110. struct target *target = nand->target;
  111. if (!halted(target, "command"))
  112. return ERROR_NAND_OPERATION_FAILED;
  113. target_write_u8(target, info->cmd, command);
  114. return ERROR_OK;
  115. }
  116. static int davinci_address(struct nand_device *nand, uint8_t address)
  117. {
  118. struct davinci_nand *info = nand->controller_priv;
  119. struct target *target = nand->target;
  120. if (!halted(target, "address"))
  121. return ERROR_NAND_OPERATION_FAILED;
  122. target_write_u8(target, info->addr, address);
  123. return ERROR_OK;
  124. }
  125. static int davinci_write_data(struct nand_device *nand, uint16_t data)
  126. {
  127. struct davinci_nand *info = nand->controller_priv;
  128. struct target *target = nand->target;
  129. if (!halted(target, "write_data"))
  130. return ERROR_NAND_OPERATION_FAILED;
  131. target_write_u8(target, info->data, data);
  132. return ERROR_OK;
  133. }
  134. static int davinci_read_data(struct nand_device *nand, void *data)
  135. {
  136. struct davinci_nand *info = nand->controller_priv;
  137. struct target *target = nand->target;
  138. if (!halted(target, "read_data"))
  139. return ERROR_NAND_OPERATION_FAILED;
  140. target_read_u8(target, info->data, data);
  141. return ERROR_OK;
  142. }
  143. /* REVISIT a bit of native code should let block reads be MUCH faster */
  144. static int davinci_read_block_data(struct nand_device *nand,
  145. uint8_t *data, int data_size)
  146. {
  147. struct davinci_nand *info = nand->controller_priv;
  148. struct target *target = nand->target;
  149. uint32_t nfdata = info->data;
  150. uint32_t tmp;
  151. if (!halted(target, "read_block"))
  152. return ERROR_NAND_OPERATION_FAILED;
  153. while (data_size >= 4) {
  154. target_read_u32(target, nfdata, &tmp);
  155. data[0] = tmp;
  156. data[1] = tmp >> 8;
  157. data[2] = tmp >> 16;
  158. data[3] = tmp >> 24;
  159. data_size -= 4;
  160. data += 4;
  161. }
  162. while (data_size > 0) {
  163. target_read_u8(target, nfdata, data);
  164. data_size -= 1;
  165. data += 1;
  166. }
  167. return ERROR_OK;
  168. }
  169. static int davinci_write_block_data(struct nand_device *nand,
  170. uint8_t *data, int data_size)
  171. {
  172. struct davinci_nand *info = nand->controller_priv;
  173. struct target *target = nand->target;
  174. uint32_t nfdata = info->data;
  175. uint32_t tmp;
  176. int status;
  177. if (!halted(target, "write_block"))
  178. return ERROR_NAND_OPERATION_FAILED;
  179. /* try the fast way first */
  180. status = arm_nandwrite(&info->io, data, data_size);
  181. if (status != ERROR_NAND_NO_BUFFER)
  182. return status;
  183. /* else do it slowly */
  184. while (data_size >= 4) {
  185. tmp = le_to_h_u32(data);
  186. target_write_u32(target, nfdata, tmp);
  187. data_size -= 4;
  188. data += 4;
  189. }
  190. while (data_size > 0) {
  191. target_write_u8(target, nfdata, *data);
  192. data_size -= 1;
  193. data += 1;
  194. }
  195. return ERROR_OK;
  196. }
  197. static int davinci_write_page(struct nand_device *nand, uint32_t page,
  198. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  199. {
  200. struct davinci_nand *info = nand->controller_priv;
  201. uint8_t *ooballoc = NULL;
  202. int status;
  203. if (!nand->device)
  204. return ERROR_NAND_DEVICE_NOT_PROBED;
  205. if (!halted(nand->target, "write_page"))
  206. return ERROR_NAND_OPERATION_FAILED;
  207. /* Always write both data and OOB ... we are not "raw" I/O! */
  208. if (!data) {
  209. LOG_ERROR("Missing NAND data; try 'nand raw_access enable'");
  210. return ERROR_NAND_OPERATION_FAILED;
  211. }
  212. /* If we're not given OOB, write 0xff where we don't write ECC codes. */
  213. switch (nand->page_size) {
  214. case 512:
  215. oob_size = 16;
  216. break;
  217. case 2048:
  218. oob_size = 64;
  219. break;
  220. case 4096:
  221. oob_size = 128;
  222. break;
  223. default:
  224. return ERROR_NAND_OPERATION_FAILED;
  225. }
  226. if (!oob) {
  227. ooballoc = malloc(oob_size);
  228. if (!ooballoc)
  229. return ERROR_NAND_OPERATION_FAILED;
  230. oob = ooballoc;
  231. memset(oob, 0x0ff, oob_size);
  232. }
  233. /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
  234. * use 512 byte chunks. Read side support will often want
  235. * to include oob_size ...
  236. */
  237. info->io.chunk_size = nand->page_size;
  238. status = info->write_page(nand, page, data, data_size, oob, oob_size);
  239. free(ooballoc);
  240. return status;
  241. }
  242. static int davinci_read_page(struct nand_device *nand, uint32_t page,
  243. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  244. {
  245. struct davinci_nand *info = nand->controller_priv;
  246. if (!nand->device)
  247. return ERROR_NAND_DEVICE_NOT_PROBED;
  248. if (!halted(nand->target, "read_page"))
  249. return ERROR_NAND_OPERATION_FAILED;
  250. return info->read_page(nand, page, data, data_size, oob, oob_size);
  251. }
  252. static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
  253. {
  254. struct davinci_nand *info = nand->controller_priv;
  255. struct target *target = nand->target;
  256. int page3 = nand->address_cycles - (nand->page_size == 512);
  257. /* write command ({page,otp}x{read,program} */
  258. target_write_u8(target, info->cmd, cmd);
  259. /* column address (beginning-of-page) */
  260. target_write_u8(target, info->addr, 0);
  261. if (nand->page_size > 512)
  262. target_write_u8(target, info->addr, 0);
  263. /* page address */
  264. target_write_u8(target, info->addr, page);
  265. target_write_u8(target, info->addr, page >> 8);
  266. if (page3)
  267. target_write_u8(target, info->addr, page >> 16);
  268. if (page3 == 2)
  269. target_write_u8(target, info->addr, page >> 24);
  270. }
  271. static int davinci_seek_column(struct nand_device *nand, uint16_t column)
  272. {
  273. struct davinci_nand *info = nand->controller_priv;
  274. struct target *target = nand->target;
  275. /* Random read, we must have issued a page read already */
  276. target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
  277. target_write_u8(target, info->addr, column);
  278. if (nand->page_size > 512) {
  279. target_write_u8(target, info->addr, column >> 8);
  280. target_write_u8(target, info->cmd, NAND_CMD_RNDOUTSTART);
  281. }
  282. if (!davinci_nand_ready(nand, 100))
  283. return ERROR_NAND_OPERATION_TIMEOUT;
  284. return ERROR_OK;
  285. }
  286. static int davinci_writepage_tail(struct nand_device *nand,
  287. uint8_t *oob, uint32_t oob_size)
  288. {
  289. struct davinci_nand *info = nand->controller_priv;
  290. struct target *target = nand->target;
  291. uint8_t status;
  292. if (oob_size)
  293. davinci_write_block_data(nand, oob, oob_size);
  294. /* non-cachemode page program */
  295. target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
  296. if (!davinci_nand_ready(nand, 100))
  297. return ERROR_NAND_OPERATION_TIMEOUT;
  298. if (nand_read_status(nand, &status) != ERROR_OK) {
  299. LOG_ERROR("couldn't read status");
  300. return ERROR_NAND_OPERATION_FAILED;
  301. }
  302. if (status & NAND_STATUS_FAIL) {
  303. LOG_ERROR("write operation failed, status: 0x%02x", status);
  304. return ERROR_NAND_OPERATION_FAILED;
  305. }
  306. return ERROR_OK;
  307. }
  308. /*
  309. * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
  310. */
  311. static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
  312. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  313. {
  314. unsigned oob_offset;
  315. struct davinci_nand *info = nand->controller_priv;
  316. struct target *target = nand->target;
  317. const uint32_t fcr_addr = info->aemif + NANDFCR;
  318. const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
  319. uint32_t fcr, ecc1;
  320. /* Write contiguous ECC bytes starting at specified offset.
  321. * NOTE: Linux reserves twice as many bytes as we need; and
  322. * for 16-bit OOB, those extra bytes are discontiguous.
  323. */
  324. switch (nand->page_size) {
  325. case 512:
  326. oob_offset = 0;
  327. break;
  328. case 2048:
  329. oob_offset = 40;
  330. break;
  331. default:
  332. oob_offset = 80;
  333. break;
  334. }
  335. davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
  336. /* scrub any old ECC state */
  337. target_read_u32(target, ecc1_addr, &ecc1);
  338. target_read_u32(target, fcr_addr, &fcr);
  339. fcr |= 1 << (8 + info->chipsel);
  340. do {
  341. /* set "start csX 1bit ecc" bit */
  342. target_write_u32(target, fcr_addr, fcr);
  343. /* write 512 bytes */
  344. davinci_write_block_data(nand, data, 512);
  345. data += 512;
  346. data_size -= 512;
  347. /* read the ecc, pack to 3 bytes, and invert so the ecc
  348. * in an erased block is correct
  349. */
  350. target_read_u32(target, ecc1_addr, &ecc1);
  351. ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
  352. ecc1 = ~ecc1;
  353. /* save correct ECC code into oob data */
  354. oob[oob_offset++] = (uint8_t)(ecc1);
  355. oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
  356. oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
  357. } while (data_size);
  358. /* write OOB into spare area */
  359. return davinci_writepage_tail(nand, oob, oob_size);
  360. }
  361. /*
  362. * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
  363. * slows down large page reads done with error correction (since the OOB
  364. * is read first, so its ECC data can be used incrementally), but the
  365. * manufacturer bad block markers are safe. Contrast: old "infix" style.
  366. */
  367. static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
  368. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  369. {
  370. static const uint8_t ecc512[] = {
  371. 0, 1, 2, 3, 4, /* 5== mfr badblock */
  372. 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
  373. };
  374. static const uint8_t ecc2048[] = {
  375. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
  376. 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
  377. 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
  378. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  379. };
  380. static const uint8_t ecc4096[] = {
  381. 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
  382. 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
  383. 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
  384. 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
  385. 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
  386. 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
  387. 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
  388. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  389. };
  390. struct davinci_nand *info = nand->controller_priv;
  391. const uint8_t *l;
  392. struct target *target = nand->target;
  393. const uint32_t fcr_addr = info->aemif + NANDFCR;
  394. const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
  395. uint32_t fcr, ecc4;
  396. /* Use the same ECC layout Linux uses. For small page chips
  397. * it's a bit cramped.
  398. *
  399. * NOTE: at this writing, 4KB pages have issues in Linux
  400. * because they need more than 64 bytes of ECC data, which
  401. * the standard ECC logic can't handle.
  402. */
  403. switch (nand->page_size) {
  404. case 512:
  405. l = ecc512;
  406. break;
  407. case 2048:
  408. l = ecc2048;
  409. break;
  410. default:
  411. l = ecc4096;
  412. break;
  413. }
  414. davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
  415. /* scrub any old ECC state */
  416. target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
  417. target_read_u32(target, fcr_addr, &fcr);
  418. fcr &= ~(0x03 << 4);
  419. fcr |= (1 << 12) | (info->chipsel << 4);
  420. do {
  421. uint32_t raw_ecc[4], *p;
  422. int i;
  423. /* start 4bit ecc on csX */
  424. target_write_u32(target, fcr_addr, fcr);
  425. /* write 512 bytes */
  426. davinci_write_block_data(nand, data, 512);
  427. data += 512;
  428. data_size -= 512;
  429. /* read the ecc, then save it into 10 bytes in the oob */
  430. for (i = 0; i < 4; i++) {
  431. target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
  432. raw_ecc[i] &= 0x03ff03ff;
  433. }
  434. for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
  435. oob[*l++] = p[0] & 0xff;
  436. oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
  437. oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
  438. oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
  439. oob[*l++] = (p[1] >> 18) & 0xff;
  440. }
  441. } while (data_size);
  442. /* write OOB into spare area */
  443. return davinci_writepage_tail(nand, oob, oob_size);
  444. }
  445. /*
  446. * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
  447. * manufacturer bad block markers, except on small page chips. Once you
  448. * write to a page using this scheme, you need specialized code to update
  449. * it (code which ignores now-invalid bad block markers).
  450. *
  451. * This is needed *only* to support older firmware. Older ROM Boot Loaders
  452. * need it to read their second stage loader (UBL) into SRAM, but from then
  453. * on the whole system can use the cleaner non-infix layouts. Systems with
  454. * older second stage loaders (ABL/U-Boot, etc) or other system software
  455. * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
  456. */
  457. static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
  458. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  459. {
  460. struct davinci_nand *info = nand->controller_priv;
  461. struct target *target = nand->target;
  462. const uint32_t fcr_addr = info->aemif + NANDFCR;
  463. const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
  464. uint32_t fcr, ecc4;
  465. davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
  466. /* scrub any old ECC state */
  467. target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
  468. target_read_u32(target, fcr_addr, &fcr);
  469. fcr &= ~(0x03 << 4);
  470. fcr |= (1 << 12) | (info->chipsel << 4);
  471. do {
  472. uint32_t raw_ecc[4], *p;
  473. uint8_t *l;
  474. int i;
  475. /* start 4bit ecc on csX */
  476. target_write_u32(target, fcr_addr, fcr);
  477. /* write 512 bytes */
  478. davinci_write_block_data(nand, data, 512);
  479. data += 512;
  480. data_size -= 512;
  481. /* read the ecc */
  482. for (i = 0; i < 4; i++) {
  483. target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
  484. raw_ecc[i] &= 0x03ff03ff;
  485. }
  486. /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
  487. for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
  488. *l++ = p[0] & 0xff;
  489. *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
  490. *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
  491. *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
  492. *l++ = (p[1] >> 18) & 0xff;
  493. }
  494. /* write this "out-of-band" data -- infix */
  495. davinci_write_block_data(nand, oob, 16);
  496. oob += 16;
  497. oob_size -= 16;
  498. } while (data_size);
  499. /* the last data and OOB writes included the spare area */
  500. return davinci_writepage_tail(nand, NULL, 0);
  501. }
  502. static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
  503. uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
  504. {
  505. int read_size;
  506. int want_col, at_col;
  507. int ret;
  508. davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
  509. /* large page devices need a start command */
  510. if (nand->page_size > 512)
  511. davinci_command(nand, NAND_CMD_READSTART);
  512. if (!davinci_nand_ready(nand, 100))
  513. return ERROR_NAND_OPERATION_TIMEOUT;
  514. /* NOTE: not bothering to compute and use ECC data for now */
  515. want_col = 0;
  516. at_col = 0;
  517. while ((data && data_size) || (oob && oob_size)) {
  518. if (data && data_size) {
  519. if (want_col != at_col) {
  520. /* Reads are slow, so seek past them when we can */
  521. ret = davinci_seek_column(nand, want_col);
  522. if (ret != ERROR_OK)
  523. return ret;
  524. at_col = want_col;
  525. }
  526. /* read 512 bytes or data_size, whichever is smaller*/
  527. read_size = data_size > 512 ? 512 : data_size;
  528. davinci_read_block_data(nand, data, read_size);
  529. data += read_size;
  530. data_size -= read_size;
  531. at_col += read_size;
  532. }
  533. want_col += 512;
  534. if (oob && oob_size) {
  535. if (want_col != at_col) {
  536. ret = davinci_seek_column(nand, want_col);
  537. if (ret != ERROR_OK)
  538. return ret;
  539. at_col = want_col;
  540. }
  541. /* read this "out-of-band" data -- infix */
  542. read_size = oob_size > 16 ? 16 : oob_size;
  543. davinci_read_block_data(nand, oob, read_size);
  544. oob += read_size;
  545. oob_size -= read_size;
  546. at_col += read_size;
  547. }
  548. want_col += 16;
  549. }
  550. return ERROR_OK;
  551. }
  552. NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
  553. {
  554. struct davinci_nand *info;
  555. unsigned long chip, aemif;
  556. enum ecc eccmode;
  557. int chipsel;
  558. /* arguments:
  559. * - "davinci"
  560. * - target
  561. * - nand chip address
  562. * - ecc mode
  563. * - aemif address
  564. * Plus someday, optionally, ALE and CLE masks.
  565. */
  566. if (CMD_ARGC < 5)
  567. return ERROR_COMMAND_SYNTAX_ERROR;
  568. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
  569. if (chip == 0) {
  570. LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
  571. goto fail;
  572. }
  573. if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
  574. eccmode = HWECC1;
  575. else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
  576. eccmode = HWECC4;
  577. else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
  578. eccmode = HWECC4_INFIX;
  579. else {
  580. LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
  581. goto fail;
  582. }
  583. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
  584. if (aemif == 0) {
  585. LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
  586. goto fail;
  587. }
  588. /* REVISIT what we'd *like* to do is look up valid ranges using
  589. * target-specific declarations, and not even need to pass the
  590. * AEMIF controller address.
  591. */
  592. if (aemif == 0x01e00000 /* dm6446, dm357 */
  593. || aemif == 0x01e10000 /* dm335, dm355 */
  594. || aemif == 0x01d10000 /* dm365 */
  595. ) {
  596. if (chip < 0x02000000 || chip >= 0x0a000000) {
  597. LOG_ERROR("NAND address %08lx out of range?", chip);
  598. goto fail;
  599. }
  600. chipsel = (chip - 0x02000000) >> 25;
  601. } else {
  602. LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
  603. goto fail;
  604. }
  605. info = calloc(1, sizeof *info);
  606. if (info == NULL)
  607. goto fail;
  608. info->eccmode = eccmode;
  609. info->chipsel = chipsel;
  610. info->aemif = aemif;
  611. info->data = chip;
  612. info->cmd = chip | 0x10;
  613. info->addr = chip | 0x08;
  614. nand->controller_priv = info;
  615. info->io.target = nand->target;
  616. info->io.data = info->data;
  617. info->io.op = ARM_NAND_NONE;
  618. /* NOTE: for now we don't do any error correction on read.
  619. * Nothing else in OpenOCD currently corrects read errors,
  620. * and in any case it's *writing* that we care most about.
  621. */
  622. info->read_page = nand_read_page_raw;
  623. switch (eccmode) {
  624. case HWECC1:
  625. /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
  626. info->write_page = davinci_write_page_ecc1;
  627. break;
  628. case HWECC4:
  629. /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
  630. info->write_page = davinci_write_page_ecc4;
  631. break;
  632. case HWECC4_INFIX:
  633. /* Same 4-bit ECC HW, with problematic page/ecc layout */
  634. info->read_page = davinci_read_page_ecc4infix;
  635. info->write_page = davinci_write_page_ecc4infix;
  636. break;
  637. }
  638. return ERROR_OK;
  639. fail:
  640. return ERROR_NAND_OPERATION_FAILED;
  641. }
  642. struct nand_flash_controller davinci_nand_controller = {
  643. .name = "davinci",
  644. .usage = "chip_addr hwecc_mode aemif_addr",
  645. .nand_device_command = davinci_nand_device_command,
  646. .init = davinci_init,
  647. .reset = davinci_reset,
  648. .command = davinci_command,
  649. .address = davinci_address,
  650. .write_data = davinci_write_data,
  651. .read_data = davinci_read_data,
  652. .write_page = davinci_write_page,
  653. .read_page = davinci_read_page,
  654. .write_block_data = davinci_write_block_data,
  655. .read_block_data = davinci_read_block_data,
  656. .nand_ready = davinci_nand_ready,
  657. };