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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. *
  5. * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
  6. * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "imp.h"
  27. #include "lpc3180.h"
  28. #include <target/target.h>
  29. static int lpc3180_reset(struct nand_device *nand);
  30. static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
  31. static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
  32. #define ECC_OFFS 0x120
  33. #define SPARE_OFFS 0x140
  34. #define DATA_OFFS 0x200
  35. /* nand device lpc3180 <target#> <oscillator_frequency>
  36. */
  37. NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
  38. {
  39. if (CMD_ARGC < 3)
  40. return ERROR_COMMAND_SYNTAX_ERROR;
  41. uint32_t osc_freq;
  42. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  43. struct lpc3180_nand_controller *lpc3180_info;
  44. lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
  45. nand->controller_priv = lpc3180_info;
  46. lpc3180_info->osc_freq = osc_freq;
  47. if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  48. LOG_WARNING(
  49. "LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i",
  50. lpc3180_info->osc_freq);
  51. lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  52. lpc3180_info->sw_write_protection = 0;
  53. lpc3180_info->sw_wp_lower_bound = 0x0;
  54. lpc3180_info->sw_wp_upper_bound = 0x0;
  55. return ERROR_OK;
  56. }
  57. static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
  58. {
  59. int bypass = (pll_ctrl & 0x8000) >> 15;
  60. int direct = (pll_ctrl & 0x4000) >> 14;
  61. int feedback = (pll_ctrl & 0x2000) >> 13;
  62. int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  63. int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  64. int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  65. int lock = (pll_ctrl & 0x1);
  66. if (!lock)
  67. LOG_WARNING("PLL is not locked");
  68. if (!bypass && direct) /* direct mode */
  69. return (m * fclkin) / n;
  70. if (bypass && !direct) /* bypass mode */
  71. return fclkin / (2 * p);
  72. if (bypass & direct) /* direct bypass mode */
  73. return fclkin;
  74. if (feedback) /* integer mode */
  75. return m * (fclkin / n);
  76. else /* non-integer mode */
  77. return (m / (2 * p)) * (fclkin / n);
  78. }
  79. static float lpc3180_cycle_time(struct nand_device *nand)
  80. {
  81. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  82. struct target *target = nand->target;
  83. uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
  84. int sysclk;
  85. int hclk;
  86. int hclk_pll;
  87. float cycle;
  88. /* calculate timings */
  89. /* determine current SYSCLK (13'MHz or main oscillator) */
  90. target_read_u32(target, 0x40004050, &sysclk_ctrl);
  91. if ((sysclk_ctrl & 1) == 0)
  92. sysclk = lpc3180_info->osc_freq;
  93. else
  94. sysclk = 13000;
  95. /* determine selected HCLK source */
  96. target_read_u32(target, 0x40004044, &pwr_ctrl);
  97. if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
  98. hclk = sysclk;
  99. else {
  100. target_read_u32(target, 0x40004058, &hclkpll_ctrl);
  101. hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
  102. target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
  103. if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
  104. hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
  105. else /* HCLK uses HCLK_PLL */
  106. hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
  107. }
  108. LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
  109. cycle = (1.0 / hclk) * 1000000.0;
  110. return cycle;
  111. }
  112. static int lpc3180_init(struct nand_device *nand)
  113. {
  114. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  115. struct target *target = nand->target;
  116. int bus_width = nand->bus_width ? : 8;
  117. int address_cycles = nand->address_cycles ? : 3;
  118. int page_size = nand->page_size ? : 512;
  119. if (target->state != TARGET_HALTED) {
  120. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  121. return ERROR_NAND_OPERATION_FAILED;
  122. }
  123. /* sanitize arguments */
  124. if ((bus_width != 8) && (bus_width != 16)) {
  125. LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
  126. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  127. }
  128. /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
  129. * would support 16 bit, too, so we just warn about this for now
  130. */
  131. if (bus_width == 16)
  132. LOG_WARNING("LPC3180 only supports 8 bit bus width");
  133. /* inform calling code about selected bus width */
  134. nand->bus_width = bus_width;
  135. if ((address_cycles != 3) && (address_cycles != 4)) {
  136. LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
  137. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  138. }
  139. if ((page_size != 512) && (page_size != 2048)) {
  140. LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
  141. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  142. }
  143. /* select MLC controller if none is currently selected */
  144. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  145. LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
  146. lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
  147. }
  148. if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  149. uint32_t mlc_icr_value = 0x0;
  150. float cycle;
  151. int twp, twh, trp, treh, trhz, trbwb, tcea;
  152. /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
  153. target_write_u32(target, 0x400040c8, 0x22);
  154. /* MLC_CEH = 0x0 (Force nCE assert) */
  155. target_write_u32(target, 0x200b804c, 0x0);
  156. /* MLC_LOCK = 0xa25e (unlock protected registers) */
  157. target_write_u32(target, 0x200b8044, 0xa25e);
  158. /* MLC_ICR = configuration */
  159. if (lpc3180_info->sw_write_protection)
  160. mlc_icr_value |= 0x8;
  161. if (page_size == 2048)
  162. mlc_icr_value |= 0x4;
  163. if (address_cycles == 4)
  164. mlc_icr_value |= 0x2;
  165. if (bus_width == 16)
  166. mlc_icr_value |= 0x1;
  167. target_write_u32(target, 0x200b8030, mlc_icr_value);
  168. /* calculate NAND controller timings */
  169. cycle = lpc3180_cycle_time(nand);
  170. twp = ((40 / cycle) + 1);
  171. twh = ((20 / cycle) + 1);
  172. trp = ((30 / cycle) + 1);
  173. treh = ((15 / cycle) + 1);
  174. trhz = ((30 / cycle) + 1);
  175. trbwb = ((100 / cycle) + 1);
  176. tcea = ((45 / cycle) + 1);
  177. /* MLC_LOCK = 0xa25e (unlock protected registers) */
  178. target_write_u32(target, 0x200b8044, 0xa25e);
  179. /* MLC_TIME_REG */
  180. target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
  181. ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
  182. ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
  183. lpc3180_reset(nand);
  184. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  185. float cycle;
  186. int r_setup, r_hold, r_width, r_rdy;
  187. int w_setup, w_hold, w_width, w_rdy;
  188. /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
  189. target_write_u32(target, 0x400040c8, 0x05);
  190. /* after reset set other registers of SLC so reset calling is here at the begining*/
  191. lpc3180_reset(nand);
  192. /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
  193. *DMA read from SLC, WIDTH = bus_width) */
  194. target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
  195. /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
  196. target_write_u32(target, 0x20020020, 0x03);
  197. /* DMA configuration
  198. * DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
  199. target_write_u32(target, 0x400040e8, 0x01);
  200. /* DMACConfig = DMA enabled*/
  201. target_write_u32(target, 0x31000030, 0x01);
  202. /* calculate NAND controller timings */
  203. cycle = lpc3180_cycle_time(nand);
  204. r_setup = w_setup = 0;
  205. r_hold = w_hold = 10 / cycle;
  206. r_width = 30 / cycle;
  207. w_width = 40 / cycle;
  208. r_rdy = w_rdy = 100 / cycle;
  209. /* SLC_TAC: SLC timing arcs register */
  210. target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
  211. ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
  212. ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
  213. }
  214. return ERROR_OK;
  215. }
  216. static int lpc3180_reset(struct nand_device *nand)
  217. {
  218. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  219. struct target *target = nand->target;
  220. if (target->state != TARGET_HALTED) {
  221. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  222. return ERROR_NAND_OPERATION_FAILED;
  223. }
  224. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  225. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  226. return ERROR_NAND_OPERATION_FAILED;
  227. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  228. /* MLC_CMD = 0xff (reset controller and NAND device) */
  229. target_write_u32(target, 0x200b8000, 0xff);
  230. if (!lpc3180_controller_ready(nand, 100)) {
  231. LOG_ERROR("LPC3180 NAND controller timed out after reset");
  232. return ERROR_NAND_OPERATION_TIMEOUT;
  233. }
  234. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  235. /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
  236. target_write_u32(target, 0x20020010, 0x6);
  237. if (!lpc3180_controller_ready(nand, 100)) {
  238. LOG_ERROR("LPC3180 NAND controller timed out after reset");
  239. return ERROR_NAND_OPERATION_TIMEOUT;
  240. }
  241. }
  242. return ERROR_OK;
  243. }
  244. static int lpc3180_command(struct nand_device *nand, uint8_t command)
  245. {
  246. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  247. struct target *target = nand->target;
  248. if (target->state != TARGET_HALTED) {
  249. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  250. return ERROR_NAND_OPERATION_FAILED;
  251. }
  252. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  253. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  254. return ERROR_NAND_OPERATION_FAILED;
  255. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  256. /* MLC_CMD = command */
  257. target_write_u32(target, 0x200b8000, command);
  258. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  259. /* SLC_CMD = command */
  260. target_write_u32(target, 0x20020008, command);
  261. }
  262. return ERROR_OK;
  263. }
  264. static int lpc3180_address(struct nand_device *nand, uint8_t address)
  265. {
  266. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  267. struct target *target = nand->target;
  268. if (target->state != TARGET_HALTED) {
  269. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  270. return ERROR_NAND_OPERATION_FAILED;
  271. }
  272. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  273. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  274. return ERROR_NAND_OPERATION_FAILED;
  275. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  276. /* MLC_ADDR = address */
  277. target_write_u32(target, 0x200b8004, address);
  278. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  279. /* SLC_ADDR = address */
  280. target_write_u32(target, 0x20020004, address);
  281. }
  282. return ERROR_OK;
  283. }
  284. static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
  285. {
  286. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  287. struct target *target = nand->target;
  288. if (target->state != TARGET_HALTED) {
  289. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  290. return ERROR_NAND_OPERATION_FAILED;
  291. }
  292. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  293. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  294. return ERROR_NAND_OPERATION_FAILED;
  295. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  296. /* MLC_DATA = data */
  297. target_write_u32(target, 0x200b0000, data);
  298. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  299. /* SLC_DATA = data */
  300. target_write_u32(target, 0x20020000, data);
  301. }
  302. return ERROR_OK;
  303. }
  304. static int lpc3180_read_data(struct nand_device *nand, void *data)
  305. {
  306. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  307. struct target *target = nand->target;
  308. if (target->state != TARGET_HALTED) {
  309. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  310. return ERROR_NAND_OPERATION_FAILED;
  311. }
  312. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  313. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  314. return ERROR_NAND_OPERATION_FAILED;
  315. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  316. /* data = MLC_DATA, use sized access */
  317. if (nand->bus_width == 8) {
  318. uint8_t *data8 = data;
  319. target_read_u8(target, 0x200b0000, data8);
  320. } else if (nand->bus_width == 16) {
  321. uint16_t *data16 = data;
  322. target_read_u16(target, 0x200b0000, data16);
  323. } else {
  324. LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
  325. return ERROR_NAND_OPERATION_FAILED;
  326. }
  327. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  328. uint32_t data32;
  329. /* data = SLC_DATA, must use 32-bit access */
  330. target_read_u32(target, 0x20020000, &data32);
  331. if (nand->bus_width == 8) {
  332. uint8_t *data8 = data;
  333. *data8 = data32 & 0xff;
  334. } else if (nand->bus_width == 16) {
  335. uint16_t *data16 = data;
  336. *data16 = data32 & 0xffff;
  337. } else {
  338. LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
  339. return ERROR_NAND_OPERATION_FAILED;
  340. }
  341. }
  342. return ERROR_OK;
  343. }
  344. static int lpc3180_write_page(struct nand_device *nand,
  345. uint32_t page,
  346. uint8_t *data,
  347. uint32_t data_size,
  348. uint8_t *oob,
  349. uint32_t oob_size)
  350. {
  351. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  352. struct target *target = nand->target;
  353. int retval;
  354. uint8_t status;
  355. uint8_t *page_buffer;
  356. if (target->state != TARGET_HALTED) {
  357. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  358. return ERROR_NAND_OPERATION_FAILED;
  359. }
  360. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  361. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  362. return ERROR_NAND_OPERATION_FAILED;
  363. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  364. uint8_t *oob_buffer;
  365. int quarter, num_quarters;
  366. if (!data && oob) {
  367. LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
  368. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  369. }
  370. if (oob && (oob_size > 24)) {
  371. LOG_ERROR("LPC3180 MLC controller can't write more "
  372. "than 6 bytes for each quarter's OOB data");
  373. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  374. }
  375. if (data_size > (uint32_t)nand->page_size) {
  376. LOG_ERROR("data size exceeds page size");
  377. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  378. }
  379. /* MLC_CMD = sequential input */
  380. target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
  381. page_buffer = malloc(512);
  382. oob_buffer = malloc(6);
  383. if (nand->page_size == 512) {
  384. /* MLC_ADDR = 0x0 (one column cycle) */
  385. target_write_u32(target, 0x200b8004, 0x0);
  386. /* MLC_ADDR = row */
  387. target_write_u32(target, 0x200b8004, page & 0xff);
  388. target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
  389. if (nand->address_cycles == 4)
  390. target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
  391. } else {
  392. /* MLC_ADDR = 0x0 (two column cycles) */
  393. target_write_u32(target, 0x200b8004, 0x0);
  394. target_write_u32(target, 0x200b8004, 0x0);
  395. /* MLC_ADDR = row */
  396. target_write_u32(target, 0x200b8004, page & 0xff);
  397. target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
  398. }
  399. /* when using the MLC controller, we have to treat a large page device
  400. * as being made out of four quarters, each the size of a small page device
  401. */
  402. num_quarters = (nand->page_size == 2048) ? 4 : 1;
  403. for (quarter = 0; quarter < num_quarters; quarter++) {
  404. int thisrun_data_size = (data_size > 512) ? 512 : data_size;
  405. int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
  406. memset(page_buffer, 0xff, 512);
  407. if (data) {
  408. memcpy(page_buffer, data, thisrun_data_size);
  409. data_size -= thisrun_data_size;
  410. data += thisrun_data_size;
  411. }
  412. memset(oob_buffer, 0xff, 6);
  413. if (oob) {
  414. memcpy(oob_buffer, oob, thisrun_oob_size);
  415. oob_size -= thisrun_oob_size;
  416. oob += thisrun_oob_size;
  417. }
  418. /* write MLC_ECC_ENC_REG to start encode cycle */
  419. target_write_u32(target, 0x200b8008, 0x0);
  420. target_write_memory(target, 0x200a8000,
  421. 4, 128, page_buffer);
  422. target_write_memory(target, 0x200a8000,
  423. 1, 6, oob_buffer);
  424. /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
  425. target_write_u32(target, 0x200b8010, 0x0);
  426. if (!lpc3180_controller_ready(nand, 1000)) {
  427. LOG_ERROR("timeout while waiting for completion of auto encode cycle");
  428. free(page_buffer);
  429. free(oob_buffer);
  430. return ERROR_NAND_OPERATION_FAILED;
  431. }
  432. }
  433. /* MLC_CMD = auto program command */
  434. target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
  435. retval = nand_read_status(nand, &status);
  436. if (retval != ERROR_OK) {
  437. LOG_ERROR("couldn't read status");
  438. free(page_buffer);
  439. free(oob_buffer);
  440. return ERROR_NAND_OPERATION_FAILED;
  441. }
  442. if (status & NAND_STATUS_FAIL) {
  443. LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
  444. free(page_buffer);
  445. free(oob_buffer);
  446. return ERROR_NAND_OPERATION_FAILED;
  447. }
  448. free(page_buffer);
  449. free(oob_buffer);
  450. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  451. /**********************************************************************
  452. * Write both SLC NAND flash page main area and spare area.
  453. * Small page -
  454. * ------------------------------------------
  455. * | 512 bytes main | 16 bytes spare |
  456. * ------------------------------------------
  457. * Large page -
  458. * ------------------------------------------
  459. * | 2048 bytes main | 64 bytes spare |
  460. * ------------------------------------------
  461. * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
  462. * data is written to the 3rd word of the spare area. The ECC
  463. * generated for the 2nd 256-byte data is written to the 4th word
  464. * of the spare area. The ECC generated for the 3rd 256-byte data is
  465. * written to the 7th word of the spare area. The ECC generated
  466. * for the 4th 256-byte data is written to the 8th word of the
  467. * spare area and so on.
  468. *
  469. **********************************************************************/
  470. int i = 0, target_mem_base;
  471. uint8_t *ecc_flash_buffer;
  472. struct working_area *pworking_area;
  473. if (lpc3180_info->is_bulk) {
  474. if (!data && oob) {
  475. /*if oob only mode is active original method is used as SLC
  476. *controller hangs during DMA interworking. Anyway the code supports
  477. *the oob only mode below. */
  478. return nand_write_page_raw(nand,
  479. page,
  480. data,
  481. data_size,
  482. oob,
  483. oob_size);
  484. }
  485. retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
  486. if (ERROR_OK != retval)
  487. return retval;
  488. /* allocate a working area */
  489. if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
  490. LOG_ERROR("Reserve at least 0x%x physical target working area",
  491. nand->page_size + 0x200);
  492. return ERROR_FLASH_OPERATION_FAILED;
  493. }
  494. if (target->working_area_phys%4) {
  495. LOG_ERROR(
  496. "Reserve the physical target working area at word boundary");
  497. return ERROR_FLASH_OPERATION_FAILED;
  498. }
  499. if (target_alloc_working_area(target, target->working_area_size,
  500. &pworking_area) != ERROR_OK) {
  501. LOG_ERROR("no working area specified, can't read LPC internal flash");
  502. return ERROR_FLASH_OPERATION_FAILED;
  503. }
  504. target_mem_base = target->working_area_phys;
  505. if (nand->page_size == 2048)
  506. page_buffer = malloc(2048);
  507. else
  508. page_buffer = malloc(512);
  509. ecc_flash_buffer = malloc(64);
  510. /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
  511. *enabled, DMA write to SLC, WIDTH = bus_width) */
  512. target_write_u32(target, 0x20020014, 0x3c);
  513. if (data && !oob) {
  514. /* set DMA LLI-s in target memory and in DMA*/
  515. for (i = 0; i < nand->page_size/0x100; i++) {
  516. int tmp;
  517. /* -------LLI for 256 byte block---------
  518. * DMACC0SrcAddr = SRAM */
  519. target_write_u32(target,
  520. target_mem_base+0+i*32,
  521. target_mem_base+DATA_OFFS+i*256);
  522. if (i == 0)
  523. target_write_u32(target,
  524. 0x31000100,
  525. target_mem_base+DATA_OFFS);
  526. /* DMACCxDestAddr = SLC_DMA_DATA */
  527. target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
  528. if (i == 0)
  529. target_write_u32(target, 0x31000104, 0x20020038);
  530. /* DMACCxLLI = next element */
  531. tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
  532. target_write_u32(target, target_mem_base+8+i*32, tmp);
  533. if (i == 0)
  534. target_write_u32(target, 0x31000108, tmp);
  535. /* DMACCxControl = TransferSize =64, Source burst size =16,
  536. * Destination burst size = 16, Source transfer width = 32 bit,
  537. * Destination transfer width = 32 bit, Source AHB master select = M0,
  538. * Destination AHB master select = M0, Source increment = 1,
  539. * Destination increment = 0, Terminal count interrupt enable bit = 0*/
  540. target_write_u32(target,
  541. target_mem_base+12+i*32,
  542. 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
  543. 0<<27 | 0<<31);
  544. if (i == 0)
  545. target_write_u32(target,
  546. 0x3100010c,
  547. 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
  548. 0<<27 | 0<<31);
  549. /* -------LLI for 3 byte ECC---------
  550. * DMACC0SrcAddr = SLC_ECC*/
  551. target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
  552. /* DMACCxDestAddr = SRAM */
  553. target_write_u32(target,
  554. target_mem_base+20+i*32,
  555. target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4);
  556. /* DMACCxLLI = next element */
  557. tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
  558. target_write_u32(target, target_mem_base+24+i*32, tmp);
  559. /* DMACCxControl = TransferSize =1, Source burst size =4,
  560. * Destination burst size = 4, Source transfer width = 32 bit,
  561. * Destination transfer width = 32 bit, Source AHB master select = M0,
  562. * Destination AHB master select = M0, Source increment = 0,
  563. * Destination increment = 1, Terminal count interrupt enable bit = 0*/
  564. target_write_u32(target,
  565. target_mem_base+28+i*32,
  566. 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
  567. 31);
  568. }
  569. } else if (data && oob) {
  570. /* -------LLI for 512 or 2048 bytes page---------
  571. * DMACC0SrcAddr = SRAM */
  572. target_write_u32(target, target_mem_base, target_mem_base+DATA_OFFS);
  573. target_write_u32(target, 0x31000100, target_mem_base+DATA_OFFS);
  574. /* DMACCxDestAddr = SLC_DMA_DATA */
  575. target_write_u32(target, target_mem_base+4, 0x20020038);
  576. target_write_u32(target, 0x31000104, 0x20020038);
  577. /* DMACCxLLI = next element */
  578. target_write_u32(target,
  579. target_mem_base+8,
  580. (target_mem_base+32)&0xfffffffc);
  581. target_write_u32(target, 0x31000108,
  582. (target_mem_base+32)&0xfffffffc);
  583. /* DMACCxControl = TransferSize =512 or 128, Source burst size =16,
  584. * Destination burst size = 16, Source transfer width = 32 bit,
  585. * Destination transfer width = 32 bit, Source AHB master select = M0,
  586. * Destination AHB master select = M0, Source increment = 1,
  587. * Destination increment = 0, Terminal count interrupt enable bit = 0*/
  588. target_write_u32(target,
  589. target_mem_base+12,
  590. (nand->page_size ==
  591. 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
  592. 1<<26 | 0<<27 | 0<<31);
  593. target_write_u32(target,
  594. 0x3100010c,
  595. (nand->page_size ==
  596. 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
  597. 1<<26 | 0<<27 | 0<<31);
  598. i = 1;
  599. } else if (!data && oob)
  600. i = 0;
  601. /* -------LLI for spare area---------
  602. * DMACC0SrcAddr = SRAM*/
  603. target_write_u32(target, target_mem_base+0+i*32, target_mem_base+SPARE_OFFS);
  604. if (i == 0)
  605. target_write_u32(target, 0x31000100, target_mem_base+SPARE_OFFS);
  606. /* DMACCxDestAddr = SLC_DMA_DATA */
  607. target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
  608. if (i == 0)
  609. target_write_u32(target, 0x31000104, 0x20020038);
  610. /* DMACCxLLI = next element = NULL */
  611. target_write_u32(target, target_mem_base+8+i*32, 0);
  612. if (i == 0)
  613. target_write_u32(target, 0x31000108, 0);
  614. /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
  615. * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
  616. * Destination transfer width = 32 bit, Source AHB master select = M0,
  617. * Destination AHB master select = M0, Source increment = 1,
  618. * Destination increment = 0, Terminal count interrupt enable bit = 0*/
  619. target_write_u32(target,
  620. target_mem_base+12+i*32,
  621. (nand->page_size ==
  622. 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
  623. 0<<27 | 0<<31);
  624. if (i == 0)
  625. target_write_u32(target, 0x3100010c,
  626. (nand->page_size == 2048 ?
  627. 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 |
  628. 0<<25 | 1<<26 | 0<<27 | 0<<31);
  629. memset(ecc_flash_buffer, 0xff, 64);
  630. if (oob)
  631. memcpy(ecc_flash_buffer, oob, oob_size);
  632. target_write_memory(target,
  633. target_mem_base+SPARE_OFFS,
  634. 4,
  635. 16,
  636. ecc_flash_buffer);
  637. if (data) {
  638. memset(page_buffer, 0xff, nand->page_size == 2048 ? 2048 : 512);
  639. memcpy(page_buffer, data, data_size);
  640. target_write_memory(target,
  641. target_mem_base+DATA_OFFS,
  642. 4,
  643. nand->page_size == 2048 ? 512 : 128,
  644. page_buffer);
  645. }
  646. free(page_buffer);
  647. free(ecc_flash_buffer);
  648. /* Enable DMA after channel set up !
  649. LLI only works when DMA is the flow controller!
  650. */
  651. /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
  652. *FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
  653. target_write_u32(target,
  654. 0x31000110,
  655. 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
  656. /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
  657. target_write_u32(target, 0x20020010, 0x3);
  658. /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
  659. target_write_u32(target, 0x20020028, 2);
  660. /* SLC_TC */
  661. if (!data && oob)
  662. target_write_u32(target, 0x20020030,
  663. (nand->page_size == 2048 ? 0x10 : 0x04));
  664. else
  665. target_write_u32(target, 0x20020030,
  666. (nand->page_size == 2048 ? 0x840 : 0x210));
  667. nand_write_finish(nand);
  668. if (!lpc3180_tc_ready(nand, 1000)) {
  669. LOG_ERROR("timeout while waiting for completion of DMA");
  670. return ERROR_NAND_OPERATION_FAILED;
  671. }
  672. target_free_working_area(target, pworking_area);
  673. LOG_INFO("Page = 0x%" PRIx32 " was written.", page);
  674. } else
  675. return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
  676. }
  677. return ERROR_OK;
  678. }
  679. static int lpc3180_read_page(struct nand_device *nand,
  680. uint32_t page,
  681. uint8_t *data,
  682. uint32_t data_size,
  683. uint8_t *oob,
  684. uint32_t oob_size)
  685. {
  686. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  687. struct target *target = nand->target;
  688. uint8_t *page_buffer;
  689. if (target->state != TARGET_HALTED) {
  690. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  691. return ERROR_NAND_OPERATION_FAILED;
  692. }
  693. if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
  694. LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
  695. return ERROR_NAND_OPERATION_FAILED;
  696. } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  697. uint8_t *oob_buffer;
  698. uint32_t page_bytes_done = 0;
  699. uint32_t oob_bytes_done = 0;
  700. uint32_t mlc_isr;
  701. #if 0
  702. if (oob && (oob_size > 6)) {
  703. LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
  704. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  705. }
  706. #endif
  707. if (data_size > (uint32_t)nand->page_size) {
  708. LOG_ERROR("data size exceeds page size");
  709. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  710. }
  711. if (nand->page_size == 2048) {
  712. page_buffer = malloc(2048);
  713. oob_buffer = malloc(64);
  714. } else {
  715. page_buffer = malloc(512);
  716. oob_buffer = malloc(16);
  717. }
  718. if (!data && oob) {
  719. /* MLC_CMD = Read OOB
  720. * we can use the READOOB command on both small and large page devices,
  721. * as the controller translates the 0x50 command to a 0x0 with appropriate
  722. * positioning of the serial buffer read pointer
  723. */
  724. target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
  725. } else {
  726. /* MLC_CMD = Read0 */
  727. target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
  728. }
  729. if (nand->page_size == 512) {
  730. /* small page device
  731. * MLC_ADDR = 0x0 (one column cycle) */
  732. target_write_u32(target, 0x200b8004, 0x0);
  733. /* MLC_ADDR = row */
  734. target_write_u32(target, 0x200b8004, page & 0xff);
  735. target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
  736. if (nand->address_cycles == 4)
  737. target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
  738. } else {
  739. /* large page device
  740. * MLC_ADDR = 0x0 (two column cycles) */
  741. target_write_u32(target, 0x200b8004, 0x0);
  742. target_write_u32(target, 0x200b8004, 0x0);
  743. /* MLC_ADDR = row */
  744. target_write_u32(target, 0x200b8004, page & 0xff);
  745. target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
  746. /* MLC_CMD = Read Start */
  747. target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
  748. }
  749. while (page_bytes_done < (uint32_t)nand->page_size) {
  750. /* MLC_ECC_AUTO_DEC_REG = dummy */
  751. target_write_u32(target, 0x200b8014, 0xaa55aa55);
  752. if (!lpc3180_controller_ready(nand, 1000)) {
  753. LOG_ERROR("timeout while waiting for completion of auto decode cycle");
  754. free(page_buffer);
  755. free(oob_buffer);
  756. return ERROR_NAND_OPERATION_FAILED;
  757. }
  758. target_read_u32(target, 0x200b8048, &mlc_isr);
  759. if (mlc_isr & 0x8) {
  760. if (mlc_isr & 0x40) {
  761. LOG_ERROR("uncorrectable error detected: 0x%2.2x",
  762. (unsigned)mlc_isr);
  763. free(page_buffer);
  764. free(oob_buffer);
  765. return ERROR_NAND_OPERATION_FAILED;
  766. }
  767. LOG_WARNING("%i symbol error detected and corrected",
  768. ((int)(((mlc_isr & 0x30) >> 4) + 1)));
  769. }
  770. if (data)
  771. target_read_memory(target,
  772. 0x200a8000,
  773. 4,
  774. 128,
  775. page_buffer + page_bytes_done);
  776. if (oob)
  777. target_read_memory(target,
  778. 0x200a8000,
  779. 4,
  780. 4,
  781. oob_buffer + oob_bytes_done);
  782. page_bytes_done += 512;
  783. oob_bytes_done += 16;
  784. }
  785. if (data)
  786. memcpy(data, page_buffer, data_size);
  787. if (oob)
  788. memcpy(oob, oob_buffer, oob_size);
  789. free(page_buffer);
  790. free(oob_buffer);
  791. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  792. /**********************************************************************
  793. * Read both SLC NAND flash page main area and spare area.
  794. * Small page -
  795. * ------------------------------------------
  796. * | 512 bytes main | 16 bytes spare |
  797. * ------------------------------------------
  798. * Large page -
  799. * ------------------------------------------
  800. * | 2048 bytes main | 64 bytes spare |
  801. * ------------------------------------------
  802. * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
  803. * data is compared with the 3rd word of the spare area. The ECC
  804. * generated for the 2nd 256-byte data is compared with the 4th word
  805. * of the spare area. The ECC generated for the 3rd 256-byte data is
  806. * compared with the 7th word of the spare area. The ECC generated
  807. * for the 4th 256-byte data is compared with the 8th word of the
  808. * spare area and so on.
  809. *
  810. **********************************************************************/
  811. int retval, i, target_mem_base;
  812. uint8_t *ecc_hw_buffer;
  813. uint8_t *ecc_flash_buffer;
  814. struct working_area *pworking_area;
  815. if (lpc3180_info->is_bulk) {
  816. /* read always the data and also oob areas*/
  817. retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
  818. if (ERROR_OK != retval)
  819. return retval;
  820. /* allocate a working area */
  821. if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
  822. LOG_ERROR("Reserve at least 0x%x physical target working area",
  823. nand->page_size + 0x200);
  824. return ERROR_FLASH_OPERATION_FAILED;
  825. }
  826. if (target->working_area_phys%4) {
  827. LOG_ERROR(
  828. "Reserve the physical target working area at word boundary");
  829. return ERROR_FLASH_OPERATION_FAILED;
  830. }
  831. if (target_alloc_working_area(target, target->working_area_size,
  832. &pworking_area) != ERROR_OK) {
  833. LOG_ERROR("no working area specified, can't read LPC internal flash");
  834. return ERROR_FLASH_OPERATION_FAILED;
  835. }
  836. target_mem_base = target->working_area_phys;
  837. if (nand->page_size == 2048)
  838. page_buffer = malloc(2048);
  839. else
  840. page_buffer = malloc(512);
  841. ecc_hw_buffer = malloc(32);
  842. ecc_flash_buffer = malloc(64);
  843. /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
  844. *enabled, DMA read from SLC, WIDTH = bus_width) */
  845. target_write_u32(target, 0x20020014, 0x3e);
  846. /* set DMA LLI-s in target memory and in DMA*/
  847. for (i = 0; i < nand->page_size/0x100; i++) {
  848. int tmp;
  849. /* -------LLI for 256 byte block---------
  850. * DMACC0SrcAddr = SLC_DMA_DATA*/
  851. target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
  852. if (i == 0)
  853. target_write_u32(target, 0x31000100, 0x20020038);
  854. /* DMACCxDestAddr = SRAM */
  855. target_write_u32(target,
  856. target_mem_base+4+i*32,
  857. target_mem_base+DATA_OFFS+i*256);
  858. if (i == 0)
  859. target_write_u32(target,
  860. 0x31000104,
  861. target_mem_base+DATA_OFFS);
  862. /* DMACCxLLI = next element */
  863. tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
  864. target_write_u32(target, target_mem_base+8+i*32, tmp);
  865. if (i == 0)
  866. target_write_u32(target, 0x31000108, tmp);
  867. /* DMACCxControl = TransferSize =64, Source burst size =16,
  868. * Destination burst size = 16, Source transfer width = 32 bit,
  869. * Destination transfer width = 32 bit, Source AHB master select = M0,
  870. * Destination AHB master select = M0, Source increment = 0,
  871. * Destination increment = 1, Terminal count interrupt enable bit = 0*/
  872. target_write_u32(target,
  873. target_mem_base+12+i*32,
  874. 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
  875. 31);
  876. if (i == 0)
  877. target_write_u32(target,
  878. 0x3100010c,
  879. 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
  880. 31);
  881. /* -------LLI for 3 byte ECC---------
  882. * DMACC0SrcAddr = SLC_ECC*/
  883. target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
  884. /* DMACCxDestAddr = SRAM */
  885. target_write_u32(target,
  886. target_mem_base+20+i*32,
  887. target_mem_base+ECC_OFFS+i*4);
  888. /* DMACCxLLI = next element */
  889. tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
  890. target_write_u32(target, target_mem_base+24+i*32, tmp);
  891. /* DMACCxControl = TransferSize =1, Source burst size =4,
  892. * Destination burst size = 4, Source transfer width = 32 bit,
  893. * Destination transfer width = 32 bit, Source AHB master select = M0,
  894. * Destination AHB master select = M0, Source increment = 0,
  895. * Destination increment = 1, Terminal count interrupt enable bit = 0*/
  896. target_write_u32(target,
  897. target_mem_base+28+i*32,
  898. 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
  899. 31);
  900. }
  901. /* -------LLI for spare area---------
  902. * DMACC0SrcAddr = SLC_DMA_DATA*/
  903. target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
  904. /* DMACCxDestAddr = SRAM */
  905. target_write_u32(target, target_mem_base+4+i*32, target_mem_base+SPARE_OFFS);
  906. /* DMACCxLLI = next element = NULL */
  907. target_write_u32(target, target_mem_base+8+i*32, 0);
  908. /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
  909. * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
  910. * Destination transfer width = 32 bit, Source AHB master select = M0,
  911. * Destination AHB master select = M0, Source increment = 0,
  912. * Destination increment = 1, Terminal count interrupt enable bit = 0*/
  913. target_write_u32(target,
  914. target_mem_base + 12 + i * 32,
  915. (nand->page_size == 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 |
  916. 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<31);
  917. /* Enable DMA after channel set up !
  918. LLI only works when DMA is the flow controller!
  919. */
  920. /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
  921. *FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
  922. target_write_u32(target,
  923. 0x31000110,
  924. 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
  925. /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
  926. target_write_u32(target, 0x20020010, 0x3);
  927. /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
  928. target_write_u32(target, 0x20020028, 2);
  929. /* SLC_TC */
  930. target_write_u32(target, 0x20020030,
  931. (nand->page_size == 2048 ? 0x840 : 0x210));
  932. if (!lpc3180_tc_ready(nand, 1000)) {
  933. LOG_ERROR("timeout while waiting for completion of DMA");
  934. free(page_buffer);
  935. free(ecc_hw_buffer);
  936. free(ecc_flash_buffer);
  937. target_free_working_area(target, pworking_area);
  938. return ERROR_NAND_OPERATION_FAILED;
  939. }
  940. if (data) {
  941. target_read_memory(target,
  942. target_mem_base+DATA_OFFS,
  943. 4,
  944. nand->page_size == 2048 ? 512 : 128,
  945. page_buffer);
  946. memcpy(data, page_buffer, data_size);
  947. LOG_INFO("Page = 0x%" PRIx32 " was read.", page);
  948. /* check hw generated ECC for each 256 bytes block with the saved
  949. *ECC in flash spare area*/
  950. int idx = nand->page_size/0x200;
  951. target_read_memory(target,
  952. target_mem_base+SPARE_OFFS,
  953. 4,
  954. 16,
  955. ecc_flash_buffer);
  956. target_read_memory(target,
  957. target_mem_base+ECC_OFFS,
  958. 4,
  959. 8,
  960. ecc_hw_buffer);
  961. for (i = 0; i < idx; i++) {
  962. if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+i*8)) !=
  963. (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)))
  964. LOG_WARNING(
  965. "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
  966. i * 2 + 1, page);
  967. if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) !=
  968. (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)))
  969. LOG_WARNING(
  970. "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
  971. i * 2 + 2, page);
  972. }
  973. }
  974. if (oob)
  975. memcpy(oob, ecc_flash_buffer, oob_size);
  976. free(page_buffer);
  977. free(ecc_hw_buffer);
  978. free(ecc_flash_buffer);
  979. target_free_working_area(target, pworking_area);
  980. } else
  981. return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
  982. }
  983. return ERROR_OK;
  984. }
  985. static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
  986. {
  987. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  988. struct target *target = nand->target;
  989. if (target->state != TARGET_HALTED) {
  990. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  991. return ERROR_NAND_OPERATION_FAILED;
  992. }
  993. LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
  994. do {
  995. if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  996. uint8_t status;
  997. /* Read MLC_ISR, wait for controller to become ready */
  998. target_read_u8(target, 0x200b8048, &status);
  999. if (status & 2) {
  1000. LOG_DEBUG("lpc3180_controller_ready count=%d",
  1001. timeout);
  1002. return 1;
  1003. }
  1004. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  1005. uint32_t status;
  1006. /* Read SLC_STAT and check READY bit */
  1007. target_read_u32(target, 0x20020018, &status);
  1008. if (status & 1) {
  1009. LOG_DEBUG("lpc3180_controller_ready count=%d",
  1010. timeout);
  1011. return 1;
  1012. }
  1013. }
  1014. alive_sleep(1);
  1015. } while (timeout-- > 0);
  1016. return 0;
  1017. }
  1018. static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
  1019. {
  1020. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  1021. struct target *target = nand->target;
  1022. if (target->state != TARGET_HALTED) {
  1023. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  1024. return ERROR_NAND_OPERATION_FAILED;
  1025. }
  1026. LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
  1027. do {
  1028. if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
  1029. uint8_t status = 0x0;
  1030. /* Read MLC_ISR, wait for NAND flash device to become ready */
  1031. target_read_u8(target, 0x200b8048, &status);
  1032. if (status & 1) {
  1033. LOG_DEBUG("lpc3180_nand_ready count end=%d",
  1034. timeout);
  1035. return 1;
  1036. }
  1037. } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  1038. uint32_t status = 0x0;
  1039. /* Read SLC_STAT and check READY bit */
  1040. target_read_u32(target, 0x20020018, &status);
  1041. if (status & 1) {
  1042. LOG_DEBUG("lpc3180_nand_ready count end=%d",
  1043. timeout);
  1044. return 1;
  1045. }
  1046. }
  1047. alive_sleep(1);
  1048. } while (timeout-- > 0);
  1049. return 0;
  1050. }
  1051. static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
  1052. {
  1053. struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  1054. struct target *target = nand->target;
  1055. if (target->state != TARGET_HALTED) {
  1056. LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
  1057. return ERROR_NAND_OPERATION_FAILED;
  1058. }
  1059. LOG_DEBUG("lpc3180_tc_ready count start=%d",
  1060. timeout);
  1061. do {
  1062. if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
  1063. uint32_t status = 0x0;
  1064. /* Read SLC_INT_STAT and check INT_TC_STAT bit */
  1065. target_read_u32(target, 0x2002001c, &status);
  1066. if (status & 2) {
  1067. LOG_DEBUG("lpc3180_tc_ready count=%d",
  1068. timeout);
  1069. return 1;
  1070. }
  1071. }
  1072. alive_sleep(1);
  1073. } while (timeout-- > 0);
  1074. return 0;
  1075. }
  1076. COMMAND_HANDLER(handle_lpc3180_select_command)
  1077. {
  1078. struct lpc3180_nand_controller *lpc3180_info = NULL;
  1079. char *selected[] = {
  1080. "no", "mlc", "slc"
  1081. };
  1082. if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
  1083. return ERROR_COMMAND_SYNTAX_ERROR;
  1084. unsigned num;
  1085. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  1086. struct nand_device *nand = get_nand_device_by_num(num);
  1087. if (!nand) {
  1088. command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
  1089. return ERROR_OK;
  1090. }
  1091. lpc3180_info = nand->controller_priv;
  1092. if (CMD_ARGC >= 2) {
  1093. if (strcmp(CMD_ARGV[1], "mlc") == 0)
  1094. lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
  1095. else if (strcmp(CMD_ARGV[1], "slc") == 0) {
  1096. lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
  1097. if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0)
  1098. lpc3180_info->is_bulk = 1;
  1099. else
  1100. lpc3180_info->is_bulk = 0;
  1101. } else
  1102. return ERROR_COMMAND_SYNTAX_ERROR;
  1103. }
  1104. if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
  1105. command_print(CMD_CTX, "%s controller selected",
  1106. selected[lpc3180_info->selected_controller]);
  1107. else
  1108. command_print(CMD_CTX,
  1109. lpc3180_info->is_bulk ? "%s controller selected bulk mode is available" :
  1110. "%s controller selected bulk mode is not available",
  1111. selected[lpc3180_info->selected_controller]);
  1112. return ERROR_OK;
  1113. }
  1114. static const struct command_registration lpc3180_exec_command_handlers[] = {
  1115. {
  1116. .name = "select",
  1117. .handler = handle_lpc3180_select_command,
  1118. .mode = COMMAND_EXEC,
  1119. .help =
  1120. "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
  1121. .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
  1122. },
  1123. COMMAND_REGISTRATION_DONE
  1124. };
  1125. static const struct command_registration lpc3180_command_handler[] = {
  1126. {
  1127. .name = "lpc3180",
  1128. .mode = COMMAND_ANY,
  1129. .help = "LPC3180 NAND flash controller commands",
  1130. .usage = "",
  1131. .chain = lpc3180_exec_command_handlers,
  1132. },
  1133. COMMAND_REGISTRATION_DONE
  1134. };
  1135. struct nand_flash_controller lpc3180_nand_controller = {
  1136. .name = "lpc3180",
  1137. .commands = lpc3180_command_handler,
  1138. .nand_device_command = lpc3180_nand_device_command,
  1139. .init = lpc3180_init,
  1140. .reset = lpc3180_reset,
  1141. .command = lpc3180_command,
  1142. .address = lpc3180_address,
  1143. .write_data = lpc3180_write_data,
  1144. .read_data = lpc3180_read_data,
  1145. .write_page = lpc3180_write_page,
  1146. .read_page = lpc3180_read_page,
  1147. .nand_ready = lpc3180_nand_ready,
  1148. };