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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com> *
  6. * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
  7. * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
  8. * *
  9. * Based on a combination of the lpc3180 driver and code from *
  10. * uboot-2009.03-lpc32xx by Kevin Wells. *
  11. * Any bugs are mine. --BSt *
  12. * *
  13. * This program is free software; you can redistribute it and/or modify *
  14. * it under the terms of the GNU General Public License as published by *
  15. * the Free Software Foundation; either version 2 of the License, or *
  16. * (at your option) any later version. *
  17. * *
  18. * This program is distributed in the hope that it will be useful, *
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  21. * GNU General Public License for more details. *
  22. * *
  23. * You should have received a copy of the GNU General Public License *
  24. * along with this program; if not, write to the *
  25. * Free Software Foundation, Inc., *
  26. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  27. ***************************************************************************/
  28. #ifdef HAVE_CONFIG_H
  29. #include "config.h"
  30. #endif
  31. #include "imp.h"
  32. #include "lpc32xx.h"
  33. #include <target/target.h>
  34. static int lpc32xx_reset(struct nand_device *nand);
  35. static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
  36. static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
  37. extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  38. u_char *read_ecc, u_char *calc_ecc);
  39. /* These are offset with the working area in IRAM when using DMA to
  40. * read/write data to the SLC controller.
  41. * - DMA descriptors will be put at start of working area,
  42. * - Hardware generated ECC will be stored at ECC_OFFS
  43. * - OOB wil be read/written from/to SPARE_OFFS
  44. * - Actual page data will be read from/to DATA_OFFS
  45. * There are unused holes between the used areas.
  46. */
  47. #define ECC_OFFS 0x120
  48. #define SPARE_OFFS 0x140
  49. #define DATA_OFFS 0x200
  50. static int sp_ooblayout[] = {
  51. 10, 11, 12, 13, 14, 15
  52. };
  53. static int lp_ooblayout[] = {
  54. 40, 41, 42, 43, 44, 45,
  55. 46, 47, 48, 49, 50, 51,
  56. 52, 53, 54, 55, 56, 57,
  57. 58, 59, 60, 61, 62, 63
  58. };
  59. typedef struct {
  60. volatile uint32_t dma_src;
  61. volatile uint32_t dma_dest;
  62. volatile uint32_t next_lli;
  63. volatile uint32_t next_ctrl;
  64. } dmac_ll_t;
  65. static dmac_ll_t dmalist[(2048/256) * 2 + 1];
  66. /* nand device lpc32xx <target#> <oscillator_frequency>
  67. */
  68. NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
  69. {
  70. if (CMD_ARGC < 3)
  71. return ERROR_COMMAND_SYNTAX_ERROR;
  72. uint32_t osc_freq;
  73. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  74. struct lpc32xx_nand_controller *lpc32xx_info;
  75. lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
  76. nand->controller_priv = lpc32xx_info;
  77. lpc32xx_info->osc_freq = osc_freq;
  78. if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
  79. LOG_WARNING("LPC32xx oscillator frequency should be between "
  80. "1000 and 20000 kHz, was %i",
  81. lpc32xx_info->osc_freq);
  82. lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
  83. lpc32xx_info->sw_write_protection = 0;
  84. lpc32xx_info->sw_wp_lower_bound = 0x0;
  85. lpc32xx_info->sw_wp_upper_bound = 0x0;
  86. return ERROR_OK;
  87. }
  88. static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
  89. {
  90. int bypass = (pll_ctrl & 0x8000) >> 15;
  91. int direct = (pll_ctrl & 0x4000) >> 14;
  92. int feedback = (pll_ctrl & 0x2000) >> 13;
  93. int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  94. int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  95. int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  96. int lock = (pll_ctrl & 0x1);
  97. if (!lock)
  98. LOG_WARNING("PLL is not locked");
  99. if (!bypass && direct) /* direct mode */
  100. return (m * fclkin) / n;
  101. if (bypass && !direct) /* bypass mode */
  102. return fclkin / (2 * p);
  103. if (bypass & direct) /* direct bypass mode */
  104. return fclkin;
  105. if (feedback) /* integer mode */
  106. return m * (fclkin / n);
  107. else /* non-integer mode */
  108. return (m / (2 * p)) * (fclkin / n);
  109. }
  110. static float lpc32xx_cycle_time(struct nand_device *nand)
  111. {
  112. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  113. struct target *target = nand->target;
  114. uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
  115. int sysclk;
  116. int hclk;
  117. int hclk_pll;
  118. float cycle;
  119. int retval;
  120. /* calculate timings */
  121. /* determine current SYSCLK (13'MHz or main oscillator) */
  122. retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
  123. if (ERROR_OK != retval) {
  124. LOG_ERROR("could not read SYSCLK_CTRL");
  125. return ERROR_NAND_OPERATION_FAILED;
  126. }
  127. if ((sysclk_ctrl & 1) == 0)
  128. sysclk = lpc32xx_info->osc_freq;
  129. else
  130. sysclk = 13000;
  131. /* determine selected HCLK source */
  132. retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
  133. if (ERROR_OK != retval) {
  134. LOG_ERROR("could not read HCLK_CTRL");
  135. return ERROR_NAND_OPERATION_FAILED;
  136. }
  137. if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
  138. hclk = sysclk;
  139. else {
  140. retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
  141. if (ERROR_OK != retval) {
  142. LOG_ERROR("could not read HCLKPLL_CTRL");
  143. return ERROR_NAND_OPERATION_FAILED;
  144. }
  145. hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
  146. retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
  147. if (ERROR_OK != retval) {
  148. LOG_ERROR("could not read CLKDIV_CTRL");
  149. return ERROR_NAND_OPERATION_FAILED;
  150. }
  151. if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
  152. hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
  153. else /* HCLK uses HCLK_PLL */
  154. hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
  155. }
  156. LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
  157. cycle = (1.0 / hclk) * 1000000.0;
  158. return cycle;
  159. }
  160. static int lpc32xx_init(struct nand_device *nand)
  161. {
  162. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  163. struct target *target = nand->target;
  164. int bus_width = nand->bus_width ? : 8;
  165. int address_cycles = nand->address_cycles ? : 3;
  166. int page_size = nand->page_size ? : 512;
  167. int retval;
  168. if (target->state != TARGET_HALTED) {
  169. LOG_ERROR("target must be halted to use LPC32xx "
  170. "NAND flash controller");
  171. return ERROR_NAND_OPERATION_FAILED;
  172. }
  173. /* sanitize arguments */
  174. if (bus_width != 8) {
  175. LOG_ERROR("LPC32xx doesn't support %i", bus_width);
  176. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  177. }
  178. /* inform calling code about selected bus width */
  179. nand->bus_width = bus_width;
  180. if ((address_cycles < 3) || (address_cycles > 5)) {
  181. LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
  182. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  183. }
  184. if ((page_size != 512) && (page_size != 2048)) {
  185. LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
  186. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  187. }
  188. /* select MLC controller if none is currently selected */
  189. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  190. LOG_DEBUG("no LPC32xx NAND flash controller selected, "
  191. "using default 'slc'");
  192. lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
  193. }
  194. if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  195. uint32_t mlc_icr_value = 0x0;
  196. float cycle;
  197. int twp, twh, trp, treh, trhz, trbwb, tcea;
  198. /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
  199. retval = target_write_u32(target, 0x400040c8, 0x22);
  200. if (ERROR_OK != retval) {
  201. LOG_ERROR("could not set FLASHCLK_CTRL");
  202. return ERROR_NAND_OPERATION_FAILED;
  203. }
  204. /* MLC_CEH = 0x0 (Force nCE assert) */
  205. retval = target_write_u32(target, 0x200b804c, 0x0);
  206. if (ERROR_OK != retval) {
  207. LOG_ERROR("could not set MLC_CEH");
  208. return ERROR_NAND_OPERATION_FAILED;
  209. }
  210. /* MLC_LOCK = 0xa25e (unlock protected registers) */
  211. retval = target_write_u32(target, 0x200b8044, 0xa25e);
  212. if (ERROR_OK != retval) {
  213. LOG_ERROR("could not set MLC_LOCK");
  214. return ERROR_NAND_OPERATION_FAILED;
  215. }
  216. /* MLC_ICR = configuration */
  217. if (lpc32xx_info->sw_write_protection)
  218. mlc_icr_value |= 0x8;
  219. if (page_size == 2048)
  220. mlc_icr_value |= 0x4;
  221. if (address_cycles == 4)
  222. mlc_icr_value |= 0x2;
  223. if (bus_width == 16)
  224. mlc_icr_value |= 0x1;
  225. retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
  226. if (ERROR_OK != retval) {
  227. LOG_ERROR("could not set MLC_ICR");
  228. return ERROR_NAND_OPERATION_FAILED;
  229. }
  230. /* calculate NAND controller timings */
  231. cycle = lpc32xx_cycle_time(nand);
  232. twp = ((40 / cycle) + 1);
  233. twh = ((20 / cycle) + 1);
  234. trp = ((30 / cycle) + 1);
  235. treh = ((15 / cycle) + 1);
  236. trhz = ((30 / cycle) + 1);
  237. trbwb = ((100 / cycle) + 1);
  238. tcea = ((45 / cycle) + 1);
  239. /* MLC_LOCK = 0xa25e (unlock protected registers) */
  240. retval = target_write_u32(target, 0x200b8044, 0xa25e);
  241. if (ERROR_OK != retval) {
  242. LOG_ERROR("could not set MLC_LOCK");
  243. return ERROR_NAND_OPERATION_FAILED;
  244. }
  245. /* MLC_TIME_REG */
  246. retval = target_write_u32(target, 0x200b8034,
  247. (twp & 0xf)
  248. | ((twh & 0xf) << 4)
  249. | ((trp & 0xf) << 8)
  250. | ((treh & 0xf) << 12)
  251. | ((trhz & 0x7) << 16)
  252. | ((trbwb & 0x1f) << 19)
  253. | ((tcea & 0x3) << 24));
  254. if (ERROR_OK != retval) {
  255. LOG_ERROR("could not set MLC_TIME_REG");
  256. return ERROR_NAND_OPERATION_FAILED;
  257. }
  258. retval = lpc32xx_reset(nand);
  259. if (ERROR_OK != retval)
  260. return ERROR_NAND_OPERATION_FAILED;
  261. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  262. float cycle;
  263. int r_setup, r_hold, r_width, r_rdy;
  264. int w_setup, w_hold, w_width, w_rdy;
  265. /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
  266. retval = target_write_u32(target, 0x400040c8, 0x05);
  267. if (ERROR_OK != retval) {
  268. LOG_ERROR("could not set FLASHCLK_CTRL");
  269. return ERROR_NAND_OPERATION_FAILED;
  270. }
  271. /* after reset set other registers of SLC,
  272. * so reset calling is here at the begining
  273. */
  274. retval = lpc32xx_reset(nand);
  275. if (ERROR_OK != retval)
  276. return ERROR_NAND_OPERATION_FAILED;
  277. /* SLC_CFG =
  278. Force nCE assert,
  279. DMA ECC enabled,
  280. ECC enabled,
  281. DMA burst enabled,
  282. DMA read from SLC,
  283. WIDTH = bus_width)
  284. */
  285. retval = target_write_u32(target, 0x20020014,
  286. 0x3e | (bus_width == 16) ? 1 : 0);
  287. if (ERROR_OK != retval) {
  288. LOG_ERROR("could not set SLC_CFG");
  289. return ERROR_NAND_OPERATION_FAILED;
  290. }
  291. /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
  292. retval = target_write_u32(target, 0x20020020, 0x03);
  293. if (ERROR_OK != retval) {
  294. LOG_ERROR("could not set SLC_IEN");
  295. return ERROR_NAND_OPERATION_FAILED;
  296. }
  297. /* DMA configuration */
  298. /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
  299. retval = target_write_u32(target, 0x400040e8, 0x01);
  300. if (ERROR_OK != retval) {
  301. LOG_ERROR("could not set DMACLK_CTRL");
  302. return ERROR_NAND_OPERATION_FAILED;
  303. }
  304. /* DMACConfig = DMA enabled*/
  305. retval = target_write_u32(target, 0x31000030, 0x01);
  306. if (ERROR_OK != retval) {
  307. LOG_ERROR("could not set DMACConfig");
  308. return ERROR_NAND_OPERATION_FAILED;
  309. }
  310. /* calculate NAND controller timings */
  311. cycle = lpc32xx_cycle_time(nand);
  312. r_setup = w_setup = 0;
  313. r_hold = w_hold = 10 / cycle;
  314. r_width = 30 / cycle;
  315. w_width = 40 / cycle;
  316. r_rdy = w_rdy = 100 / cycle;
  317. /* SLC_TAC: SLC timing arcs register */
  318. retval = target_write_u32(target, 0x2002002c,
  319. (r_setup & 0xf)
  320. | ((r_hold & 0xf) << 4)
  321. | ((r_width & 0xf) << 8)
  322. | ((r_rdy & 0xf) << 12)
  323. | ((w_setup & 0xf) << 16)
  324. | ((w_hold & 0xf) << 20)
  325. | ((w_width & 0xf) << 24)
  326. | ((w_rdy & 0xf) << 28));
  327. if (ERROR_OK != retval) {
  328. LOG_ERROR("could not set SLC_TAC");
  329. return ERROR_NAND_OPERATION_FAILED;
  330. }
  331. }
  332. return ERROR_OK;
  333. }
  334. static int lpc32xx_reset(struct nand_device *nand)
  335. {
  336. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  337. struct target *target = nand->target;
  338. int retval;
  339. if (target->state != TARGET_HALTED) {
  340. LOG_ERROR("target must be halted to use "
  341. "LPC32xx NAND flash controller");
  342. return ERROR_NAND_OPERATION_FAILED;
  343. }
  344. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  345. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  346. return ERROR_NAND_OPERATION_FAILED;
  347. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  348. /* MLC_CMD = 0xff (reset controller and NAND device) */
  349. retval = target_write_u32(target, 0x200b8000, 0xff);
  350. if (ERROR_OK != retval) {
  351. LOG_ERROR("could not set MLC_CMD");
  352. return ERROR_NAND_OPERATION_FAILED;
  353. }
  354. if (!lpc32xx_controller_ready(nand, 100)) {
  355. LOG_ERROR("LPC32xx MLC NAND controller timed out "
  356. "after reset");
  357. return ERROR_NAND_OPERATION_TIMEOUT;
  358. }
  359. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  360. /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
  361. retval = target_write_u32(target, 0x20020010, 0x6);
  362. if (ERROR_OK != retval) {
  363. LOG_ERROR("could not set SLC_CTRL");
  364. return ERROR_NAND_OPERATION_FAILED;
  365. }
  366. if (!lpc32xx_controller_ready(nand, 100)) {
  367. LOG_ERROR("LPC32xx SLC NAND controller timed out "
  368. "after reset");
  369. return ERROR_NAND_OPERATION_TIMEOUT;
  370. }
  371. }
  372. return ERROR_OK;
  373. }
  374. static int lpc32xx_command(struct nand_device *nand, uint8_t command)
  375. {
  376. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  377. struct target *target = nand->target;
  378. int retval;
  379. if (target->state != TARGET_HALTED) {
  380. LOG_ERROR("target must be halted to use "
  381. "LPC32xx NAND flash controller");
  382. return ERROR_NAND_OPERATION_FAILED;
  383. }
  384. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  385. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  386. return ERROR_NAND_OPERATION_FAILED;
  387. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  388. /* MLC_CMD = command */
  389. retval = target_write_u32(target, 0x200b8000, command);
  390. if (ERROR_OK != retval) {
  391. LOG_ERROR("could not set MLC_CMD");
  392. return ERROR_NAND_OPERATION_FAILED;
  393. }
  394. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  395. /* SLC_CMD = command */
  396. retval = target_write_u32(target, 0x20020008, command);
  397. if (ERROR_OK != retval) {
  398. LOG_ERROR("could not set SLC_CMD");
  399. return ERROR_NAND_OPERATION_FAILED;
  400. }
  401. }
  402. return ERROR_OK;
  403. }
  404. static int lpc32xx_address(struct nand_device *nand, uint8_t address)
  405. {
  406. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  407. struct target *target = nand->target;
  408. int retval;
  409. if (target->state != TARGET_HALTED) {
  410. LOG_ERROR("target must be halted to use "
  411. "LPC32xx NAND flash controller");
  412. return ERROR_NAND_OPERATION_FAILED;
  413. }
  414. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  415. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  416. return ERROR_NAND_OPERATION_FAILED;
  417. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  418. /* MLC_ADDR = address */
  419. retval = target_write_u32(target, 0x200b8004, address);
  420. if (ERROR_OK != retval) {
  421. LOG_ERROR("could not set MLC_ADDR");
  422. return ERROR_NAND_OPERATION_FAILED;
  423. }
  424. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  425. /* SLC_ADDR = address */
  426. retval = target_write_u32(target, 0x20020004, address);
  427. if (ERROR_OK != retval) {
  428. LOG_ERROR("could not set SLC_ADDR");
  429. return ERROR_NAND_OPERATION_FAILED;
  430. }
  431. }
  432. return ERROR_OK;
  433. }
  434. static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
  435. {
  436. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  437. struct target *target = nand->target;
  438. int retval;
  439. if (target->state != TARGET_HALTED) {
  440. LOG_ERROR("target must be halted to use "
  441. "LPC32xx NAND flash controller");
  442. return ERROR_NAND_OPERATION_FAILED;
  443. }
  444. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  445. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  446. return ERROR_NAND_OPERATION_FAILED;
  447. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  448. /* MLC_DATA = data */
  449. retval = target_write_u32(target, 0x200b0000, data);
  450. if (ERROR_OK != retval) {
  451. LOG_ERROR("could not set MLC_DATA");
  452. return ERROR_NAND_OPERATION_FAILED;
  453. }
  454. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  455. /* SLC_DATA = data */
  456. retval = target_write_u32(target, 0x20020000, data);
  457. if (ERROR_OK != retval) {
  458. LOG_ERROR("could not set SLC_DATA");
  459. return ERROR_NAND_OPERATION_FAILED;
  460. }
  461. }
  462. return ERROR_OK;
  463. }
  464. static int lpc32xx_read_data(struct nand_device *nand, void *data)
  465. {
  466. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  467. struct target *target = nand->target;
  468. int retval;
  469. if (target->state != TARGET_HALTED) {
  470. LOG_ERROR("target must be halted to use LPC32xx "
  471. "NAND flash controller");
  472. return ERROR_NAND_OPERATION_FAILED;
  473. }
  474. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  475. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  476. return ERROR_NAND_OPERATION_FAILED;
  477. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  478. /* data = MLC_DATA, use sized access */
  479. if (nand->bus_width == 8) {
  480. uint8_t *data8 = data;
  481. retval = target_read_u8(target, 0x200b0000, data8);
  482. } else {
  483. LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
  484. return ERROR_NAND_OPERATION_FAILED;
  485. }
  486. if (ERROR_OK != retval) {
  487. LOG_ERROR("could not read MLC_DATA");
  488. return ERROR_NAND_OPERATION_FAILED;
  489. }
  490. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  491. uint32_t data32;
  492. /* data = SLC_DATA, must use 32-bit access */
  493. retval = target_read_u32(target, 0x20020000, &data32);
  494. if (ERROR_OK != retval) {
  495. LOG_ERROR("could not read SLC_DATA");
  496. return ERROR_NAND_OPERATION_FAILED;
  497. }
  498. if (nand->bus_width == 8) {
  499. uint8_t *data8 = data;
  500. *data8 = data32 & 0xff;
  501. } else {
  502. LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
  503. return ERROR_NAND_OPERATION_FAILED;
  504. }
  505. }
  506. return ERROR_OK;
  507. }
  508. static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
  509. uint8_t *data, uint32_t data_size,
  510. uint8_t *oob, uint32_t oob_size)
  511. {
  512. struct target *target = nand->target;
  513. int retval;
  514. uint8_t status;
  515. static uint8_t page_buffer[512];
  516. static uint8_t oob_buffer[6];
  517. int quarter, num_quarters;
  518. /* MLC_CMD = sequential input */
  519. retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
  520. if (ERROR_OK != retval) {
  521. LOG_ERROR("could not set MLC_CMD");
  522. return ERROR_NAND_OPERATION_FAILED;
  523. }
  524. if (nand->page_size == 512) {
  525. /* MLC_ADDR = 0x0 (one column cycle) */
  526. retval = target_write_u32(target, 0x200b8004, 0x0);
  527. if (ERROR_OK != retval) {
  528. LOG_ERROR("could not set MLC_ADDR");
  529. return ERROR_NAND_OPERATION_FAILED;
  530. }
  531. /* MLC_ADDR = row */
  532. retval = target_write_u32(target, 0x200b8004, page & 0xff);
  533. if (ERROR_OK != retval) {
  534. LOG_ERROR("could not set MLC_ADDR");
  535. return ERROR_NAND_OPERATION_FAILED;
  536. }
  537. retval = target_write_u32(target, 0x200b8004,
  538. (page >> 8) & 0xff);
  539. if (ERROR_OK != retval) {
  540. LOG_ERROR("could not set MLC_ADDR");
  541. return ERROR_NAND_OPERATION_FAILED;
  542. }
  543. if (nand->address_cycles == 4) {
  544. retval = target_write_u32(target, 0x200b8004,
  545. (page >> 16) & 0xff);
  546. if (ERROR_OK != retval) {
  547. LOG_ERROR("could not set MLC_ADDR");
  548. return ERROR_NAND_OPERATION_FAILED;
  549. }
  550. }
  551. } else {
  552. /* MLC_ADDR = 0x0 (two column cycles) */
  553. retval = target_write_u32(target, 0x200b8004, 0x0);
  554. if (ERROR_OK != retval) {
  555. LOG_ERROR("could not set MLC_ADDR");
  556. return ERROR_NAND_OPERATION_FAILED;
  557. }
  558. retval = target_write_u32(target, 0x200b8004, 0x0);
  559. if (ERROR_OK != retval) {
  560. LOG_ERROR("could not set MLC_ADDR");
  561. return ERROR_NAND_OPERATION_FAILED;
  562. }
  563. /* MLC_ADDR = row */
  564. retval = target_write_u32(target, 0x200b8004, page & 0xff);
  565. if (ERROR_OK != retval) {
  566. LOG_ERROR("could not set MLC_ADDR");
  567. return ERROR_NAND_OPERATION_FAILED;
  568. }
  569. retval = target_write_u32(target, 0x200b8004,
  570. (page >> 8) & 0xff);
  571. if (ERROR_OK != retval) {
  572. LOG_ERROR("could not set MLC_ADDR");
  573. return ERROR_NAND_OPERATION_FAILED;
  574. }
  575. }
  576. /* when using the MLC controller, we have to treat a large page device
  577. * as being made out of four quarters, each the size of a small page
  578. * device
  579. */
  580. num_quarters = (nand->page_size == 2048) ? 4 : 1;
  581. for (quarter = 0; quarter < num_quarters; quarter++) {
  582. int thisrun_data_size = (data_size > 512) ? 512 : data_size;
  583. int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
  584. memset(page_buffer, 0xff, 512);
  585. if (data) {
  586. memcpy(page_buffer, data, thisrun_data_size);
  587. data_size -= thisrun_data_size;
  588. data += thisrun_data_size;
  589. }
  590. memset(oob_buffer, 0xff, 6);
  591. if (oob) {
  592. memcpy(oob_buffer, oob, thisrun_oob_size);
  593. oob_size -= thisrun_oob_size;
  594. oob += thisrun_oob_size;
  595. }
  596. /* write MLC_ECC_ENC_REG to start encode cycle */
  597. retval = target_write_u32(target, 0x200b8008, 0x0);
  598. if (ERROR_OK != retval) {
  599. LOG_ERROR("could not set MLC_ECC_ENC_REG");
  600. return ERROR_NAND_OPERATION_FAILED;
  601. }
  602. retval = target_write_memory(target, 0x200a8000,
  603. 4, 128, page_buffer);
  604. if (ERROR_OK != retval) {
  605. LOG_ERROR("could not set MLC_BUF (data)");
  606. return ERROR_NAND_OPERATION_FAILED;
  607. }
  608. retval = target_write_memory(target, 0x200a8000,
  609. 1, 6, oob_buffer);
  610. if (ERROR_OK != retval) {
  611. LOG_ERROR("could not set MLC_BUF (oob)");
  612. return ERROR_NAND_OPERATION_FAILED;
  613. }
  614. /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
  615. retval = target_write_u32(target, 0x200b8010, 0x0);
  616. if (ERROR_OK != retval) {
  617. LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
  618. return ERROR_NAND_OPERATION_FAILED;
  619. }
  620. if (!lpc32xx_controller_ready(nand, 1000)) {
  621. LOG_ERROR("timeout while waiting for "
  622. "completion of auto encode cycle");
  623. return ERROR_NAND_OPERATION_FAILED;
  624. }
  625. }
  626. /* MLC_CMD = auto program command */
  627. retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
  628. if (ERROR_OK != retval) {
  629. LOG_ERROR("could not set MLC_CMD");
  630. return ERROR_NAND_OPERATION_FAILED;
  631. }
  632. retval = nand_read_status(nand, &status);
  633. if (retval != ERROR_OK) {
  634. LOG_ERROR("couldn't read status");
  635. return ERROR_NAND_OPERATION_FAILED;
  636. }
  637. if (status & NAND_STATUS_FAIL) {
  638. LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
  639. status);
  640. return ERROR_NAND_OPERATION_FAILED;
  641. }
  642. return ERROR_OK;
  643. }
  644. /* SLC controller in !raw mode will use target cpu to read/write nand from/to
  645. * target internal memory. The transfer to/from flash is done by DMA. This
  646. * function sets up the dma linked list in host memory for later transfer to
  647. * target.
  648. */
  649. static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
  650. int do_read)
  651. {
  652. uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
  653. /* DMACCxControl =
  654. TransferSize =64,
  655. Source burst size =16,
  656. Destination burst size = 16,
  657. Source transfer width = 32 bit,
  658. Destination transfer width = 32 bit,
  659. Source AHB master select = M0,
  660. Destination AHB master select = M0,
  661. Source increment = 0, // set later
  662. Destination increment = 0, // set later
  663. Terminal count interrupt enable bit = 0 // set on last
  664. */ /*
  665. * Write Operation Sequence for Small Block NAND
  666. * ----------------------------------------------------------
  667. * 1. X'fer 256 bytes of data from Memory to Flash.
  668. * 2. Copy generated ECC data from Register to Spare Area
  669. * 3. X'fer next 256 bytes of data from Memory to Flash.
  670. * 4. Copy generated ECC data from Register to Spare Area.
  671. * 5. X'fer 16 byets of Spare area from Memory to Flash.
  672. * Read Operation Sequence for Small Block NAND
  673. * ----------------------------------------------------------
  674. * 1. X'fer 256 bytes of data from Flash to Memory.
  675. * 2. Copy generated ECC data from Register to ECC calc Buffer.
  676. * 3. X'fer next 256 bytes of data from Flash to Memory.
  677. * 4. Copy generated ECC data from Register to ECC calc Buffer.
  678. * 5. X'fer 16 bytes of Spare area from Flash to Memory.
  679. * Write Operation Sequence for Large Block NAND
  680. * ----------------------------------------------------------
  681. * 1. Steps(1-4) of Write Operations repeate for four times
  682. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  683. * data & 32 bytes of ECC data.
  684. * 2. X'fer 64 bytes of Spare area from Memory to Flash.
  685. * Read Operation Sequence for Large Block NAND
  686. * ----------------------------------------------------------
  687. * 1. Steps(1-4) of Read Operations repeate for four times
  688. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  689. * data & 32 bytes of ECC data.
  690. * 2. X'fer 64 bytes of Spare area from Flash to Memory.
  691. */
  692. ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
  693. | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
  694. /* DMACCxControl =
  695. TransferSize =1,
  696. Source burst size =4,
  697. Destination burst size = 4,
  698. Source transfer width = 32 bit,
  699. Destination transfer width = 32 bit,
  700. Source AHB master select = M0,
  701. Destination AHB master select = M0,
  702. Source increment = 0,
  703. Destination increment = 1,
  704. Terminal count interrupt enable bit = 0
  705. */
  706. ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
  707. | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
  708. /* DMACCxControl =
  709. TransferSize =16 for lp or 4 for sp,
  710. Source burst size =16,
  711. Destination burst size = 16,
  712. Source transfer width = 32 bit,
  713. Destination transfer width = 32 bit,
  714. Source AHB master select = M0,
  715. Destination AHB master select = M0,
  716. Source increment = 0, // set later
  717. Destination increment = 0, // set later
  718. Terminal count interrupt enable bit = 1 // set on last
  719. */
  720. oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
  721. | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
  722. | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
  723. if (do_read) {
  724. ctrl |= 1 << 27;/* Destination increment = 1 */
  725. oob_ctrl |= 1 << 27; /* Destination increment = 1 */
  726. dmasrc = 0x20020038; /* SLC_DMA_DATA */
  727. dmadst = target_mem_base + DATA_OFFS;
  728. } else {
  729. ctrl |= 1 << 26;/* Source increment = 1 */
  730. oob_ctrl |= 1 << 26; /* Source increment = 1 */
  731. dmasrc = target_mem_base + DATA_OFFS;
  732. dmadst = 0x20020038; /* SLC_DMA_DATA */
  733. }
  734. /*
  735. * Write Operation Sequence for Small Block NAND
  736. * ----------------------------------------------------------
  737. * 1. X'fer 256 bytes of data from Memory to Flash.
  738. * 2. Copy generated ECC data from Register to Spare Area
  739. * 3. X'fer next 256 bytes of data from Memory to Flash.
  740. * 4. Copy generated ECC data from Register to Spare Area.
  741. * 5. X'fer 16 byets of Spare area from Memory to Flash.
  742. * Read Operation Sequence for Small Block NAND
  743. * ----------------------------------------------------------
  744. * 1. X'fer 256 bytes of data from Flash to Memory.
  745. * 2. Copy generated ECC data from Register to ECC calc Buffer.
  746. * 3. X'fer next 256 bytes of data from Flash to Memory.
  747. * 4. Copy generated ECC data from Register to ECC calc Buffer.
  748. * 5. X'fer 16 bytes of Spare area from Flash to Memory.
  749. * Write Operation Sequence for Large Block NAND
  750. * ----------------------------------------------------------
  751. * 1. Steps(1-4) of Write Operations repeate for four times
  752. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  753. * data & 32 bytes of ECC data.
  754. * 2. X'fer 64 bytes of Spare area from Memory to Flash.
  755. * Read Operation Sequence for Large Block NAND
  756. * ----------------------------------------------------------
  757. * 1. Steps(1-4) of Read Operations repeate for four times
  758. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  759. * data & 32 bytes of ECC data.
  760. * 2. X'fer 64 bytes of Spare area from Flash to Memory.
  761. */
  762. for (i = 0; i < page_size/0x100; i++) {
  763. dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
  764. dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
  765. dmalist[i*2].next_lli =
  766. target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
  767. dmalist[i*2].next_ctrl = ctrl;
  768. dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
  769. dmalist[(i*2) + 1].dma_dest =
  770. target_mem_base + ECC_OFFS + i * 4;
  771. dmalist[(i*2) + 1].next_lli =
  772. target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
  773. dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
  774. }
  775. if (do_read)
  776. dmadst = target_mem_base + SPARE_OFFS;
  777. else {
  778. dmasrc = target_mem_base + SPARE_OFFS;
  779. dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
  780. dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
  781. }
  782. dmalist[i*2].dma_src = dmasrc;
  783. dmalist[i*2].dma_dest = dmadst;
  784. dmalist[i*2].next_lli = 0;
  785. dmalist[i*2].next_ctrl = oob_ctrl;
  786. return i * 2 + 1; /* Number of descriptors */
  787. }
  788. static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
  789. int do_wait)
  790. {
  791. struct target *target = nand->target;
  792. int retval;
  793. /* DMACIntTCClear = ch0 */
  794. retval = target_write_u32(target, 0x31000008, 1);
  795. if (ERROR_OK != retval) {
  796. LOG_ERROR("Could not set DMACIntTCClear");
  797. return retval;
  798. }
  799. /* DMACIntErrClear = ch0 */
  800. retval = target_write_u32(target, 0x31000010, 1);
  801. if (ERROR_OK != retval) {
  802. LOG_ERROR("Could not set DMACIntErrClear");
  803. return retval;
  804. }
  805. /* DMACCxConfig=
  806. E=1,
  807. SrcPeripheral = 1 (SLC),
  808. DestPeripheral = 1 (SLC),
  809. FlowCntrl = 2 (Pher -> Mem, DMA),
  810. IE = 0,
  811. ITC = 0,
  812. L= 0,
  813. H=0
  814. */
  815. retval = target_write_u32(target, 0x31000110,
  816. 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
  817. | 0<<15 | 0<<16 | 0<<18);
  818. if (ERROR_OK != retval) {
  819. LOG_ERROR("Could not set DMACC0Config");
  820. return retval;
  821. }
  822. /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
  823. retval = target_write_u32(target, 0x20020010, 0x3);
  824. if (ERROR_OK != retval) {
  825. LOG_ERROR("Could not set SLC_CTRL");
  826. return retval;
  827. }
  828. /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
  829. retval = target_write_u32(target, 0x20020028, 2);
  830. if (ERROR_OK != retval) {
  831. LOG_ERROR("Could not set SLC_ICR");
  832. return retval;
  833. }
  834. /* SLC_TC */
  835. retval = target_write_u32(target, 0x20020030, count);
  836. if (ERROR_OK != retval) {
  837. LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
  838. return retval;
  839. }
  840. /* Wait finish */
  841. if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
  842. LOG_ERROR("timeout while waiting for completion of DMA");
  843. return ERROR_NAND_OPERATION_FAILED;
  844. }
  845. return retval;
  846. }
  847. static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
  848. {
  849. struct target *target = nand->target;
  850. LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
  851. do {
  852. uint32_t tc_stat;
  853. uint32_t err_stat;
  854. int retval;
  855. /* Read DMACRawIntTCStat */
  856. retval = target_read_u32(target, 0x31000014, &tc_stat);
  857. if (ERROR_OK != retval) {
  858. LOG_ERROR("Could not read DMACRawIntTCStat");
  859. return 0;
  860. }
  861. /* Read DMACRawIntErrStat */
  862. retval = target_read_u32(target, 0x31000018, &err_stat);
  863. if (ERROR_OK != retval) {
  864. LOG_ERROR("Could not read DMACRawIntErrStat");
  865. return 0;
  866. }
  867. if ((tc_stat | err_stat) & 1) {
  868. LOG_DEBUG("lpc32xx_dma_ready count=%d",
  869. timeout);
  870. if (err_stat & 1) {
  871. LOG_ERROR("lpc32xx_dma_ready "
  872. "DMA error, aborted");
  873. return 0;
  874. } else
  875. return 1;
  876. }
  877. alive_sleep(1);
  878. } while (timeout-- > 0);
  879. return 0;
  880. }
  881. static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
  882. const uint32_t *ecc, int count)
  883. {
  884. int i;
  885. for (i = 0; i < (count * 3); i += 3) {
  886. uint32_t ce = ecc[i/3];
  887. ce = ~(ce << 2) & 0xFFFFFF;
  888. spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
  889. spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
  890. spare[i] = (uint8_t)(ce & 0xFF);
  891. }
  892. return 0;
  893. }
  894. static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
  895. {
  896. int addr = 0;
  897. while (oob_size > 0) {
  898. LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
  899. oob[0], oob[1], oob[2], oob[3],
  900. oob[4], oob[5], oob[6], oob[7]);
  901. oob += 8;
  902. addr += 8;
  903. oob_size -= 8;
  904. }
  905. }
  906. static int lpc32xx_write_page_slc(struct nand_device *nand,
  907. struct working_area *pworking_area,
  908. uint32_t page, uint8_t *data,
  909. uint32_t data_size, uint8_t *oob,
  910. uint32_t oob_size)
  911. {
  912. struct target *target = nand->target;
  913. int retval;
  914. uint32_t target_mem_base;
  915. LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
  916. "data_size=%d, oob_size=%d",
  917. page, data != 0, oob != 0, data_size, oob_size);
  918. target_mem_base = pworking_area->address;
  919. /*
  920. * Skip writting page which has all 0xFF data as this will
  921. * generate 0x0 value.
  922. */
  923. if (data && !oob) {
  924. uint32_t i, all_ff = 1;
  925. for (i = 0; i < data_size; i++)
  926. if (data[i] != 0xFF) {
  927. all_ff = 0;
  928. break;
  929. }
  930. if (all_ff)
  931. return ERROR_OK;
  932. }
  933. /* Make the dma descriptors in local memory */
  934. int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
  935. /* Write them to target.
  936. XXX: Assumes host and target have same byte sex.
  937. */
  938. retval = target_write_memory(target, target_mem_base, 4,
  939. nll * sizeof(dmac_ll_t) / 4,
  940. (uint8_t *)dmalist);
  941. if (ERROR_OK != retval) {
  942. LOG_ERROR("Could not write DMA descriptors to IRAM");
  943. return retval;
  944. }
  945. retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
  946. if (ERROR_OK != retval) {
  947. LOG_ERROR("NAND_CMD_SEQIN failed");
  948. return retval;
  949. }
  950. /* SLC_CFG =
  951. Force nCE assert,
  952. DMA ECC enabled,
  953. ECC enabled,
  954. DMA burst enabled,
  955. DMA write to SLC,
  956. WIDTH = bus_width
  957. */
  958. retval = target_write_u32(target, 0x20020014, 0x3c);
  959. if (ERROR_OK != retval) {
  960. LOG_ERROR("Could not set SLC_CFG");
  961. return retval;
  962. }
  963. if (data) {
  964. /* Write data to target */
  965. static uint8_t fdata[2048];
  966. memset(fdata, 0xFF, nand->page_size);
  967. memcpy(fdata, data, data_size);
  968. retval = target_write_memory(target,
  969. target_mem_base + DATA_OFFS,
  970. 4, nand->page_size/4, fdata);
  971. if (ERROR_OK != retval) {
  972. LOG_ERROR("Could not write data to IRAM");
  973. return retval;
  974. }
  975. /* Write first decriptor to DMA controller */
  976. retval = target_write_memory(target, 0x31000100, 4,
  977. sizeof(dmac_ll_t) / 4,
  978. (uint8_t *)dmalist);
  979. if (ERROR_OK != retval) {
  980. LOG_ERROR("Could not write DMA descriptor to DMAC");
  981. return retval;
  982. }
  983. /* Start xfer of data from iram to flash using DMA */
  984. int tot_size = nand->page_size;
  985. tot_size += tot_size == 2048 ? 64 : 16;
  986. retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
  987. if (ERROR_OK != retval) {
  988. LOG_ERROR("DMA failed");
  989. return retval;
  990. }
  991. /* Wait for DMA to finish. SLC is not finished at this stage */
  992. if (!lpc32xx_dma_ready(nand, 100)) {
  993. LOG_ERROR("Data DMA failed during write");
  994. return ERROR_FLASH_OPERATION_FAILED;
  995. }
  996. } /* data xfer */
  997. /* Copy OOB to iram */
  998. static uint8_t foob[64];
  999. int foob_size = nand->page_size == 2048 ? 64 : 16;
  1000. memset(foob, 0xFF, foob_size);
  1001. if (oob) /* Raw mode */
  1002. memcpy(foob, oob, oob_size);
  1003. else {
  1004. /* Get HW generated ECC, made while writing data */
  1005. int ecc_count = nand->page_size == 2048 ? 8 : 2;
  1006. static uint32_t hw_ecc[8];
  1007. retval = target_read_memory(target, target_mem_base + ECC_OFFS,
  1008. 4, ecc_count, (uint8_t *)hw_ecc);
  1009. if (ERROR_OK != retval) {
  1010. LOG_ERROR("Reading hw generated ECC from IRAM failed");
  1011. return retval;
  1012. }
  1013. /* Copy to oob, at correct offsets */
  1014. static uint8_t ecc[24];
  1015. slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
  1016. int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
  1017. int i;
  1018. for (i = 0; i < ecc_count * 3; i++)
  1019. foob[layout[i]] = ecc[i];
  1020. lpc32xx_dump_oob(foob, foob_size);
  1021. }
  1022. retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
  1023. foob_size / 4, foob);
  1024. if (ERROR_OK != retval) {
  1025. LOG_ERROR("Writing OOB to IRAM failed");
  1026. return retval;
  1027. }
  1028. /* Write OOB decriptor to DMA controller */
  1029. retval = target_write_memory(target, 0x31000100, 4,
  1030. sizeof(dmac_ll_t) / 4,
  1031. (uint8_t *)(&dmalist[nll-1]));
  1032. if (ERROR_OK != retval) {
  1033. LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
  1034. return retval;
  1035. }
  1036. if (data) {
  1037. /* Only restart DMA with last descriptor,
  1038. * don't setup SLC again */
  1039. /* DMACIntTCClear = ch0 */
  1040. retval = target_write_u32(target, 0x31000008, 1);
  1041. if (ERROR_OK != retval) {
  1042. LOG_ERROR("Could not set DMACIntTCClear");
  1043. return retval;
  1044. }
  1045. /* DMACCxConfig=
  1046. * E=1,
  1047. * SrcPeripheral = 1 (SLC),
  1048. * DestPeripheral = 1 (SLC),
  1049. * FlowCntrl = 2 (Pher -> Mem, DMA),
  1050. * IE = 0,
  1051. * ITC = 0,
  1052. * L= 0,
  1053. * H=0
  1054. */
  1055. retval = target_write_u32(target, 0x31000110,
  1056. 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
  1057. | 0<<15 | 0<<16 | 0<<18);
  1058. if (ERROR_OK != retval) {
  1059. LOG_ERROR("Could not set DMACC0Config");
  1060. return retval;
  1061. }
  1062. /* Wait finish */
  1063. if (!lpc32xx_tc_ready(nand, 100)) {
  1064. LOG_ERROR("timeout while waiting for "
  1065. "completion of DMA");
  1066. return ERROR_NAND_OPERATION_FAILED;
  1067. }
  1068. } else {
  1069. /* Start xfer of data from iram to flash using DMA */
  1070. retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
  1071. if (ERROR_OK != retval) {
  1072. LOG_ERROR("DMA OOB failed");
  1073. return retval;
  1074. }
  1075. }
  1076. /* Let NAND start actual writing */
  1077. retval = nand_write_finish(nand);
  1078. if (ERROR_OK != retval) {
  1079. LOG_ERROR("nand_write_finish failed");
  1080. return retval;
  1081. }
  1082. return ERROR_OK;
  1083. }
  1084. static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
  1085. uint8_t *data, uint32_t data_size,
  1086. uint8_t *oob, uint32_t oob_size)
  1087. {
  1088. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  1089. struct target *target = nand->target;
  1090. int retval = ERROR_OK;
  1091. if (target->state != TARGET_HALTED) {
  1092. LOG_ERROR("target must be halted to use LPC32xx "
  1093. "NAND flash controller");
  1094. return ERROR_NAND_OPERATION_FAILED;
  1095. }
  1096. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  1097. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  1098. return ERROR_NAND_OPERATION_FAILED;
  1099. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  1100. if (!data && oob) {
  1101. LOG_ERROR("LPC32xx MLC controller can't write "
  1102. "OOB data only");
  1103. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  1104. }
  1105. if (oob && (oob_size > 24)) {
  1106. LOG_ERROR("LPC32xx MLC controller can't write more "
  1107. "than 6 bytes for each quarter's OOB data");
  1108. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  1109. }
  1110. if (data_size > (uint32_t)nand->page_size) {
  1111. LOG_ERROR("data size exceeds page size");
  1112. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  1113. }
  1114. retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
  1115. oob, oob_size);
  1116. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  1117. struct working_area *pworking_area;
  1118. if (!data && oob) {
  1119. /*
  1120. * if oob only mode is active original method is used
  1121. * as SLC controller hangs during DMA interworking. (?)
  1122. * Anyway the code supports the oob only mode below.
  1123. */
  1124. return nand_write_page_raw(nand, page, data,
  1125. data_size, oob, oob_size);
  1126. }
  1127. retval = target_alloc_working_area(target,
  1128. nand->page_size + DATA_OFFS,
  1129. &pworking_area);
  1130. if (retval != ERROR_OK) {
  1131. LOG_ERROR("Can't allocate working area in "
  1132. "LPC internal RAM");
  1133. return ERROR_FLASH_OPERATION_FAILED;
  1134. }
  1135. retval = lpc32xx_write_page_slc(nand, pworking_area, page,
  1136. data, data_size, oob, oob_size);
  1137. target_free_working_area(target, pworking_area);
  1138. }
  1139. return retval;
  1140. }
  1141. static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
  1142. uint8_t *data, uint32_t data_size,
  1143. uint8_t *oob, uint32_t oob_size)
  1144. {
  1145. struct target *target = nand->target;
  1146. static uint8_t page_buffer[2048];
  1147. static uint8_t oob_buffer[64];
  1148. uint32_t page_bytes_done = 0;
  1149. uint32_t oob_bytes_done = 0;
  1150. uint32_t mlc_isr;
  1151. int retval;
  1152. if (!data && oob) {
  1153. /* MLC_CMD = Read OOB
  1154. * we can use the READOOB command on both small and large page
  1155. * devices, as the controller translates the 0x50 command to
  1156. * a 0x0 with appropriate positioning of the serial buffer
  1157. * read pointer
  1158. */
  1159. retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
  1160. } else {
  1161. /* MLC_CMD = Read0 */
  1162. retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
  1163. }
  1164. if (ERROR_OK != retval) {
  1165. LOG_ERROR("could not set MLC_CMD");
  1166. return ERROR_NAND_OPERATION_FAILED;
  1167. }
  1168. if (nand->page_size == 512) {
  1169. /* small page device
  1170. * MLC_ADDR = 0x0 (one column cycle) */
  1171. retval = target_write_u32(target, 0x200b8004, 0x0);
  1172. if (ERROR_OK != retval) {
  1173. LOG_ERROR("could not set MLC_ADDR");
  1174. return ERROR_NAND_OPERATION_FAILED;
  1175. }
  1176. /* MLC_ADDR = row */
  1177. retval = target_write_u32(target, 0x200b8004, page & 0xff);
  1178. if (ERROR_OK != retval) {
  1179. LOG_ERROR("could not set MLC_ADDR");
  1180. return ERROR_NAND_OPERATION_FAILED;
  1181. }
  1182. retval = target_write_u32(target, 0x200b8004,
  1183. (page >> 8) & 0xff);
  1184. if (ERROR_OK != retval) {
  1185. LOG_ERROR("could not set MLC_ADDR");
  1186. return ERROR_NAND_OPERATION_FAILED;
  1187. }
  1188. if (nand->address_cycles == 4) {
  1189. retval = target_write_u32(target, 0x200b8004,
  1190. (page >> 16) & 0xff);
  1191. if (ERROR_OK != retval) {
  1192. LOG_ERROR("could not set MLC_ADDR");
  1193. return ERROR_NAND_OPERATION_FAILED;
  1194. }
  1195. }
  1196. } else {
  1197. /* large page device
  1198. * MLC_ADDR = 0x0 (two column cycles) */
  1199. retval = target_write_u32(target, 0x200b8004, 0x0);
  1200. if (ERROR_OK != retval) {
  1201. LOG_ERROR("could not set MLC_ADDR");
  1202. return ERROR_NAND_OPERATION_FAILED;
  1203. }
  1204. retval = target_write_u32(target, 0x200b8004, 0x0);
  1205. if (ERROR_OK != retval) {
  1206. LOG_ERROR("could not set MLC_ADDR");
  1207. return ERROR_NAND_OPERATION_FAILED;
  1208. }
  1209. /* MLC_ADDR = row */
  1210. retval = target_write_u32(target, 0x200b8004, page & 0xff);
  1211. if (ERROR_OK != retval) {
  1212. LOG_ERROR("could not set MLC_ADDR");
  1213. return ERROR_NAND_OPERATION_FAILED;
  1214. }
  1215. retval = target_write_u32(target, 0x200b8004,
  1216. (page >> 8) & 0xff);
  1217. if (ERROR_OK != retval) {
  1218. LOG_ERROR("could not set MLC_ADDR");
  1219. return ERROR_NAND_OPERATION_FAILED;
  1220. }
  1221. /* MLC_CMD = Read Start */
  1222. retval = target_write_u32(target, 0x200b8000,
  1223. NAND_CMD_READSTART);
  1224. if (ERROR_OK != retval) {
  1225. LOG_ERROR("could not set MLC_CMD");
  1226. return ERROR_NAND_OPERATION_FAILED;
  1227. }
  1228. }
  1229. while (page_bytes_done < (uint32_t)nand->page_size) {
  1230. /* MLC_ECC_AUTO_DEC_REG = dummy */
  1231. retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
  1232. if (ERROR_OK != retval) {
  1233. LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
  1234. return ERROR_NAND_OPERATION_FAILED;
  1235. }
  1236. if (!lpc32xx_controller_ready(nand, 1000)) {
  1237. LOG_ERROR("timeout while waiting for "
  1238. "completion of auto decode cycle");
  1239. return ERROR_NAND_OPERATION_FAILED;
  1240. }
  1241. retval = target_read_u32(target, 0x200b8048, &mlc_isr);
  1242. if (ERROR_OK != retval) {
  1243. LOG_ERROR("could not read MLC_ISR");
  1244. return ERROR_NAND_OPERATION_FAILED;
  1245. }
  1246. if (mlc_isr & 0x8) {
  1247. if (mlc_isr & 0x40) {
  1248. LOG_ERROR("uncorrectable error detected: "
  1249. "0x%2.2x", (unsigned)mlc_isr);
  1250. return ERROR_NAND_OPERATION_FAILED;
  1251. }
  1252. LOG_WARNING("%i symbol error detected and corrected",
  1253. ((int)(((mlc_isr & 0x30) >> 4) + 1)));
  1254. }
  1255. if (data) {
  1256. retval = target_read_memory(target, 0x200a8000, 4, 128,
  1257. page_buffer + page_bytes_done);
  1258. if (ERROR_OK != retval) {
  1259. LOG_ERROR("could not read MLC_BUF (data)");
  1260. return ERROR_NAND_OPERATION_FAILED;
  1261. }
  1262. }
  1263. if (oob) {
  1264. retval = target_read_memory(target, 0x200a8000, 4, 4,
  1265. oob_buffer + oob_bytes_done);
  1266. if (ERROR_OK != retval) {
  1267. LOG_ERROR("could not read MLC_BUF (oob)");
  1268. return ERROR_NAND_OPERATION_FAILED;
  1269. }
  1270. }
  1271. page_bytes_done += 512;
  1272. oob_bytes_done += 16;
  1273. }
  1274. if (data)
  1275. memcpy(data, page_buffer, data_size);
  1276. if (oob)
  1277. memcpy(oob, oob_buffer, oob_size);
  1278. return ERROR_OK;
  1279. }
  1280. static int lpc32xx_read_page_slc(struct nand_device *nand,
  1281. struct working_area *pworking_area,
  1282. uint32_t page, uint8_t *data,
  1283. uint32_t data_size, uint8_t *oob,
  1284. uint32_t oob_size)
  1285. {
  1286. struct target *target = nand->target;
  1287. int retval;
  1288. uint32_t target_mem_base;
  1289. LOG_DEBUG("SLC read page %x data=%d, oob=%d",
  1290. page, data_size, oob_size);
  1291. target_mem_base = pworking_area->address;
  1292. /* Make the dma descriptors in local memory */
  1293. int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
  1294. /* Write them to target.
  1295. XXX: Assumes host and target have same byte sex.
  1296. */
  1297. retval = target_write_memory(target, target_mem_base, 4,
  1298. nll * sizeof(dmac_ll_t) / 4,
  1299. (uint8_t *)dmalist);
  1300. if (ERROR_OK != retval) {
  1301. LOG_ERROR("Could not write DMA descriptors to IRAM");
  1302. return retval;
  1303. }
  1304. retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
  1305. if (ERROR_OK != retval) {
  1306. LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
  1307. return retval;
  1308. }
  1309. /* SLC_CFG =
  1310. Force nCE assert,
  1311. DMA ECC enabled,
  1312. ECC enabled,
  1313. DMA burst enabled,
  1314. DMA read from SLC,
  1315. WIDTH = bus_width
  1316. */
  1317. retval = target_write_u32(target, 0x20020014, 0x3e);
  1318. if (ERROR_OK != retval) {
  1319. LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
  1320. return retval;
  1321. }
  1322. /* Write first decriptor to DMA controller */
  1323. retval = target_write_memory(target, 0x31000100, 4,
  1324. sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
  1325. if (ERROR_OK != retval) {
  1326. LOG_ERROR("Could not write DMA descriptor to DMAC");
  1327. return retval;
  1328. }
  1329. /* Start xfer of data from flash to iram using DMA */
  1330. int tot_size = nand->page_size;
  1331. tot_size += nand->page_size == 2048 ? 64 : 16;
  1332. retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
  1333. if (ERROR_OK != retval) {
  1334. LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
  1335. return retval;
  1336. }
  1337. /* Copy data from iram */
  1338. if (data) {
  1339. retval = target_read_memory(target, target_mem_base + DATA_OFFS,
  1340. 4, data_size/4, data);
  1341. if (ERROR_OK != retval) {
  1342. LOG_ERROR("Could not read data from IRAM");
  1343. return retval;
  1344. }
  1345. }
  1346. if (oob) {
  1347. /* No error correction, just return data as read from flash */
  1348. retval = target_read_memory(target,
  1349. target_mem_base + SPARE_OFFS, 4,
  1350. oob_size/4, oob);
  1351. if (ERROR_OK != retval) {
  1352. LOG_ERROR("Could not read OOB from IRAM");
  1353. return retval;
  1354. }
  1355. return ERROR_OK;
  1356. }
  1357. /* Copy OOB from flash, stored in IRAM */
  1358. static uint8_t foob[64];
  1359. retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
  1360. 4, nand->page_size == 2048 ? 16 : 4, foob);
  1361. lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
  1362. if (ERROR_OK != retval) {
  1363. LOG_ERROR("Could not read OOB from IRAM");
  1364. return retval;
  1365. }
  1366. /* Copy ECC from HW, generated while reading */
  1367. int ecc_count = nand->page_size == 2048 ? 8 : 2;
  1368. static uint32_t hw_ecc[8]; /* max size */
  1369. retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
  1370. ecc_count, (uint8_t *)hw_ecc);
  1371. if (ERROR_OK != retval) {
  1372. LOG_ERROR("Could not read hw generated ECC from IRAM");
  1373. return retval;
  1374. }
  1375. static uint8_t ecc[24];
  1376. slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
  1377. /* Copy ECC from flash using correct layout */
  1378. static uint8_t fecc[24];/* max size */
  1379. int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
  1380. int i;
  1381. for (i = 0; i < ecc_count * 3; i++)
  1382. fecc[i] = foob[layout[i]];
  1383. /* Compare ECC and possibly correct data */
  1384. for (i = 0; i < ecc_count; i++) {
  1385. retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
  1386. &ecc[i * 3]);
  1387. if (retval > 0)
  1388. LOG_WARNING("error detected and corrected: %d/%d",
  1389. page, i);
  1390. if (retval < 0)
  1391. break;
  1392. }
  1393. if (i == ecc_count)
  1394. retval = ERROR_OK;
  1395. else {
  1396. LOG_ERROR("uncorrectable error detected: %d/%d", page, i);
  1397. retval = ERROR_NAND_OPERATION_FAILED;
  1398. }
  1399. return retval;
  1400. }
  1401. static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
  1402. uint8_t *data, uint32_t data_size,
  1403. uint8_t *oob, uint32_t oob_size)
  1404. {
  1405. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  1406. struct target *target = nand->target;
  1407. int retval = ERROR_OK;
  1408. if (target->state != TARGET_HALTED) {
  1409. LOG_ERROR("target must be halted to use LPC32xx "
  1410. "NAND flash controller");
  1411. return ERROR_NAND_OPERATION_FAILED;
  1412. }
  1413. if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
  1414. LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
  1415. return ERROR_NAND_OPERATION_FAILED;
  1416. } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  1417. if (data_size > (uint32_t)nand->page_size) {
  1418. LOG_ERROR("data size exceeds page size");
  1419. return ERROR_NAND_OPERATION_NOT_SUPPORTED;
  1420. }
  1421. retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
  1422. oob, oob_size);
  1423. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  1424. struct working_area *pworking_area;
  1425. retval = target_alloc_working_area(target,
  1426. nand->page_size + 0x200,
  1427. &pworking_area);
  1428. if (retval != ERROR_OK) {
  1429. LOG_ERROR("Can't allocate working area in "
  1430. "LPC internal RAM");
  1431. return ERROR_FLASH_OPERATION_FAILED;
  1432. }
  1433. retval = lpc32xx_read_page_slc(nand, pworking_area, page,
  1434. data, data_size, oob, oob_size);
  1435. target_free_working_area(target, pworking_area);
  1436. }
  1437. return retval;
  1438. }
  1439. static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
  1440. {
  1441. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  1442. struct target *target = nand->target;
  1443. int retval;
  1444. if (target->state != TARGET_HALTED) {
  1445. LOG_ERROR("target must be halted to use LPC32xx "
  1446. "NAND flash controller");
  1447. return ERROR_NAND_OPERATION_FAILED;
  1448. }
  1449. LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
  1450. do {
  1451. if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  1452. uint8_t status;
  1453. /* Read MLC_ISR, wait for controller to become ready */
  1454. retval = target_read_u8(target, 0x200b8048, &status);
  1455. if (ERROR_OK != retval) {
  1456. LOG_ERROR("could not set MLC_STAT");
  1457. return ERROR_NAND_OPERATION_FAILED;
  1458. }
  1459. if (status & 2) {
  1460. LOG_DEBUG("lpc32xx_controller_ready count=%d",
  1461. timeout);
  1462. return 1;
  1463. }
  1464. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  1465. uint32_t status;
  1466. /* Read SLC_STAT and check READY bit */
  1467. retval = target_read_u32(target, 0x20020018, &status);
  1468. if (ERROR_OK != retval) {
  1469. LOG_ERROR("could not set SLC_STAT");
  1470. return ERROR_NAND_OPERATION_FAILED;
  1471. }
  1472. if (status & 1) {
  1473. LOG_DEBUG("lpc32xx_controller_ready count=%d",
  1474. timeout);
  1475. return 1;
  1476. }
  1477. }
  1478. alive_sleep(1);
  1479. } while (timeout-- > 0);
  1480. return 0;
  1481. }
  1482. static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
  1483. {
  1484. struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
  1485. struct target *target = nand->target;
  1486. int retval;
  1487. if (target->state != TARGET_HALTED) {
  1488. LOG_ERROR("target must be halted to use LPC32xx "
  1489. "NAND flash controller");
  1490. return ERROR_NAND_OPERATION_FAILED;
  1491. }
  1492. LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
  1493. do {
  1494. if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
  1495. uint8_t status = 0x0;
  1496. /* Read MLC_ISR, wait for NAND flash device to
  1497. * become ready */
  1498. retval = target_read_u8(target, 0x200b8048, &status);
  1499. if (ERROR_OK != retval) {
  1500. LOG_ERROR("could not read MLC_ISR");
  1501. return ERROR_NAND_OPERATION_FAILED;
  1502. }
  1503. if (status & 1) {
  1504. LOG_DEBUG("lpc32xx_nand_ready count end=%d",
  1505. timeout);
  1506. return 1;
  1507. }
  1508. } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
  1509. uint32_t status = 0x0;
  1510. /* Read SLC_STAT and check READY bit */
  1511. retval = target_read_u32(target, 0x20020018, &status);
  1512. if (ERROR_OK != retval) {
  1513. LOG_ERROR("could not read SLC_STAT");
  1514. return ERROR_NAND_OPERATION_FAILED;
  1515. }
  1516. if (status & 1) {
  1517. LOG_DEBUG("lpc32xx_nand_ready count end=%d",
  1518. timeout);
  1519. return 1;
  1520. }
  1521. }
  1522. alive_sleep(1);
  1523. } while (timeout-- > 0);
  1524. return 0;
  1525. }
  1526. static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
  1527. {
  1528. struct target *target = nand->target;
  1529. LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
  1530. do {
  1531. uint32_t status = 0x0;
  1532. int retval;
  1533. /* Read SLC_INT_STAT and check INT_TC_STAT bit */
  1534. retval = target_read_u32(target, 0x2002001c, &status);
  1535. if (ERROR_OK != retval) {
  1536. LOG_ERROR("Could not read SLC_INT_STAT");
  1537. return 0;
  1538. }
  1539. if (status & 2) {
  1540. LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
  1541. return 1;
  1542. }
  1543. alive_sleep(1);
  1544. } while (timeout-- > 0);
  1545. return 0;
  1546. }
  1547. COMMAND_HANDLER(handle_lpc32xx_select_command)
  1548. {
  1549. struct lpc32xx_nand_controller *lpc32xx_info = NULL;
  1550. char *selected[] = {
  1551. "no", "mlc", "slc"
  1552. };
  1553. if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
  1554. return ERROR_COMMAND_SYNTAX_ERROR;
  1555. unsigned num;
  1556. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
  1557. struct nand_device *nand = get_nand_device_by_num(num);
  1558. if (!nand) {
  1559. command_print(CMD_CTX, "nand device '#%s' is out of bounds",
  1560. CMD_ARGV[0]);
  1561. return ERROR_OK;
  1562. }
  1563. lpc32xx_info = nand->controller_priv;
  1564. if (CMD_ARGC >= 2) {
  1565. if (strcmp(CMD_ARGV[1], "mlc") == 0) {
  1566. lpc32xx_info->selected_controller =
  1567. LPC32xx_MLC_CONTROLLER;
  1568. } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
  1569. lpc32xx_info->selected_controller =
  1570. LPC32xx_SLC_CONTROLLER;
  1571. } else
  1572. return ERROR_COMMAND_SYNTAX_ERROR;
  1573. }
  1574. command_print(CMD_CTX, "%s controller selected",
  1575. selected[lpc32xx_info->selected_controller]);
  1576. return ERROR_OK;
  1577. }
  1578. static const struct command_registration lpc32xx_exec_command_handlers[] = {
  1579. {
  1580. .name = "select",
  1581. .handler = handle_lpc32xx_select_command,
  1582. .mode = COMMAND_EXEC,
  1583. .help = "select MLC or SLC controller (default is MLC)",
  1584. .usage = "bank_id ['mlc'|'slc' ]",
  1585. },
  1586. COMMAND_REGISTRATION_DONE
  1587. };
  1588. static const struct command_registration lpc32xx_command_handler[] = {
  1589. {
  1590. .name = "lpc32xx",
  1591. .mode = COMMAND_ANY,
  1592. .help = "LPC32xx NAND flash controller commands",
  1593. .usage = "",
  1594. .chain = lpc32xx_exec_command_handlers,
  1595. },
  1596. COMMAND_REGISTRATION_DONE
  1597. };
  1598. struct nand_flash_controller lpc32xx_nand_controller = {
  1599. .name = "lpc32xx",
  1600. .commands = lpc32xx_command_handler,
  1601. .nand_device_command = lpc32xx_nand_device_command,
  1602. .init = lpc32xx_init,
  1603. .reset = lpc32xx_reset,
  1604. .command = lpc32xx_command,
  1605. .address = lpc32xx_address,
  1606. .write_data = lpc32xx_write_data,
  1607. .read_data = lpc32xx_read_data,
  1608. .write_page = lpc32xx_write_page,
  1609. .read_page = lpc32xx_read_page,
  1610. .nand_ready = lpc32xx_nand_ready,
  1611. };