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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Alexei Babich *
  3. * Rezonans plc., Chelyabinsk, Russia *
  4. * impatt@mail.ru *
  5. * *
  6. * This program is free software; you can redistribute it and/or modify *
  7. * it under the terms of the GNU General Public License as published by *
  8. * the Free Software Foundation; either version 2 of the License, or *
  9. * (at your option) any later version. *
  10. * *
  11. * This program is distributed in the hope that it will be useful, *
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  14. * GNU General Public License for more details. *
  15. * *
  16. * You should have received a copy of the GNU General Public License *
  17. * along with this program; if not, write to the *
  18. * Free Software Foundation, Inc., *
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  20. ***************************************************************************/
  21. /*
  22. * Freescale iMX3* OpenOCD NAND Flash controller support.
  23. *
  24. * Many thanks to Ben Dooks for writing s3c24xx driver.
  25. */
  26. /*
  27. driver tested with STMicro NAND512W3A @imx31
  28. tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
  29. get_next_halfword_from_sram_buffer() not tested
  30. */
  31. #ifdef HAVE_CONFIG_H
  32. #include "config.h"
  33. #endif
  34. #include "imp.h"
  35. #include "mx3.h"
  36. #include <target/target.h>
  37. static const char target_not_halted_err_msg[] =
  38. "target must be halted to use mx3 NAND flash controller";
  39. static const char data_block_size_err_msg[] =
  40. "minimal granularity is one half-word, %" PRId32 " is incorrect";
  41. static const char sram_buffer_bounds_err_msg[] =
  42. "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  43. static const char get_status_register_err_msg[] = "can't get NAND status";
  44. static uint32_t in_sram_address;
  45. static unsigned char sign_of_sequental_byte_read;
  46. static int test_iomux_settings(struct target *target, uint32_t value,
  47. uint32_t mask, const char *text);
  48. static int initialize_nf_controller(struct nand_device *nand);
  49. static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
  50. static int get_next_halfword_from_sram_buffer(struct target *target,
  51. uint16_t *value);
  52. static int poll_for_complete_op(struct target *target, const char *text);
  53. static int validate_target_state(struct nand_device *nand);
  54. static int do_data_output(struct nand_device *nand);
  55. static int imx31_command(struct nand_device *nand, uint8_t command);
  56. static int imx31_address(struct nand_device *nand, uint8_t address);
  57. NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
  58. {
  59. struct mx3_nf_controller *mx3_nf_info;
  60. mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
  61. if (mx3_nf_info == NULL) {
  62. LOG_ERROR("no memory for nand controller");
  63. return ERROR_FAIL;
  64. }
  65. nand->controller_priv = mx3_nf_info;
  66. if (CMD_ARGC < 3)
  67. return ERROR_COMMAND_SYNTAX_ERROR;
  68. /*
  69. * check hwecc requirements
  70. */
  71. {
  72. int hwecc_needed;
  73. hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
  74. if (hwecc_needed == 0)
  75. mx3_nf_info->flags.hw_ecc_enabled = 1;
  76. else
  77. mx3_nf_info->flags.hw_ecc_enabled = 0;
  78. }
  79. mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
  80. mx3_nf_info->fin = MX3_NF_FIN_NONE;
  81. mx3_nf_info->flags.target_little_endian =
  82. (nand->target->endianness == TARGET_LITTLE_ENDIAN);
  83. /*
  84. * testing host endianness
  85. */
  86. {
  87. int x = 1;
  88. if (*(char *) &x == 1)
  89. mx3_nf_info->flags.host_little_endian = 1;
  90. else
  91. mx3_nf_info->flags.host_little_endian = 0;
  92. }
  93. return ERROR_OK;
  94. }
  95. static int imx31_init(struct nand_device *nand)
  96. {
  97. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  98. struct target *target = nand->target;
  99. {
  100. /*
  101. * validate target state
  102. */
  103. int validate_target_result;
  104. validate_target_result = validate_target_state(nand);
  105. if (validate_target_result != ERROR_OK)
  106. return validate_target_result;
  107. }
  108. {
  109. uint16_t buffsize_register_content;
  110. target_read_u16(target, MX3_NF_BUFSIZ, &buffsize_register_content);
  111. mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
  112. }
  113. {
  114. uint32_t pcsr_register_content;
  115. target_read_u32(target, MX3_PCSR, &pcsr_register_content);
  116. if (!nand->bus_width) {
  117. nand->bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
  118. } else {
  119. pcsr_register_content |= ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
  120. target_write_u32(target, MX3_PCSR, pcsr_register_content);
  121. }
  122. if (!nand->page_size) {
  123. nand->page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
  124. } else {
  125. pcsr_register_content |= ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
  126. target_write_u32(target, MX3_PCSR, pcsr_register_content);
  127. }
  128. if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
  129. LOG_ERROR("NAND controller have only 1 kb SRAM, "
  130. "so pagesize 2048 is incompatible with it");
  131. }
  132. }
  133. {
  134. uint32_t cgr_register_content;
  135. target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
  136. if (!(cgr_register_content & 0x00000300)) {
  137. LOG_ERROR("clock gating to EMI disabled");
  138. return ERROR_FAIL;
  139. }
  140. }
  141. {
  142. uint32_t gpr_register_content;
  143. target_read_u32(target, MX3_GPR, &gpr_register_content);
  144. if (gpr_register_content & 0x00000060) {
  145. LOG_ERROR("pins mode overrided by GPR");
  146. return ERROR_FAIL;
  147. }
  148. }
  149. {
  150. /*
  151. * testing IOMUX settings; must be in "functional-mode output and
  152. * functional-mode input" mode
  153. */
  154. int test_iomux;
  155. test_iomux = ERROR_OK;
  156. test_iomux |= test_iomux_settings(target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
  157. test_iomux |= test_iomux_settings(target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
  158. test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x0000007f, "d7");
  159. if (nand->bus_width == 16) {
  160. test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
  161. test_iomux |= test_iomux_settings(target, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
  162. test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x0000007f, "d15");
  163. }
  164. test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
  165. test_iomux |= test_iomux_settings(target, 0x43fac0d4, 0x7f7f7f7f,
  166. "nfwe,nfre,nfale,nfcle");
  167. if (test_iomux != ERROR_OK)
  168. return ERROR_FAIL;
  169. }
  170. initialize_nf_controller(nand);
  171. {
  172. int retval;
  173. uint16_t nand_status_content;
  174. retval = ERROR_OK;
  175. retval |= imx31_command(nand, NAND_CMD_STATUS);
  176. retval |= imx31_address(nand, 0x00);
  177. retval |= do_data_output(nand);
  178. if (retval != ERROR_OK) {
  179. LOG_ERROR(get_status_register_err_msg);
  180. return ERROR_FAIL;
  181. }
  182. target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
  183. if (!(nand_status_content & 0x0080)) {
  184. /*
  185. * is host-big-endian correctly ??
  186. */
  187. LOG_INFO("NAND read-only");
  188. mx3_nf_info->flags.nand_readonly = 1;
  189. } else
  190. mx3_nf_info->flags.nand_readonly = 0;
  191. }
  192. return ERROR_OK;
  193. }
  194. static int imx31_read_data(struct nand_device *nand, void *data)
  195. {
  196. struct target *target = nand->target;
  197. {
  198. /*
  199. * validate target state
  200. */
  201. int validate_target_result;
  202. validate_target_result = validate_target_state(nand);
  203. if (validate_target_result != ERROR_OK)
  204. return validate_target_result;
  205. }
  206. {
  207. /*
  208. * get data from nand chip
  209. */
  210. int try_data_output_from_nand_chip;
  211. try_data_output_from_nand_chip = do_data_output(nand);
  212. if (try_data_output_from_nand_chip != ERROR_OK)
  213. return try_data_output_from_nand_chip;
  214. }
  215. if (nand->bus_width == 16)
  216. get_next_halfword_from_sram_buffer(target, data);
  217. else
  218. get_next_byte_from_sram_buffer(target, data);
  219. return ERROR_OK;
  220. }
  221. static int imx31_write_data(struct nand_device *nand, uint16_t data)
  222. {
  223. LOG_ERROR("write_data() not implemented");
  224. return ERROR_NAND_OPERATION_FAILED;
  225. }
  226. static int imx31_reset(struct nand_device *nand)
  227. {
  228. /*
  229. * validate target state
  230. */
  231. int validate_target_result;
  232. validate_target_result = validate_target_state(nand);
  233. if (validate_target_result != ERROR_OK)
  234. return validate_target_result;
  235. initialize_nf_controller(nand);
  236. return ERROR_OK;
  237. }
  238. static int imx31_command(struct nand_device *nand, uint8_t command)
  239. {
  240. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  241. struct target *target = nand->target;
  242. {
  243. /*
  244. * validate target state
  245. */
  246. int validate_target_result;
  247. validate_target_result = validate_target_state(nand);
  248. if (validate_target_result != ERROR_OK)
  249. return validate_target_result;
  250. }
  251. switch (command) {
  252. case NAND_CMD_READOOB:
  253. command = NAND_CMD_READ0;
  254. in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
  255. * data_read() and
  256. * read_block_data() to
  257. * spare area in SRAM
  258. * buffer */
  259. break;
  260. case NAND_CMD_READ1:
  261. command = NAND_CMD_READ0;
  262. /*
  263. * offset == one half of page size
  264. */
  265. in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
  266. default:
  267. in_sram_address = MX3_NF_MAIN_BUFFER0;
  268. }
  269. target_write_u16(target, MX3_NF_FCMD, command);
  270. /*
  271. * start command input operation (set MX3_NF_BIT_OP_DONE==0)
  272. */
  273. target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
  274. {
  275. int poll_result;
  276. poll_result = poll_for_complete_op(target, "command");
  277. if (poll_result != ERROR_OK)
  278. return poll_result;
  279. }
  280. /*
  281. * reset cursor to begin of the buffer
  282. */
  283. sign_of_sequental_byte_read = 0;
  284. switch (command) {
  285. case NAND_CMD_READID:
  286. mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
  287. mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
  288. break;
  289. case NAND_CMD_STATUS:
  290. mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
  291. mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
  292. break;
  293. case NAND_CMD_READ0:
  294. mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
  295. mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
  296. break;
  297. default:
  298. mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
  299. }
  300. return ERROR_OK;
  301. }
  302. static int imx31_address(struct nand_device *nand, uint8_t address)
  303. {
  304. struct target *target = nand->target;
  305. {
  306. /*
  307. * validate target state
  308. */
  309. int validate_target_result;
  310. validate_target_result = validate_target_state(nand);
  311. if (validate_target_result != ERROR_OK)
  312. return validate_target_result;
  313. }
  314. target_write_u16(target, MX3_NF_FADDR, address);
  315. /*
  316. * start address input operation (set MX3_NF_BIT_OP_DONE==0)
  317. */
  318. target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
  319. {
  320. int poll_result;
  321. poll_result = poll_for_complete_op(target, "address");
  322. if (poll_result != ERROR_OK)
  323. return poll_result;
  324. }
  325. return ERROR_OK;
  326. }
  327. static int imx31_nand_ready(struct nand_device *nand, int tout)
  328. {
  329. uint16_t poll_complete_status;
  330. struct target *target = nand->target;
  331. {
  332. /*
  333. * validate target state
  334. */
  335. int validate_target_result;
  336. validate_target_result = validate_target_state(nand);
  337. if (validate_target_result != ERROR_OK)
  338. return validate_target_result;
  339. }
  340. do {
  341. target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
  342. if (poll_complete_status & MX3_NF_BIT_OP_DONE)
  343. return tout;
  344. alive_sleep(1);
  345. } while (tout-- > 0);
  346. return tout;
  347. }
  348. static int imx31_write_page(struct nand_device *nand, uint32_t page,
  349. uint8_t *data, uint32_t data_size, uint8_t *oob,
  350. uint32_t oob_size)
  351. {
  352. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  353. struct target *target = nand->target;
  354. if (data_size % 2) {
  355. LOG_ERROR(data_block_size_err_msg, data_size);
  356. return ERROR_NAND_OPERATION_FAILED;
  357. }
  358. if (oob_size % 2) {
  359. LOG_ERROR(data_block_size_err_msg, oob_size);
  360. return ERROR_NAND_OPERATION_FAILED;
  361. }
  362. if (!data) {
  363. LOG_ERROR("nothing to program");
  364. return ERROR_NAND_OPERATION_FAILED;
  365. }
  366. {
  367. /*
  368. * validate target state
  369. */
  370. int retval;
  371. retval = validate_target_state(nand);
  372. if (retval != ERROR_OK)
  373. return retval;
  374. }
  375. {
  376. int retval = ERROR_OK;
  377. retval |= imx31_command(nand, NAND_CMD_SEQIN);
  378. retval |= imx31_address(nand, 0x00);
  379. retval |= imx31_address(nand, page & 0xff);
  380. retval |= imx31_address(nand, (page >> 8) & 0xff);
  381. if (nand->address_cycles >= 4) {
  382. retval |= imx31_address(nand, (page >> 16) & 0xff);
  383. if (nand->address_cycles >= 5)
  384. retval |= imx31_address(nand, (page >> 24) & 0xff);
  385. }
  386. target_write_buffer(target, MX3_NF_MAIN_BUFFER0, data_size, data);
  387. if (oob) {
  388. if (mx3_nf_info->flags.hw_ecc_enabled) {
  389. /*
  390. * part of spare block will be overrided by hardware
  391. * ECC generator
  392. */
  393. LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
  394. }
  395. target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
  396. }
  397. /*
  398. * start data input operation (set MX3_NF_BIT_OP_DONE==0)
  399. */
  400. target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
  401. {
  402. int poll_result;
  403. poll_result = poll_for_complete_op(target, "data input");
  404. if (poll_result != ERROR_OK)
  405. return poll_result;
  406. }
  407. retval |= imx31_command(nand, NAND_CMD_PAGEPROG);
  408. if (retval != ERROR_OK)
  409. return retval;
  410. /*
  411. * check status register
  412. */
  413. {
  414. uint16_t nand_status_content;
  415. retval = ERROR_OK;
  416. retval |= imx31_command(nand, NAND_CMD_STATUS);
  417. retval |= imx31_address(nand, 0x00);
  418. retval |= do_data_output(nand);
  419. if (retval != ERROR_OK) {
  420. LOG_ERROR(get_status_register_err_msg);
  421. return retval;
  422. }
  423. target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
  424. if (nand_status_content & 0x0001) {
  425. /*
  426. * is host-big-endian correctly ??
  427. */
  428. return ERROR_NAND_OPERATION_FAILED;
  429. }
  430. }
  431. }
  432. return ERROR_OK;
  433. }
  434. static int imx31_read_page(struct nand_device *nand, uint32_t page,
  435. uint8_t *data, uint32_t data_size, uint8_t *oob,
  436. uint32_t oob_size)
  437. {
  438. struct target *target = nand->target;
  439. if (data_size % 2) {
  440. LOG_ERROR(data_block_size_err_msg, data_size);
  441. return ERROR_NAND_OPERATION_FAILED;
  442. }
  443. if (oob_size % 2) {
  444. LOG_ERROR(data_block_size_err_msg, oob_size);
  445. return ERROR_NAND_OPERATION_FAILED;
  446. }
  447. {
  448. /*
  449. * validate target state
  450. */
  451. int retval;
  452. retval = validate_target_state(nand);
  453. if (retval != ERROR_OK)
  454. return retval;
  455. }
  456. {
  457. int retval = ERROR_OK;
  458. retval |= imx31_command(nand, NAND_CMD_READ0);
  459. retval |= imx31_address(nand, 0x00);
  460. retval |= imx31_address(nand, page & 0xff);
  461. retval |= imx31_address(nand, (page >> 8) & 0xff);
  462. if (nand->address_cycles >= 4) {
  463. retval |= imx31_address(nand, (page >> 16) & 0xff);
  464. if (nand->address_cycles >= 5) {
  465. retval |= imx31_address(nand, (page >> 24) & 0xff);
  466. retval |= imx31_command(nand, NAND_CMD_READSTART);
  467. }
  468. }
  469. retval |= do_data_output(nand);
  470. if (retval != ERROR_OK)
  471. return retval;
  472. if (data) {
  473. target_read_buffer(target, MX3_NF_MAIN_BUFFER0, data_size,
  474. data);
  475. }
  476. if (oob) {
  477. target_read_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size,
  478. oob);
  479. }
  480. }
  481. return ERROR_OK;
  482. }
  483. static int test_iomux_settings(struct target *target, uint32_t address,
  484. uint32_t mask, const char *text)
  485. {
  486. uint32_t register_content;
  487. target_read_u32(target, address, &register_content);
  488. if ((register_content & mask) != (0x12121212 & mask)) {
  489. LOG_ERROR("IOMUX for {%s} is bad", text);
  490. return ERROR_FAIL;
  491. }
  492. return ERROR_OK;
  493. }
  494. static int initialize_nf_controller(struct nand_device *nand)
  495. {
  496. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  497. struct target *target = nand->target;
  498. /*
  499. * resets NAND flash controller in zero time ? I dont know.
  500. */
  501. target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
  502. {
  503. uint16_t work_mode;
  504. work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
  505. if (target->endianness == TARGET_BIG_ENDIAN)
  506. work_mode |= MX3_NF_BIT_BE_EN;
  507. if (mx3_nf_info->flags.hw_ecc_enabled)
  508. work_mode |= MX3_NF_BIT_ECC_EN;
  509. target_write_u16(target, MX3_NF_CFG1, work_mode);
  510. }
  511. /*
  512. * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
  513. */
  514. target_write_u16(target, MX3_NF_BUFCFG, 2);
  515. {
  516. uint16_t temp;
  517. target_read_u16(target, MX3_NF_FWP, &temp);
  518. if ((temp & 0x0007) == 1) {
  519. LOG_ERROR("NAND flash is tight-locked, reset needed");
  520. return ERROR_FAIL;
  521. }
  522. }
  523. /*
  524. * unlock NAND flash for write
  525. */
  526. target_write_u16(target, MX3_NF_FWP, 4);
  527. target_write_u16(target, MX3_NF_LOCKSTART, 0x0000);
  528. target_write_u16(target, MX3_NF_LOCKEND, 0xFFFF);
  529. /*
  530. * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
  531. */
  532. target_write_u16(target, MX3_NF_BUFADDR, 0x0000);
  533. /*
  534. * address of SRAM buffer
  535. */
  536. in_sram_address = MX3_NF_MAIN_BUFFER0;
  537. sign_of_sequental_byte_read = 0;
  538. return ERROR_OK;
  539. }
  540. static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
  541. {
  542. static uint8_t even_byte;
  543. /*
  544. * host-big_endian ??
  545. */
  546. if (sign_of_sequental_byte_read == 0)
  547. even_byte = 0;
  548. if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
  549. LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
  550. *value = 0;
  551. sign_of_sequental_byte_read = 0;
  552. even_byte = 0;
  553. return ERROR_NAND_OPERATION_FAILED;
  554. } else {
  555. uint16_t temp;
  556. target_read_u16(target, in_sram_address, &temp);
  557. if (even_byte) {
  558. *value = temp >> 8;
  559. even_byte = 0;
  560. in_sram_address += 2;
  561. } else {
  562. *value = temp & 0xff;
  563. even_byte = 1;
  564. }
  565. }
  566. sign_of_sequental_byte_read = 1;
  567. return ERROR_OK;
  568. }
  569. static int get_next_halfword_from_sram_buffer(struct target *target,
  570. uint16_t *value)
  571. {
  572. if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
  573. LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
  574. *value = 0;
  575. return ERROR_NAND_OPERATION_FAILED;
  576. } else {
  577. target_read_u16(target, in_sram_address, value);
  578. in_sram_address += 2;
  579. }
  580. return ERROR_OK;
  581. }
  582. static int poll_for_complete_op(struct target *target, const char *text)
  583. {
  584. uint16_t poll_complete_status;
  585. for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
  586. usleep(25);
  587. target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
  588. if (poll_complete_status & MX3_NF_BIT_OP_DONE)
  589. break;
  590. }
  591. if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) {
  592. LOG_ERROR("%s sending timeout", text);
  593. return ERROR_NAND_OPERATION_FAILED;
  594. }
  595. return ERROR_OK;
  596. }
  597. static int validate_target_state(struct nand_device *nand)
  598. {
  599. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  600. struct target *target = nand->target;
  601. if (target->state != TARGET_HALTED) {
  602. LOG_ERROR(target_not_halted_err_msg);
  603. return ERROR_NAND_OPERATION_FAILED;
  604. }
  605. if (mx3_nf_info->flags.target_little_endian !=
  606. (target->endianness == TARGET_LITTLE_ENDIAN)) {
  607. /*
  608. * endianness changed after NAND controller probed
  609. */
  610. return ERROR_NAND_OPERATION_FAILED;
  611. }
  612. return ERROR_OK;
  613. }
  614. static int do_data_output(struct nand_device *nand)
  615. {
  616. struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
  617. struct target *target = nand->target;
  618. switch (mx3_nf_info->fin) {
  619. case MX3_NF_FIN_DATAOUT:
  620. /*
  621. * start data output operation (set MX3_NF_BIT_OP_DONE==0)
  622. */
  623. target_write_u16 (target, MX3_NF_CFG2,
  624. MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
  625. {
  626. int poll_result;
  627. poll_result = poll_for_complete_op(target, "data output");
  628. if (poll_result != ERROR_OK)
  629. return poll_result;
  630. }
  631. mx3_nf_info->fin = MX3_NF_FIN_NONE;
  632. /*
  633. * ECC stuff
  634. */
  635. if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
  636. && mx3_nf_info->flags.hw_ecc_enabled) {
  637. uint16_t ecc_status;
  638. target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
  639. switch (ecc_status & 0x000c) {
  640. case 1 << 2:
  641. LOG_DEBUG("main area readed with 1 (correctable) error");
  642. break;
  643. case 2 << 2:
  644. LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
  645. return ERROR_NAND_OPERATION_FAILED;
  646. break;
  647. }
  648. switch (ecc_status & 0x0003) {
  649. case 1:
  650. LOG_DEBUG("spare area readed with 1 (correctable) error");
  651. break;
  652. case 2:
  653. LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
  654. return ERROR_NAND_OPERATION_FAILED;
  655. break;
  656. }
  657. }
  658. break;
  659. case MX3_NF_FIN_NONE:
  660. break;
  661. }
  662. return ERROR_OK;
  663. }
  664. struct nand_flash_controller imx31_nand_flash_controller = {
  665. .name = "imx31",
  666. .usage = "nand device imx31 target noecc|hwecc",
  667. .nand_device_command = &imx31_nand_device_command,
  668. .init = &imx31_init,
  669. .reset = &imx31_reset,
  670. .command = &imx31_command,
  671. .address = &imx31_address,
  672. .write_data = &imx31_write_data,
  673. .read_data = &imx31_read_data,
  674. .write_page = &imx31_write_page,
  675. .read_page = &imx31_read_page,
  676. .nand_ready = &imx31_nand_ready,
  677. };