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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Alexei Babich *
  3. * Rezonans plc., Chelyabinsk, Russia *
  4. * impatt@mail.ru *
  5. * *
  6. * Copyright (C) 2010 by Gaetan CARLIER *
  7. * Trump s.a., Belgium *
  8. * *
  9. * Copyright (C) 2011 by Erik Ahlen *
  10. * Avalon Innovation, Sweden *
  11. * *
  12. * This program is free software; you can redistribute it and/or modify *
  13. * it under the terms of the GNU General Public License as published by *
  14. * the Free Software Foundation; either version 2 of the License, or *
  15. * (at your option) any later version. *
  16. * *
  17. * This program is distributed in the hope that it will be useful, *
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  20. * GNU General Public License for more details. *
  21. * *
  22. * You should have received a copy of the GNU General Public License *
  23. * along with this program; if not, write to the *
  24. * Free Software Foundation, Inc., *
  25. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  26. ***************************************************************************/
  27. /*
  28. * Freescale iMX OpenOCD NAND Flash controller support.
  29. * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  30. */
  31. /*
  32. * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  33. * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  34. * "nand write # file 0", "nand verify"
  35. *
  36. * get_next_halfword_from_sram_buffer() not tested
  37. * !! all function only tested with 2k page nand device; mxc_write_page
  38. * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  39. * !! oob must be be used due to NFS bug
  40. * !! oob must be 64 bytes per 2KiB page
  41. */
  42. #ifdef HAVE_CONFIG_H
  43. #include "config.h"
  44. #endif
  45. #include "imp.h"
  46. #include "mxc.h"
  47. #include <target/target.h>
  48. #define OOB_SIZE 64
  49. #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
  50. mxc_nf_info->mxc_version == MXC_VERSION_MX31)
  51. #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
  52. mxc_nf_info->mxc_version == MXC_VERSION_MX35)
  53. /* This permits to print (in LOG_INFO) how much bytes
  54. * has been written after a page read or write.
  55. * This is useful when OpenOCD is used with a graphical
  56. * front-end to estimate progression of the global read/write
  57. */
  58. #undef _MXC_PRINT_STAT
  59. /* #define _MXC_PRINT_STAT */
  60. static const char target_not_halted_err_msg[] =
  61. "target must be halted to use mxc NAND flash controller";
  62. static const char data_block_size_err_msg[] =
  63. "minimal granularity is one half-word, %" PRId32 " is incorrect";
  64. static const char sram_buffer_bounds_err_msg[] =
  65. "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  66. static const char get_status_register_err_msg[] = "can't get NAND status";
  67. static uint32_t in_sram_address;
  68. static unsigned char sign_of_sequental_byte_read;
  69. static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
  70. static int initialize_nf_controller(struct nand_device *nand);
  71. static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  72. static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  73. static int poll_for_complete_op(struct nand_device *nand, const char *text);
  74. static int validate_target_state(struct nand_device *nand);
  75. static int do_data_output(struct nand_device *nand);
  76. static int mxc_command(struct nand_device *nand, uint8_t command);
  77. static int mxc_address(struct nand_device *nand, uint8_t address);
  78. NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  79. {
  80. struct mxc_nf_controller *mxc_nf_info;
  81. int hwecc_needed;
  82. int x;
  83. mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  84. if (mxc_nf_info == NULL) {
  85. LOG_ERROR("no memory for nand controller");
  86. return ERROR_FAIL;
  87. }
  88. nand->controller_priv = mxc_nf_info;
  89. if (CMD_ARGC < 4) {
  90. LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
  91. return ERROR_FAIL;
  92. }
  93. /*
  94. * check board type
  95. */
  96. if (strcmp(CMD_ARGV[2], "mx25") == 0) {
  97. mxc_nf_info->mxc_version = MXC_VERSION_MX25;
  98. mxc_nf_info->mxc_base_addr = 0xBB000000;
  99. mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
  100. } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
  101. mxc_nf_info->mxc_version = MXC_VERSION_MX27;
  102. mxc_nf_info->mxc_base_addr = 0xD8000000;
  103. mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
  104. } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
  105. mxc_nf_info->mxc_version = MXC_VERSION_MX31;
  106. mxc_nf_info->mxc_base_addr = 0xB8000000;
  107. mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
  108. } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
  109. mxc_nf_info->mxc_version = MXC_VERSION_MX35;
  110. mxc_nf_info->mxc_base_addr = 0xBB000000;
  111. mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
  112. }
  113. /*
  114. * check hwecc requirements
  115. */
  116. hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
  117. if (hwecc_needed == 0)
  118. mxc_nf_info->flags.hw_ecc_enabled = 1;
  119. else
  120. mxc_nf_info->flags.hw_ecc_enabled = 0;
  121. mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
  122. mxc_nf_info->fin = MXC_NF_FIN_NONE;
  123. mxc_nf_info->flags.target_little_endian =
  124. (nand->target->endianness == TARGET_LITTLE_ENDIAN);
  125. /*
  126. * should factory bad block indicator be swaped
  127. * as a workaround for how the nfc handles pages.
  128. */
  129. if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
  130. LOG_DEBUG("BI-swap enabled");
  131. mxc_nf_info->flags.biswap_enabled = 1;
  132. }
  133. /*
  134. * testing host endianness
  135. */
  136. x = 1;
  137. if (*(char *) &x == 1)
  138. mxc_nf_info->flags.host_little_endian = 1;
  139. else
  140. mxc_nf_info->flags.host_little_endian = 0;
  141. return ERROR_OK;
  142. }
  143. COMMAND_HANDLER(handle_mxc_biswap_command)
  144. {
  145. struct nand_device *nand = NULL;
  146. struct mxc_nf_controller *mxc_nf_info = NULL;
  147. if (CMD_ARGC < 1 || CMD_ARGC > 2)
  148. return ERROR_COMMAND_SYNTAX_ERROR;
  149. int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
  150. if (retval != ERROR_OK) {
  151. command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
  152. return ERROR_COMMAND_ARGUMENT_INVALID;
  153. }
  154. mxc_nf_info = nand->controller_priv;
  155. if (CMD_ARGC == 2) {
  156. if (strcmp(CMD_ARGV[1], "enable") == 0)
  157. mxc_nf_info->flags.biswap_enabled = true;
  158. else
  159. mxc_nf_info->flags.biswap_enabled = false;
  160. }
  161. if (mxc_nf_info->flags.biswap_enabled)
  162. command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
  163. else
  164. command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
  165. return ERROR_OK;
  166. }
  167. static const struct command_registration mxc_sub_command_handlers[] = {
  168. {
  169. .name = "biswap",
  170. .handler = handle_mxc_biswap_command,
  171. .help = "Turns on/off bad block information swaping from main area, "
  172. "without parameter query status.",
  173. .usage = "bank_id ['enable'|'disable']",
  174. },
  175. COMMAND_REGISTRATION_DONE
  176. };
  177. static const struct command_registration mxc_nand_command_handler[] = {
  178. {
  179. .name = "mxc",
  180. .mode = COMMAND_ANY,
  181. .help = "MXC NAND flash controller commands",
  182. .chain = mxc_sub_command_handlers
  183. },
  184. COMMAND_REGISTRATION_DONE
  185. };
  186. static int mxc_init(struct nand_device *nand)
  187. {
  188. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  189. struct target *target = nand->target;
  190. int validate_target_result;
  191. uint16_t buffsize_register_content;
  192. uint32_t sreg_content;
  193. uint32_t SREG = MX2_FMCR;
  194. uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
  195. uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
  196. int retval;
  197. uint16_t nand_status_content;
  198. /*
  199. * validate target state
  200. */
  201. validate_target_result = validate_target_state(nand);
  202. if (validate_target_result != ERROR_OK)
  203. return validate_target_result;
  204. if (nfc_is_v1()) {
  205. target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
  206. mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
  207. } else
  208. mxc_nf_info->flags.one_kb_sram = 0;
  209. if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
  210. SREG = MX3_PCSR;
  211. SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
  212. SEL_FMS = MX3_PCSR_NF_FMS;
  213. } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
  214. SREG = MX25_RCSR;
  215. SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
  216. SEL_FMS = MX25_RCSR_NF_FMS;
  217. } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
  218. SREG = MX35_RCSR;
  219. SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
  220. SEL_FMS = MX35_RCSR_NF_FMS;
  221. }
  222. target_read_u32(target, SREG, &sreg_content);
  223. if (!nand->bus_width) {
  224. /* bus_width not yet defined. Read it from MXC_FMCR */
  225. nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
  226. } else {
  227. /* bus_width forced in soft. Sync it to MXC_FMCR */
  228. sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
  229. target_write_u32(target, SREG, sreg_content);
  230. }
  231. if (nand->bus_width == 16)
  232. LOG_DEBUG("MXC_NF : bus is 16-bit width");
  233. else
  234. LOG_DEBUG("MXC_NF : bus is 8-bit width");
  235. if (!nand->page_size)
  236. nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
  237. else {
  238. sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
  239. target_write_u32(target, SREG, sreg_content);
  240. }
  241. if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
  242. LOG_ERROR("NAND controller have only 1 kb SRAM, so "
  243. "pagesize 2048 is incompatible with it");
  244. } else
  245. LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
  246. if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
  247. LOG_ERROR("MXC driver does not have support for 4k pagesize.");
  248. initialize_nf_controller(nand);
  249. retval = ERROR_OK;
  250. retval |= mxc_command(nand, NAND_CMD_STATUS);
  251. retval |= mxc_address(nand, 0x00);
  252. retval |= do_data_output(nand);
  253. if (retval != ERROR_OK) {
  254. LOG_ERROR(get_status_register_err_msg);
  255. return ERROR_FAIL;
  256. }
  257. target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
  258. if (!(nand_status_content & 0x0080)) {
  259. LOG_INFO("NAND read-only");
  260. mxc_nf_info->flags.nand_readonly = 1;
  261. } else
  262. mxc_nf_info->flags.nand_readonly = 0;
  263. return ERROR_OK;
  264. }
  265. static int mxc_read_data(struct nand_device *nand, void *data)
  266. {
  267. int validate_target_result;
  268. int try_data_output_from_nand_chip;
  269. /*
  270. * validate target state
  271. */
  272. validate_target_result = validate_target_state(nand);
  273. if (validate_target_result != ERROR_OK)
  274. return validate_target_result;
  275. /*
  276. * get data from nand chip
  277. */
  278. try_data_output_from_nand_chip = do_data_output(nand);
  279. if (try_data_output_from_nand_chip != ERROR_OK) {
  280. LOG_ERROR("mxc_read_data : read data failed : '%x'",
  281. try_data_output_from_nand_chip);
  282. return try_data_output_from_nand_chip;
  283. }
  284. if (nand->bus_width == 16)
  285. get_next_halfword_from_sram_buffer(nand, data);
  286. else
  287. get_next_byte_from_sram_buffer(nand, data);
  288. return ERROR_OK;
  289. }
  290. static int mxc_write_data(struct nand_device *nand, uint16_t data)
  291. {
  292. LOG_ERROR("write_data() not implemented");
  293. return ERROR_NAND_OPERATION_FAILED;
  294. }
  295. static int mxc_reset(struct nand_device *nand)
  296. {
  297. /*
  298. * validate target state
  299. */
  300. int validate_target_result;
  301. validate_target_result = validate_target_state(nand);
  302. if (validate_target_result != ERROR_OK)
  303. return validate_target_result;
  304. initialize_nf_controller(nand);
  305. return ERROR_OK;
  306. }
  307. static int mxc_command(struct nand_device *nand, uint8_t command)
  308. {
  309. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  310. struct target *target = nand->target;
  311. int validate_target_result;
  312. int poll_result;
  313. /*
  314. * validate target state
  315. */
  316. validate_target_result = validate_target_state(nand);
  317. if (validate_target_result != ERROR_OK)
  318. return validate_target_result;
  319. switch (command) {
  320. case NAND_CMD_READOOB:
  321. command = NAND_CMD_READ0;
  322. /* set read point for data_read() and read_block_data() to
  323. * spare area in SRAM buffer
  324. */
  325. if (nfc_is_v1())
  326. in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
  327. else
  328. in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
  329. break;
  330. case NAND_CMD_READ1:
  331. command = NAND_CMD_READ0;
  332. /*
  333. * offset == one half of page size
  334. */
  335. in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
  336. break;
  337. default:
  338. in_sram_address = MXC_NF_MAIN_BUFFER0;
  339. break;
  340. }
  341. target_write_u16(target, MXC_NF_FCMD, command);
  342. /*
  343. * start command input operation (set MXC_NF_BIT_OP_DONE==0)
  344. */
  345. target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
  346. poll_result = poll_for_complete_op(nand, "command");
  347. if (poll_result != ERROR_OK)
  348. return poll_result;
  349. /*
  350. * reset cursor to begin of the buffer
  351. */
  352. sign_of_sequental_byte_read = 0;
  353. /* Handle special read command and adjust NF_CFG2(FDO) */
  354. switch (command) {
  355. case NAND_CMD_READID:
  356. mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
  357. mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
  358. break;
  359. case NAND_CMD_STATUS:
  360. mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
  361. mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
  362. target_write_u16 (target, MXC_NF_BUFADDR, 0);
  363. in_sram_address = 0;
  364. break;
  365. case NAND_CMD_READ0:
  366. mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
  367. mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
  368. break;
  369. default:
  370. /* Ohter command use the default 'One page data out' FDO */
  371. mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
  372. break;
  373. }
  374. return ERROR_OK;
  375. }
  376. static int mxc_address(struct nand_device *nand, uint8_t address)
  377. {
  378. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  379. struct target *target = nand->target;
  380. int validate_target_result;
  381. int poll_result;
  382. /*
  383. * validate target state
  384. */
  385. validate_target_result = validate_target_state(nand);
  386. if (validate_target_result != ERROR_OK)
  387. return validate_target_result;
  388. target_write_u16(target, MXC_NF_FADDR, address);
  389. /*
  390. * start address input operation (set MXC_NF_BIT_OP_DONE==0)
  391. */
  392. target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
  393. poll_result = poll_for_complete_op(nand, "address");
  394. if (poll_result != ERROR_OK)
  395. return poll_result;
  396. return ERROR_OK;
  397. }
  398. static int mxc_nand_ready(struct nand_device *nand, int tout)
  399. {
  400. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  401. struct target *target = nand->target;
  402. uint16_t poll_complete_status;
  403. int validate_target_result;
  404. /*
  405. * validate target state
  406. */
  407. validate_target_result = validate_target_state(nand);
  408. if (validate_target_result != ERROR_OK)
  409. return validate_target_result;
  410. do {
  411. target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
  412. if (poll_complete_status & MXC_NF_BIT_OP_DONE)
  413. return tout;
  414. alive_sleep(1);
  415. } while (tout-- > 0);
  416. return tout;
  417. }
  418. static int mxc_write_page(struct nand_device *nand, uint32_t page,
  419. uint8_t *data, uint32_t data_size,
  420. uint8_t *oob, uint32_t oob_size)
  421. {
  422. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  423. struct target *target = nand->target;
  424. int retval;
  425. uint16_t nand_status_content;
  426. uint16_t swap1, swap2, new_swap1;
  427. uint8_t bufs;
  428. int poll_result;
  429. if (data_size % 2) {
  430. LOG_ERROR(data_block_size_err_msg, data_size);
  431. return ERROR_NAND_OPERATION_FAILED;
  432. }
  433. if (oob_size % 2) {
  434. LOG_ERROR(data_block_size_err_msg, oob_size);
  435. return ERROR_NAND_OPERATION_FAILED;
  436. }
  437. if (!data) {
  438. LOG_ERROR("nothing to program");
  439. return ERROR_NAND_OPERATION_FAILED;
  440. }
  441. /*
  442. * validate target state
  443. */
  444. retval = validate_target_state(nand);
  445. if (retval != ERROR_OK)
  446. return retval;
  447. in_sram_address = MXC_NF_MAIN_BUFFER0;
  448. sign_of_sequental_byte_read = 0;
  449. retval = ERROR_OK;
  450. retval |= mxc_command(nand, NAND_CMD_SEQIN);
  451. retval |= mxc_address(nand, 0); /* col */
  452. retval |= mxc_address(nand, 0); /* col */
  453. retval |= mxc_address(nand, page & 0xff); /* page address */
  454. retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
  455. retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
  456. target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
  457. if (oob) {
  458. if (mxc_nf_info->flags.hw_ecc_enabled) {
  459. /*
  460. * part of spare block will be overrided by hardware
  461. * ECC generator
  462. */
  463. LOG_DEBUG("part of spare block will be overrided "
  464. "by hardware ECC generator");
  465. }
  466. if (nfc_is_v1())
  467. target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
  468. else {
  469. uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
  470. while (oob_size > 0) {
  471. uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
  472. target_write_buffer(target, addr, len, oob);
  473. addr = align_address_v2(nand, addr + len);
  474. oob += len;
  475. oob_size -= len;
  476. }
  477. }
  478. }
  479. if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
  480. /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
  481. target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
  482. if (oob) {
  483. LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
  484. return ERROR_NAND_OPERATION_FAILED;
  485. }
  486. swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
  487. new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
  488. swap2 = (swap1 << 8) | (swap2 & 0xFF);
  489. target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
  490. if (nfc_is_v1())
  491. target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3, swap2);
  492. else
  493. target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
  494. }
  495. /*
  496. * start data input operation (set MXC_NF_BIT_OP_DONE==0)
  497. */
  498. if (nfc_is_v1() && nand->page_size > 512)
  499. bufs = 4;
  500. else
  501. bufs = 1;
  502. for (uint8_t i = 0; i < bufs; ++i) {
  503. target_write_u16(target, MXC_NF_BUFADDR, i);
  504. target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
  505. poll_result = poll_for_complete_op(nand, "data input");
  506. if (poll_result != ERROR_OK)
  507. return poll_result;
  508. }
  509. retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
  510. if (retval != ERROR_OK)
  511. return retval;
  512. /*
  513. * check status register
  514. */
  515. retval = ERROR_OK;
  516. retval |= mxc_command(nand, NAND_CMD_STATUS);
  517. target_write_u16 (target, MXC_NF_BUFADDR, 0);
  518. mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
  519. mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
  520. retval |= do_data_output(nand);
  521. if (retval != ERROR_OK) {
  522. LOG_ERROR(get_status_register_err_msg);
  523. return retval;
  524. }
  525. target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
  526. if (nand_status_content & 0x0001) {
  527. /*
  528. * page not correctly written
  529. */
  530. return ERROR_NAND_OPERATION_FAILED;
  531. }
  532. #ifdef _MXC_PRINT_STAT
  533. LOG_INFO("%d bytes newly written", data_size);
  534. #endif
  535. return ERROR_OK;
  536. }
  537. static int mxc_read_page(struct nand_device *nand, uint32_t page,
  538. uint8_t *data, uint32_t data_size,
  539. uint8_t *oob, uint32_t oob_size)
  540. {
  541. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  542. struct target *target = nand->target;
  543. int retval;
  544. uint8_t bufs;
  545. uint16_t swap1, swap2, new_swap1;
  546. if (data_size % 2) {
  547. LOG_ERROR(data_block_size_err_msg, data_size);
  548. return ERROR_NAND_OPERATION_FAILED;
  549. }
  550. if (oob_size % 2) {
  551. LOG_ERROR(data_block_size_err_msg, oob_size);
  552. return ERROR_NAND_OPERATION_FAILED;
  553. }
  554. /*
  555. * validate target state
  556. */
  557. retval = validate_target_state(nand);
  558. if (retval != ERROR_OK)
  559. return retval;
  560. /* Reset address_cycles before mxc_command ?? */
  561. retval = mxc_command(nand, NAND_CMD_READ0);
  562. if (retval != ERROR_OK)
  563. return retval;
  564. retval = mxc_address(nand, 0); /* col */
  565. if (retval != ERROR_OK)
  566. return retval;
  567. retval = mxc_address(nand, 0); /* col */
  568. if (retval != ERROR_OK)
  569. return retval;
  570. retval = mxc_address(nand, page & 0xff);/* page address */
  571. if (retval != ERROR_OK)
  572. return retval;
  573. retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
  574. if (retval != ERROR_OK)
  575. return retval;
  576. retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
  577. if (retval != ERROR_OK)
  578. return retval;
  579. retval = mxc_command(nand, NAND_CMD_READSTART);
  580. if (retval != ERROR_OK)
  581. return retval;
  582. if (nfc_is_v1() && nand->page_size > 512)
  583. bufs = 4;
  584. else
  585. bufs = 1;
  586. for (uint8_t i = 0; i < bufs; ++i) {
  587. target_write_u16(target, MXC_NF_BUFADDR, i);
  588. mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
  589. retval = do_data_output(nand);
  590. if (retval != ERROR_OK) {
  591. LOG_ERROR("MXC_NF : Error reading page %d", i);
  592. return retval;
  593. }
  594. }
  595. if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
  596. uint32_t SPARE_BUFFER3;
  597. /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
  598. target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
  599. if (nfc_is_v1())
  600. SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3;
  601. else
  602. SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
  603. target_read_u16(target, SPARE_BUFFER3, &swap2);
  604. new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
  605. swap2 = (swap1 << 8) | (swap2 & 0xFF);
  606. target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
  607. target_write_u16(target, SPARE_BUFFER3, swap2);
  608. }
  609. if (data)
  610. target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
  611. if (oob) {
  612. if (nfc_is_v1())
  613. target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
  614. else {
  615. uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
  616. while (oob_size > 0) {
  617. uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
  618. target_read_buffer(target, addr, len, oob);
  619. addr = align_address_v2(nand, addr + len);
  620. oob += len;
  621. oob_size -= len;
  622. }
  623. }
  624. }
  625. #ifdef _MXC_PRINT_STAT
  626. if (data_size > 0) {
  627. /* When Operation Status is read (when page is erased),
  628. * this function is used but data_size is null.
  629. */
  630. LOG_INFO("%d bytes newly read", data_size);
  631. }
  632. #endif
  633. return ERROR_OK;
  634. }
  635. static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
  636. {
  637. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  638. uint32_t ret = addr;
  639. if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
  640. (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
  641. ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
  642. else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
  643. ret = MXC_NF_V2_SPARE_BUFFER0;
  644. return ret;
  645. }
  646. static int initialize_nf_controller(struct nand_device *nand)
  647. {
  648. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  649. struct target *target = nand->target;
  650. uint16_t work_mode = 0;
  651. uint16_t temp;
  652. /*
  653. * resets NAND flash controller in zero time ? I dont know.
  654. */
  655. target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
  656. if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
  657. work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
  658. if (target->endianness == TARGET_BIG_ENDIAN) {
  659. LOG_DEBUG("MXC_NF : work in Big Endian mode");
  660. work_mode |= MXC_NF_BIT_BE_EN;
  661. } else
  662. LOG_DEBUG("MXC_NF : work in Little Endian mode");
  663. if (mxc_nf_info->flags.hw_ecc_enabled) {
  664. LOG_DEBUG("MXC_NF : work with ECC mode");
  665. work_mode |= MXC_NF_BIT_ECC_EN;
  666. } else
  667. LOG_DEBUG("MXC_NF : work without ECC mode");
  668. if (nfc_is_v2()) {
  669. target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
  670. if (nand->page_size) {
  671. uint16_t pages_per_block = nand->erase_size / nand->page_size;
  672. work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
  673. }
  674. work_mode |= MXC_NF_BIT_ECC_4BIT;
  675. }
  676. target_write_u16(target, MXC_NF_CFG1, work_mode);
  677. /*
  678. * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
  679. */
  680. target_write_u16(target, MXC_NF_BUFCFG, 2);
  681. target_read_u16(target, MXC_NF_FWP, &temp);
  682. if ((temp & 0x0007) == 1) {
  683. LOG_ERROR("NAND flash is tight-locked, reset needed");
  684. return ERROR_FAIL;
  685. }
  686. /*
  687. * unlock NAND flash for write
  688. */
  689. if (nfc_is_v1()) {
  690. target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
  691. target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
  692. } else {
  693. target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
  694. target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
  695. target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
  696. target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
  697. target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
  698. target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
  699. target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
  700. target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
  701. }
  702. target_write_u16(target, MXC_NF_FWP, 4);
  703. /*
  704. * 0x0000 means that first SRAM buffer @base_addr will be used
  705. */
  706. target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
  707. /*
  708. * address of SRAM buffer
  709. */
  710. in_sram_address = MXC_NF_MAIN_BUFFER0;
  711. sign_of_sequental_byte_read = 0;
  712. return ERROR_OK;
  713. }
  714. static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
  715. {
  716. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  717. struct target *target = nand->target;
  718. static uint8_t even_byte;
  719. uint16_t temp;
  720. /*
  721. * host-big_endian ??
  722. */
  723. if (sign_of_sequental_byte_read == 0)
  724. even_byte = 0;
  725. if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
  726. LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
  727. *value = 0;
  728. sign_of_sequental_byte_read = 0;
  729. even_byte = 0;
  730. return ERROR_NAND_OPERATION_FAILED;
  731. } else {
  732. if (nfc_is_v2())
  733. in_sram_address = align_address_v2(nand, in_sram_address);
  734. target_read_u16(target, in_sram_address, &temp);
  735. if (even_byte) {
  736. *value = temp >> 8;
  737. even_byte = 0;
  738. in_sram_address += 2;
  739. } else {
  740. *value = temp & 0xff;
  741. even_byte = 1;
  742. }
  743. }
  744. sign_of_sequental_byte_read = 1;
  745. return ERROR_OK;
  746. }
  747. static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
  748. {
  749. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  750. struct target *target = nand->target;
  751. if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
  752. LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
  753. *value = 0;
  754. return ERROR_NAND_OPERATION_FAILED;
  755. } else {
  756. if (nfc_is_v2())
  757. in_sram_address = align_address_v2(nand, in_sram_address);
  758. target_read_u16(target, in_sram_address, value);
  759. in_sram_address += 2;
  760. }
  761. return ERROR_OK;
  762. }
  763. static int poll_for_complete_op(struct nand_device *nand, const char *text)
  764. {
  765. if (mxc_nand_ready(nand, 1000) == -1) {
  766. LOG_ERROR("%s sending timeout", text);
  767. return ERROR_NAND_OPERATION_FAILED;
  768. }
  769. return ERROR_OK;
  770. }
  771. static int validate_target_state(struct nand_device *nand)
  772. {
  773. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  774. struct target *target = nand->target;
  775. if (target->state != TARGET_HALTED) {
  776. LOG_ERROR(target_not_halted_err_msg);
  777. return ERROR_NAND_OPERATION_FAILED;
  778. }
  779. if (mxc_nf_info->flags.target_little_endian !=
  780. (target->endianness == TARGET_LITTLE_ENDIAN)) {
  781. /*
  782. * endianness changed after NAND controller probed
  783. */
  784. return ERROR_NAND_OPERATION_FAILED;
  785. }
  786. return ERROR_OK;
  787. }
  788. int ecc_status_v1(struct nand_device *nand)
  789. {
  790. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  791. struct target *target = nand->target;
  792. uint16_t ecc_status;
  793. target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
  794. switch (ecc_status & 0x000c) {
  795. case 1 << 2:
  796. LOG_INFO("main area read with 1 (correctable) error");
  797. break;
  798. case 2 << 2:
  799. LOG_INFO("main area read with more than 1 (incorrectable) error");
  800. return ERROR_NAND_OPERATION_FAILED;
  801. break;
  802. }
  803. switch (ecc_status & 0x0003) {
  804. case 1:
  805. LOG_INFO("spare area read with 1 (correctable) error");
  806. break;
  807. case 2:
  808. LOG_INFO("main area read with more than 1 (incorrectable) error");
  809. return ERROR_NAND_OPERATION_FAILED;
  810. break;
  811. }
  812. return ERROR_OK;
  813. }
  814. int ecc_status_v2(struct nand_device *nand)
  815. {
  816. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  817. struct target *target = nand->target;
  818. uint16_t ecc_status;
  819. uint8_t no_subpages;
  820. uint8_t err;
  821. no_subpages = nand->page_size >> 9;
  822. target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
  823. do {
  824. err = ecc_status & 0xF;
  825. if (err > 4) {
  826. LOG_INFO("UnCorrectable RS-ECC Error");
  827. return ERROR_NAND_OPERATION_FAILED;
  828. } else if (err > 0)
  829. LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
  830. ecc_status >>= 4;
  831. } while (--no_subpages);
  832. return ERROR_OK;
  833. }
  834. static int do_data_output(struct nand_device *nand)
  835. {
  836. struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
  837. struct target *target = nand->target;
  838. int poll_result;
  839. switch (mxc_nf_info->fin) {
  840. case MXC_NF_FIN_DATAOUT:
  841. /*
  842. * start data output operation (set MXC_NF_BIT_OP_DONE==0)
  843. */
  844. target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
  845. poll_result = poll_for_complete_op(nand, "data output");
  846. if (poll_result != ERROR_OK)
  847. return poll_result;
  848. mxc_nf_info->fin = MXC_NF_FIN_NONE;
  849. /*
  850. * ECC stuff
  851. */
  852. if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
  853. int ecc_status;
  854. if (nfc_is_v1())
  855. ecc_status = ecc_status_v1(nand);
  856. else
  857. ecc_status = ecc_status_v2(nand);
  858. if (ecc_status != ERROR_OK)
  859. return ecc_status;
  860. }
  861. break;
  862. case MXC_NF_FIN_NONE:
  863. break;
  864. }
  865. return ERROR_OK;
  866. }
  867. struct nand_flash_controller mxc_nand_flash_controller = {
  868. .name = "mxc",
  869. .nand_device_command = &mxc_nand_device_command,
  870. .commands = mxc_nand_command_handler,
  871. .init = &mxc_init,
  872. .reset = &mxc_reset,
  873. .command = &mxc_command,
  874. .address = &mxc_address,
  875. .write_data = &mxc_write_data,
  876. .read_data = &mxc_read_data,
  877. .write_page = &mxc_write_page,
  878. .read_page = &mxc_read_page,
  879. .nand_ready = &mxc_nand_ready,
  880. };