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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Alexei Babich *
  3. * Rezonans plc., Chelyabinsk, Russia *
  4. * impatt@mail.ru *
  5. * *
  6. * Copyright (C) 2011 by Erik Ahlen *
  7. * Avalon Innovation, Sweden *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  23. ***************************************************************************/
  24. /*
  25. * Freescale iMX OpenOCD NAND Flash controller support.
  26. * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  27. *
  28. * Many thanks to Ben Dooks for writing s3c24xx driver.
  29. */
  30. #define MXC_NF_BUFSIZ (mxc_nf_info->mxc_regs_addr + 0x00)
  31. #define MXC_NF_BUFADDR (mxc_nf_info->mxc_regs_addr + 0x04)
  32. #define MXC_NF_FADDR (mxc_nf_info->mxc_regs_addr + 0x06)
  33. #define MXC_NF_FCMD (mxc_nf_info->mxc_regs_addr + 0x08)
  34. #define MXC_NF_BUFCFG (mxc_nf_info->mxc_regs_addr + 0x0a)
  35. #define MXC_NF_ECCSTATUS (mxc_nf_info->mxc_regs_addr + 0x0c)
  36. #define MXC_NF_ECCMAINPOS (mxc_nf_info->mxc_regs_addr + 0x0e)
  37. #define MXC_NF_V1_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
  38. #define MXC_NF_V2_SPAS (mxc_nf_info->mxc_regs_addr + 0x10)
  39. #define MXC_NF_FWP (mxc_nf_info->mxc_regs_addr + 0x12)
  40. #define MXC_NF_V1_UNLOCKSTART (mxc_nf_info->mxc_regs_addr + 0x14)
  41. #define MXC_NF_V1_UNLOCKEND (mxc_nf_info->mxc_regs_addr + 0x16)
  42. #define MXC_NF_V2_UNLOCKSTART0 (mxc_nf_info->mxc_regs_addr + 0x20)
  43. #define MXC_NF_V2_UNLOCKSTART1 (mxc_nf_info->mxc_regs_addr + 0x24)
  44. #define MXC_NF_V2_UNLOCKSTART2 (mxc_nf_info->mxc_regs_addr + 0x28)
  45. #define MXC_NF_V2_UNLOCKSTART3 (mxc_nf_info->mxc_regs_addr + 0x2c)
  46. #define MXC_NF_V2_UNLOCKEND0 (mxc_nf_info->mxc_regs_addr + 0x22)
  47. #define MXC_NF_V2_UNLOCKEND1 (mxc_nf_info->mxc_regs_addr + 0x26)
  48. #define MXC_NF_V2_UNLOCKEND2 (mxc_nf_info->mxc_regs_addr + 0x2a)
  49. #define MXC_NF_V2_UNLOCKEND3 (mxc_nf_info->mxc_regs_addr + 0x2e)
  50. #define MXC_NF_FWPSTATUS (mxc_nf_info->mxc_regs_addr + 0x18)
  51. /*
  52. * all bits not marked as self-clearing bit
  53. */
  54. #define MXC_NF_CFG1 (mxc_nf_info->mxc_regs_addr + 0x1a)
  55. #define MXC_NF_CFG2 (mxc_nf_info->mxc_regs_addr + 0x1c)
  56. #define MXC_NF_MAIN_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0000)
  57. #define MXC_NF_MAIN_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0200)
  58. #define MXC_NF_MAIN_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0400)
  59. #define MXC_NF_MAIN_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0600)
  60. #define MXC_NF_V1_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0800)
  61. #define MXC_NF_V1_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0810)
  62. #define MXC_NF_V1_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0820)
  63. #define MXC_NF_V1_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0830)
  64. #define MXC_NF_V2_MAIN_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x0800)
  65. #define MXC_NF_V2_MAIN_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x0a00)
  66. #define MXC_NF_V2_MAIN_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x0c00)
  67. #define MXC_NF_V2_MAIN_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x0e00)
  68. #define MXC_NF_V2_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x1000)
  69. #define MXC_NF_V2_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x1040)
  70. #define MXC_NF_V2_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x1080)
  71. #define MXC_NF_V2_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x10c0)
  72. #define MXC_NF_V2_SPARE_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x1100)
  73. #define MXC_NF_V2_SPARE_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x1140)
  74. #define MXC_NF_V2_SPARE_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x1180)
  75. #define MXC_NF_V2_SPARE_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x11c0)
  76. #define MXC_NF_MAIN_BUFFER_LEN 512
  77. #define MXC_NF_SPARE_BUFFER_LEN 16
  78. #define MXC_NF_SPARE_BUFFER_MAX 64
  79. #define MXC_NF_V1_LAST_BUFFADDR ((MXC_NF_V1_SPARE_BUFFER3) + \
  80. MXC_NF_SPARE_BUFFER_LEN - 2)
  81. #define MXC_NF_V2_LAST_BUFFADDR ((MXC_NF_V2_SPARE_BUFFER7) + \
  82. MXC_NF_SPARE_BUFFER_LEN - 2)
  83. /* bits in MXC_NF_CFG1 register */
  84. #define MXC_NF_BIT_ECC_4BIT (1<<0)
  85. #define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
  86. #define MXC_NF_BIT_ECC_EN (1<<3)
  87. #define MXC_NF_BIT_INT_DIS (1<<4)
  88. #define MXC_NF_BIT_BE_EN (1<<5)
  89. #define MXC_NF_BIT_RESET_EN (1<<6)
  90. #define MXC_NF_BIT_FORCE_CE (1<<7)
  91. #define MXC_NF_V2_CFG1_PPB(x) (((x) & 0x3) << 9)
  92. /* bits in MXC_NF_CFG2 register */
  93. /*Flash Command Input*/
  94. #define MXC_NF_BIT_OP_FCI (1<<0)
  95. /*
  96. * Flash Address Input
  97. */
  98. #define MXC_NF_BIT_OP_FAI (1<<1)
  99. /*
  100. * Flash Data Input
  101. */
  102. #define MXC_NF_BIT_OP_FDI (1<<2)
  103. /* see "enum mx_dataout_type" below */
  104. #define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
  105. #define MXC_NF_BIT_OP_DONE (1<<15)
  106. #define MXC_CCM_CGR2 0x53f80028
  107. #define MXC_GPR 0x43fac008
  108. #define MX2_FMCR 0x10027814
  109. #define MX2_FMCR_NF_16BIT_SEL (1<<4)
  110. #define MX2_FMCR_NF_FMS (1<<5)
  111. #define MX25_RCSR 0x53f80018
  112. #define MX25_RCSR_NF_16BIT_SEL (1<<14)
  113. #define MX25_RCSR_NF_FMS (1<<8)
  114. #define MX25_RCSR_NF_4K (1<<9)
  115. #define MX3_PCSR 0x53f8000c
  116. #define MX3_PCSR_NF_16BIT_SEL (1<<31)
  117. #define MX3_PCSR_NF_FMS (1<<30)
  118. #define MX35_RCSR 0x53f80018
  119. #define MX35_RCSR_NF_16BIT_SEL (1<<14)
  120. #define MX35_RCSR_NF_FMS (1<<8)
  121. #define MX35_RCSR_NF_4K (1<<9)
  122. enum mxc_version {
  123. MXC_VERSION_UKWN = 0,
  124. MXC_VERSION_MX25 = 1,
  125. MXC_VERSION_MX27 = 2,
  126. MXC_VERSION_MX31 = 3,
  127. MXC_VERSION_MX35 = 4
  128. };
  129. enum mxc_dataout_type {
  130. MXC_NF_DATAOUT_PAGE = 1,
  131. MXC_NF_DATAOUT_NANDID = 2,
  132. MXC_NF_DATAOUT_NANDSTATUS = 4,
  133. };
  134. enum mxc_nf_finalize_action {
  135. MXC_NF_FIN_NONE,
  136. MXC_NF_FIN_DATAOUT,
  137. };
  138. struct mxc_nf_flags {
  139. unsigned host_little_endian:1;
  140. unsigned target_little_endian:1;
  141. unsigned nand_readonly:1;
  142. unsigned one_kb_sram:1;
  143. unsigned hw_ecc_enabled:1;
  144. unsigned biswap_enabled:1;
  145. };
  146. struct mxc_nf_controller {
  147. enum mxc_version mxc_version;
  148. uint32_t mxc_base_addr;
  149. uint32_t mxc_regs_addr;
  150. enum mxc_dataout_type optype;
  151. enum mxc_nf_finalize_action fin;
  152. struct mxc_nf_flags flags;
  153. };