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  1. /***************************************************************************
  2. * Copyright (C) 2007, 2008 by Ben Dooks *
  3. * ben@fluff.org *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. /*
  21. * S3C2440 OpenOCD NAND Flash controller support.
  22. *
  23. * Many thanks to Simtec Electronics for sponsoring this work.
  24. */
  25. #ifdef HAVE_CONFIG_H
  26. #include "config.h"
  27. #endif
  28. #include "s3c24xx.h"
  29. NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
  30. {
  31. struct s3c24xx_nand_controller *info;
  32. CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
  33. /* fill in the address fields for the core device */
  34. info->cmd = S3C2440_NFCMD;
  35. info->addr = S3C2440_NFADDR;
  36. info->data = S3C2440_NFDATA;
  37. info->nfstat = S3C2440_NFSTAT;
  38. return ERROR_OK;
  39. }
  40. static int s3c2440_init(struct nand_device *nand)
  41. {
  42. struct target *target = nand->target;
  43. target_write_u32(target, S3C2410_NFCONF,
  44. S3C2440_NFCONF_TACLS(3) |
  45. S3C2440_NFCONF_TWRPH0(7) |
  46. S3C2440_NFCONF_TWRPH1(7));
  47. target_write_u32(target, S3C2440_NFCONT,
  48. S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE);
  49. return ERROR_OK;
  50. }
  51. int s3c2440_nand_ready(struct nand_device *nand, int timeout)
  52. {
  53. struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
  54. struct target *target = nand->target;
  55. uint8_t status;
  56. if (target->state != TARGET_HALTED) {
  57. LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
  58. return ERROR_NAND_OPERATION_FAILED;
  59. }
  60. do {
  61. target_read_u8(target, s3c24xx_info->nfstat, &status);
  62. if (status & S3C2440_NFSTAT_READY)
  63. return 1;
  64. alive_sleep(1);
  65. } while (timeout-- > 0);
  66. return 0;
  67. }
  68. /* use the fact we can read/write 4 bytes in one go via a single 32bit op */
  69. int s3c2440_read_block_data(struct nand_device *nand, uint8_t *data, int data_size)
  70. {
  71. struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
  72. struct target *target = nand->target;
  73. uint32_t nfdata = s3c24xx_info->data;
  74. uint32_t tmp;
  75. LOG_INFO("%s: reading data: %p, %p, %d", __func__, nand, data, data_size);
  76. if (target->state != TARGET_HALTED) {
  77. LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
  78. return ERROR_NAND_OPERATION_FAILED;
  79. }
  80. while (data_size >= 4) {
  81. target_read_u32(target, nfdata, &tmp);
  82. data[0] = tmp;
  83. data[1] = tmp >> 8;
  84. data[2] = tmp >> 16;
  85. data[3] = tmp >> 24;
  86. data_size -= 4;
  87. data += 4;
  88. }
  89. while (data_size > 0) {
  90. target_read_u8(target, nfdata, data);
  91. data_size -= 1;
  92. data += 1;
  93. }
  94. return ERROR_OK;
  95. }
  96. int s3c2440_write_block_data(struct nand_device *nand, uint8_t *data, int data_size)
  97. {
  98. struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
  99. struct target *target = nand->target;
  100. uint32_t nfdata = s3c24xx_info->data;
  101. uint32_t tmp;
  102. if (target->state != TARGET_HALTED) {
  103. LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
  104. return ERROR_NAND_OPERATION_FAILED;
  105. }
  106. while (data_size >= 4) {
  107. tmp = le_to_h_u32(data);
  108. target_write_u32(target, nfdata, tmp);
  109. data_size -= 4;
  110. data += 4;
  111. }
  112. while (data_size > 0) {
  113. target_write_u8(target, nfdata, *data);
  114. data_size -= 1;
  115. data += 1;
  116. }
  117. return ERROR_OK;
  118. }
  119. struct nand_flash_controller s3c2440_nand_controller = {
  120. .name = "s3c2440",
  121. .nand_device_command = &s3c2440_nand_device_command,
  122. .init = &s3c2440_init,
  123. .reset = &s3c24xx_reset,
  124. .command = &s3c24xx_command,
  125. .address = &s3c24xx_address,
  126. .write_data = &s3c24xx_write_data,
  127. .read_data = &s3c24xx_read_data,
  128. .write_page = s3c24xx_write_page,
  129. .read_page = s3c24xx_read_page,
  130. .write_block_data = &s3c2440_write_block_data,
  131. .read_block_data = &s3c2440_read_block_data,
  132. .nand_ready = &s3c2440_nand_ready,
  133. };