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  1. /***************************************************************************
  2. * Copyright (C) 2004, 2005 by Simtec Electronics *
  3. * linux@simtec.co.uk *
  4. * http://www.simtec.co.uk/products/SWLINUX/ *
  5. * *
  6. * This program is free software; you can redistribute it and/or modify *
  7. * it under the terms of the GNU General Public License as published by *
  8. * the Free Software Foundation; version 2 of the License. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. /*
  21. * S3C2410 NAND register definitions
  22. */
  23. #ifndef __ASM_ARM_REGS_NAND
  24. #define __ASM_ARM_REGS_NAND
  25. #define S3C2410_NFREG(x) (x)
  26. #define S3C2410_NFCONF S3C2410_NFREG(0x00)
  27. #define S3C2410_NFCMD S3C2410_NFREG(0x04)
  28. #define S3C2410_NFADDR S3C2410_NFREG(0x08)
  29. #define S3C2410_NFDATA S3C2410_NFREG(0x0C)
  30. #define S3C2410_NFSTAT S3C2410_NFREG(0x10)
  31. #define S3C2410_NFECC S3C2410_NFREG(0x14)
  32. #define S3C2440_NFCONT S3C2410_NFREG(0x04)
  33. #define S3C2440_NFCMD S3C2410_NFREG(0x08)
  34. #define S3C2440_NFADDR S3C2410_NFREG(0x0C)
  35. #define S3C2440_NFDATA S3C2410_NFREG(0x10)
  36. #define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
  37. #define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
  38. #define S3C2440_NFECCD S3C2410_NFREG(0x1C)
  39. #define S3C2440_NFSTAT S3C2410_NFREG(0x20)
  40. #define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
  41. #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
  42. #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
  43. #define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
  44. #define S3C2440_NFSECC S3C2410_NFREG(0x34)
  45. #define S3C2440_NFSBLK S3C2410_NFREG(0x38)
  46. #define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
  47. #define S3C2412_NFSBLK S3C2410_NFREG(0x20)
  48. #define S3C2412_NFEBLK S3C2410_NFREG(0x24)
  49. #define S3C2412_NFSTAT S3C2410_NFREG(0x28)
  50. #define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
  51. #define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
  52. #define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
  53. #define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
  54. #define S3C2412_NFSECC S3C2410_NFREG(0x3C)
  55. #define S3C2410_NFCONF_EN (1 << 15)
  56. #define S3C2410_NFCONF_512BYTE (1 << 14)
  57. #define S3C2410_NFCONF_4STEP (1 << 13)
  58. #define S3C2410_NFCONF_INITECC (1 << 12)
  59. #define S3C2410_NFCONF_nFCE (1 << 11)
  60. #define S3C2410_NFCONF_TACLS(x) ((x) << 8)
  61. #define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
  62. #define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
  63. #define S3C2410_NFSTAT_BUSY (1 << 0)
  64. #define S3C2440_NFCONF_BUSWIDTH_8 (0 << 0)
  65. #define S3C2440_NFCONF_BUSWIDTH_16 (1 << 0)
  66. #define S3C2440_NFCONF_ADVFLASH (1 << 3)
  67. #define S3C2440_NFCONF_TACLS(x) ((x) << 12)
  68. #define S3C2440_NFCONF_TWRPH0(x) ((x) << 8)
  69. #define S3C2440_NFCONF_TWRPH1(x) ((x) << 4)
  70. #define S3C2440_NFCONT_LOCKTIGHT (1 << 13)
  71. #define S3C2440_NFCONT_SOFTLOCK (1 << 12)
  72. #define S3C2440_NFCONT_ILLEGALACC_EN (1 << 10)
  73. #define S3C2440_NFCONT_RNBINT_EN (1 << 9)
  74. #define S3C2440_NFCONT_RN_FALLING (1 << 8)
  75. #define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
  76. #define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
  77. #define S3C2440_NFCONT_INITECC (1 << 4)
  78. #define S3C2440_NFCONT_nFCE (1 << 1)
  79. #define S3C2440_NFCONT_ENABLE (1 << 0)
  80. #define S3C2440_NFSTAT_READY (1 << 0)
  81. #define S3C2440_NFSTAT_nCE (1 << 1)
  82. #define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
  83. #define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
  84. #define S3C2412_NFCONF_NANDBOOT (1 << 31)
  85. #define S3C2412_NFCONF_ECCCLKCON (1 << 30)
  86. #define S3C2412_NFCONF_ECC_MLC (1 << 24)
  87. #define S3C2412_NFCONF_TACLS_MASK (7 << 12) /* 1 extra bit of Tacls */
  88. #define S3C2412_NFCONT_ECC4_DIRWR (1 << 18)
  89. #define S3C2412_NFCONT_LOCKTIGHT (1 << 17)
  90. #define S3C2412_NFCONT_SOFTLOCK (1 << 16)
  91. #define S3C2412_NFCONT_ECC4_ENCINT (1 << 13)
  92. #define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
  93. #define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
  94. #define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
  95. #define S3C2412_NFCONT_nFCE1 (1 << 2)
  96. #define S3C2412_NFCONT_nFCE0 (1 << 1)
  97. #define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
  98. #define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
  99. #define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
  100. #define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
  101. #define S3C2412_NFSTAT_nFCE1 (1 << 3)
  102. #define S3C2412_NFSTAT_nFCE0 (1 << 2)
  103. #define S3C2412_NFSTAT_Res1 (1 << 1)
  104. #define S3C2412_NFSTAT_READY (1 << 0)
  105. #define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
  106. #define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
  107. #define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
  108. #define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
  109. #define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
  110. #define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
  111. #define S3C2412_NFECCERR_NONE (0)
  112. #define S3C2412_NFECCERR_1BIT (1)
  113. #define S3C2412_NFECCERR_MULTIBIT (2)
  114. #define S3C2412_NFECCERR_ECCAREA (3)
  115. #endif /* __ASM_ARM_REGS_NAND */