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openocd/src/flash/nor/at91sam3.c

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  1. /***************************************************************************

  2.  *   Copyright (C) 2009 by Duane Ellis                                     *

  3.  *   openocd@duaneellis.com                                                *

  4.  *                                                                         *

  5.  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *

  6.  *   olaf@uni-paderborn.de                                                 *

  7.  *																		   *

  8.  *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *

  9.  *                     and Jim Norris                                      *

  10.  *   This program is free software; you can redistribute it and/or modify  *

  11.  *   it under the terms of the GNU General public License as published by  *

  12.  *   the Free Software Foundation; either version 2 of the License, or     *

  13.  *   (at your option) any later version.                                   *

  14.  *                                                                         *

  15.  *   This program is distributed in the hope that it will be useful,       *

  16.  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

  17.  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *

  18.  *   GNU General public License for more details.                          *

  19.  *                                                                         *

  20.  *   You should have received a copy of the GNU General public License     *

  21.  *   along with this program; if not, write to the                         *

  22.  *   Free Software Foundation, Inc.,                                       *

  23.  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *

  24. ****************************************************************************/

  25. 

  26. /* Some of the the lower level code was based on code supplied by

  27.  * ATMEL under this copyright. */

  28. 

  29. /* BEGIN ATMEL COPYRIGHT */

  30. /* ----------------------------------------------------------------------------

  31.  *         ATMEL Microcontroller Software Support

  32.  * ----------------------------------------------------------------------------

  33.  * Copyright (c) 2009, Atmel Corporation

  34.  *

  35.  * All rights reserved.

  36.  *

  37.  * Redistribution and use in source and binary forms, with or without

  38.  * modification, are permitted provided that the following conditions are met:

  39.  *

  40.  * - Redistributions of source code must retain the above copyright notice,

  41.  * this list of conditions and the disclaimer below.

  42.  *

  43.  * Atmel's name may not be used to endorse or promote products derived from

  44.  * this software without specific prior written permission.

  45.  *

  46.  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

  47.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

  48.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

  49.  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

  50.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

  51.  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

  52.  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

  53.  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

  54.  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

  55.  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  56.  * ----------------------------------------------------------------------------

  57.  */

  58. /* END ATMEL COPYRIGHT */

  59. 

  60. #ifdef HAVE_CONFIG_H

  61. #include "config.h"

  62. #endif

  63. 

  64. #include "imp.h"

  65. #include <helper/time_support.h>

  66. 

  67. #define REG_NAME_WIDTH  (12)

  68. 

  69. /* at91sam3u series (has one or two flash banks) */

  70. #define FLASH_BANK0_BASE_U   0x00080000

  71. #define FLASH_BANK1_BASE_U   0x00100000

  72. 

  73. /* at91sam3s series (has always one flash bank) */

  74. #define FLASH_BANK_BASE_S   0x00400000

  75. 

  76. /* at91sam3n series (has always one flash bank) */

  77. #define FLASH_BANK_BASE_N   0x00400000

  78. 

  79. /* at91sam3a/x series has two flash banks*/

  80. #define	FLASH_BANK0_BASE_AX			0x00080000

  81. /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/

  82. #define	FLASH_BANK1_BASE_256K_AX	0x000A0000

  83. #define	FLASH_BANK1_BASE_512K_AX	0x000C0000

  84. 

  85. #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S

  86. #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))

  87. 

  88. #define         AT91C_EFC_FCMD_GETD                 (0x0)	/* (EFC) Get Flash Descriptor */

  89. #define         AT91C_EFC_FCMD_WP                   (0x1)	/* (EFC) Write Page */

  90. #define         AT91C_EFC_FCMD_WPL                  (0x2)	/* (EFC) Write Page and Lock */

  91. #define         AT91C_EFC_FCMD_EWP                  (0x3)	/* (EFC) Erase Page and Write Page */

  92. #define         AT91C_EFC_FCMD_EWPL                 (0x4)	/* (EFC) Erase Page and Write Page then Lock */

  93. #define         AT91C_EFC_FCMD_EA                   (0x5)	/* (EFC) Erase All */

  94. /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */

  95. /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */

  96. /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */

  97. /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */

  98. #define         AT91C_EFC_FCMD_SLB                  (0x8)	/* (EFC) Set Lock Bit */

  99. #define         AT91C_EFC_FCMD_CLB                  (0x9)	/* (EFC) Clear Lock Bit */

  100. #define         AT91C_EFC_FCMD_GLB                  (0xA)	/* (EFC) Get Lock Bit */

  101. #define         AT91C_EFC_FCMD_SFB                  (0xB)	/* (EFC) Set Fuse Bit */

  102. #define         AT91C_EFC_FCMD_CFB                  (0xC)	/* (EFC) Clear Fuse Bit */

  103. #define         AT91C_EFC_FCMD_GFB                  (0xD)	/* (EFC) Get Fuse Bit */

  104. #define         AT91C_EFC_FCMD_STUI                 (0xE)	/* (EFC) Start Read Unique ID */

  105. #define         AT91C_EFC_FCMD_SPUI                 (0xF)	/* (EFC) Stop Read Unique ID */

  106. 

  107. #define  offset_EFC_FMR   0

  108. #define  offset_EFC_FCR   4

  109. #define  offset_EFC_FSR   8

  110. #define  offset_EFC_FRR   12

  111. 

  112. extern struct flash_driver at91sam3_flash;

  113. 

  114. static float _tomhz(uint32_t freq_hz)

  115. {

  116. 	float f;

  117. 

  118. 	f = ((float)(freq_hz)) / 1000000.0;

  119. 	return f;

  120. }

  121. 

  122. /* How the chip is configured. */

  123. struct sam3_cfg {

  124. 	uint32_t unique_id[4];

  125. 

  126. 	uint32_t slow_freq;

  127. 	uint32_t rc_freq;

  128. 	uint32_t mainosc_freq;

  129. 	uint32_t plla_freq;

  130. 	uint32_t mclk_freq;

  131. 	uint32_t cpu_freq;

  132. 	uint32_t fclk_freq;

  133. 	uint32_t pclk0_freq;

  134. 	uint32_t pclk1_freq;

  135. 	uint32_t pclk2_freq;

  136. 

  137. 

  138. #define SAM3_CHIPID_CIDR          (0x400E0740)

  139. 	uint32_t CHIPID_CIDR;

  140. #define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/

  141. 	uint32_t CHIPID_CIDR2;

  142. #define SAM3_CHIPID_EXID          (0x400E0744)

  143. 	uint32_t CHIPID_EXID;

  144. #define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/

  145. 	uint32_t CHIPID_EXID2;

  146. 

  147. 

  148. #define SAM3_PMC_BASE             (0x400E0400)

  149. #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)

  150. 	uint32_t PMC_SCSR;

  151. #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)

  152. 	uint32_t PMC_PCSR;

  153. #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)

  154. 	uint32_t CKGR_UCKR;

  155. #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)

  156. 	uint32_t CKGR_MOR;

  157. #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)

  158. 	uint32_t CKGR_MCFR;

  159. #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)

  160. 	uint32_t CKGR_PLLAR;

  161. #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)

  162. 	uint32_t PMC_MCKR;

  163. #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)

  164. 	uint32_t PMC_PCK0;

  165. #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)

  166. 	uint32_t PMC_PCK1;

  167. #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)

  168. 	uint32_t PMC_PCK2;

  169. #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)

  170. 	uint32_t PMC_SR;

  171. #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)

  172. 	uint32_t PMC_IMR;

  173. #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)

  174. 	uint32_t PMC_FSMR;

  175. #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)

  176. 	uint32_t PMC_FSPR;

  177. };

  178. 

  179. /*

  180.  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011

  181.  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes

  182.  * the flash wait state (FWS) should be set to 6. It seems like that the

  183.  * cause of the problem is not the flash itself, but the flash write

  184.  * buffer. Ie the wait states have to be set before writing into the

  185.  * buffer.

  186.  * Tested and confirmed with SAM3N and SAM3U

  187.  */

  188. 

  189. struct sam3_bank_private {

  190. 	int probed;

  191. 	/* DANGER: THERE ARE DRAGONS HERE.. */

  192. 	/* NOTE: If you add more 'ghost' pointers */

  193. 	/* be aware that you must *manually* update */

  194. 	/* these pointers in the function sam3_GetDetails() */

  195. 	/* See the comment "Here there be dragons" */

  196. 

  197. 	/* so we can find the chip we belong to */

  198. 	struct sam3_chip *pChip;

  199. 	/* so we can find the original bank pointer */

  200. 	struct flash_bank *pBank;

  201. 	unsigned bank_number;

  202. 	uint32_t controller_address;

  203. 	uint32_t base_address;

  204. 	uint32_t flash_wait_states;

  205. 	bool present;

  206. 	unsigned size_bytes;

  207. 	unsigned nsectors;

  208. 	unsigned sector_size;

  209. 	unsigned page_size;

  210. };

  211. 

  212. struct sam3_chip_details {

  213. 	/* THERE ARE DRAGONS HERE.. */

  214. 	/* note: If you add pointers here */

  215. 	/* be careful about them as they */

  216. 	/* may need to be updated inside */

  217. 	/* the function: "sam3_GetDetails() */

  218. 	/* which copy/overwrites the */

  219. 	/* 'runtime' copy of this structure */

  220. 	uint32_t chipid_cidr;

  221. 	const char *name;

  222. 

  223. 	unsigned n_gpnvms;

  224. #define SAM3_N_NVM_BITS 3

  225. 	unsigned gpnvm[SAM3_N_NVM_BITS];

  226. 	unsigned total_flash_size;

  227. 	unsigned total_sram_size;

  228. 	unsigned n_banks;

  229. #define SAM3_MAX_FLASH_BANKS 2

  230. 	/* these are "initialized" from the global const data */

  231. 	struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];

  232. };

  233. 

  234. struct sam3_chip {

  235. 	struct sam3_chip *next;

  236. 	int probed;

  237. 

  238. 	/* this is "initialized" from the global const structure */

  239. 	struct sam3_chip_details details;

  240. 	struct target *target;

  241. 	struct sam3_cfg cfg;

  242. };

  243. 

  244. 

  245. struct sam3_reg_list {

  246. 	uint32_t address;  size_t struct_offset; const char *name;

  247. 	void (*explain_func)(struct sam3_chip *pInfo);

  248. };

  249. 

  250. static struct sam3_chip *all_sam3_chips;

  251. 

  252. static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)

  253. {

  254. 	struct target *t;

  255. 	static struct sam3_chip *p;

  256. 

  257. 	t = get_current_target(cmd_ctx);

  258. 	if (!t) {

  259. 		command_print(cmd_ctx, "No current target?");

  260. 		return NULL;

  261. 	}

  262. 

  263. 	p = all_sam3_chips;

  264. 	if (!p) {

  265. 		/* this should not happen */

  266. 		/* the command is not registered until the chip is created? */

  267. 		command_print(cmd_ctx, "No SAM3 chips exist?");

  268. 		return NULL;

  269. 	}

  270. 

  271. 	while (p) {

  272. 		if (p->target == t)

  273. 			return p;

  274. 		p = p->next;

  275. 	}

  276. 	command_print(cmd_ctx, "Cannot find SAM3 chip?");

  277. 	return NULL;

  278. }

  279. 

  280. /* these are used to *initialize* the "pChip->details" structure. */

  281. static const struct sam3_chip_details all_sam3_details[] = {

  282. 	/* Start at91sam3u* series */

  283. 	{

  284. 		.chipid_cidr    = 0x28100960,

  285. 		.name           = "at91sam3u4e",

  286. 		.total_flash_size     = 256 * 1024,

  287. 		.total_sram_size      = 52 * 1024,

  288. 		.n_gpnvms       = 3,

  289. 		.n_banks        = 2,

  290. 

  291. 		/* System boots at address 0x0 */

  292. 		/* gpnvm[1] = selects boot code */

  293. 		/*     if gpnvm[1] == 0 */

  294. 		/*         boot is via "SAMBA" (rom) */

  295. 		/*     else */

  296. 		/*         boot is via FLASH */

  297. 		/*         Selection is via gpnvm[2] */

  298. 		/*     endif */

  299. 		/*  */

  300. 		/* NOTE: banks 0 & 1 switch places */

  301. 		/*     if gpnvm[2] == 0 */

  302. 		/*         Bank0 is the boot rom */

  303. 		/*      else */

  304. 		/*         Bank1 is the boot rom */

  305. 		/*      endif */

  306. /*		.bank[0] = { */

  307. 		{

  308. 			{

  309. 				.probed = 0,

  310. 				.pChip  = NULL,

  311. 				.pBank  = NULL,

  312. 				.bank_number = 0,

  313. 				.base_address = FLASH_BANK0_BASE_U,

  314. 				.controller_address = 0x400e0800,

  315. 				.flash_wait_states = 6,	/* workaround silicon bug */

  316. 				.present = 1,

  317. 				.size_bytes = 128 * 1024,

  318. 				.nsectors   = 16,

  319. 				.sector_size = 8192,

  320. 				.page_size   = 256,

  321. 			},

  322. 

  323. /*		.bank[1] = { */

  324. 			{

  325. 				.probed = 0,

  326. 				.pChip  = NULL,

  327. 				.pBank  = NULL,

  328. 				.bank_number = 1,

  329. 				.base_address = FLASH_BANK1_BASE_U,

  330. 				.controller_address = 0x400e0a00,

  331. 				.flash_wait_states = 6,	/* workaround silicon bug */

  332. 				.present = 1,

  333. 				.size_bytes = 128 * 1024,

  334. 				.nsectors   = 16,

  335. 				.sector_size = 8192,

  336. 				.page_size   = 256,

  337. 			},

  338. 		},

  339. 	},

  340. 

  341. 	{

  342. 		.chipid_cidr    = 0x281a0760,

  343. 		.name           = "at91sam3u2e",

  344. 		.total_flash_size     = 128 * 1024,

  345. 		.total_sram_size      = 36 * 1024,

  346. 		.n_gpnvms       = 2,

  347. 		.n_banks        = 1,

  348. 

  349. 		/* System boots at address 0x0 */

  350. 		/* gpnvm[1] = selects boot code */

  351. 		/*     if gpnvm[1] == 0 */

  352. 		/*         boot is via "SAMBA" (rom) */

  353. 		/*     else */

  354. 		/*         boot is via FLASH */

  355. 		/*         Selection is via gpnvm[2] */

  356. 		/*     endif */

  357. /*		.bank[0] = { */

  358. 		{

  359. 			{

  360. 				.probed = 0,

  361. 				.pChip  = NULL,

  362. 				.pBank  = NULL,

  363. 				.bank_number = 0,

  364. 				.base_address = FLASH_BANK0_BASE_U,

  365. 				.controller_address = 0x400e0800,

  366. 				.flash_wait_states = 6,	/* workaround silicon bug */

  367. 				.present = 1,

  368. 				.size_bytes = 128 * 1024,

  369. 				.nsectors   = 16,

  370. 				.sector_size = 8192,

  371. 				.page_size   = 256,

  372. 			},

  373. /*		  .bank[1] = { */

  374. 			{

  375. 				.present = 0,

  376. 				.probed = 0,

  377. 				.bank_number = 1,

  378. 			},

  379. 		},

  380. 	},

  381. 	{

  382. 		.chipid_cidr    = 0x28190560,

  383. 		.name           = "at91sam3u1e",

  384. 		.total_flash_size     = 64 * 1024,

  385. 		.total_sram_size      = 20 * 1024,

  386. 		.n_gpnvms       = 2,

  387. 		.n_banks        = 1,

  388. 

  389. 		/* System boots at address 0x0 */

  390. 		/* gpnvm[1] = selects boot code */

  391. 		/*     if gpnvm[1] == 0 */

  392. 		/*         boot is via "SAMBA" (rom) */

  393. 		/*     else */

  394. 		/*         boot is via FLASH */

  395. 		/*         Selection is via gpnvm[2] */

  396. 		/*     endif */

  397. 		/*  */

  398. 

  399. /*		.bank[0] = { */

  400. 		{

  401. 			{

  402. 				.probed = 0,

  403. 				.pChip  = NULL,

  404. 				.pBank  = NULL,

  405. 				.bank_number = 0,

  406. 				.base_address = FLASH_BANK0_BASE_U,

  407. 				.controller_address = 0x400e0800,

  408. 				.flash_wait_states = 6,	/* workaround silicon bug */

  409. 				.present = 1,

  410. 				.size_bytes = 64 * 1024,

  411. 				.nsectors   = 8,

  412. 				.sector_size = 8192,

  413. 				.page_size   = 256,

  414. 			},

  415. 

  416. /*		.bank[1] = { */

  417. 			{

  418. 				.present = 0,

  419. 				.probed = 0,

  420. 				.bank_number = 1,

  421. 			},

  422. 		},

  423. 	},

  424. 

  425. 	{

  426. 		.chipid_cidr    = 0x28000960,

  427. 		.name           = "at91sam3u4c",

  428. 		.total_flash_size     = 256 * 1024,

  429. 		.total_sram_size      = 52 * 1024,

  430. 		.n_gpnvms       = 3,

  431. 		.n_banks        = 2,

  432. 

  433. 		/* System boots at address 0x0 */

  434. 		/* gpnvm[1] = selects boot code */

  435. 		/*     if gpnvm[1] == 0 */

  436. 		/*         boot is via "SAMBA" (rom) */

  437. 		/*     else */

  438. 		/*         boot is via FLASH */

  439. 		/*         Selection is via gpnvm[2] */

  440. 		/*     endif */

  441. 		/*  */

  442. 		/* NOTE: banks 0 & 1 switch places */

  443. 		/*     if gpnvm[2] == 0 */

  444. 		/*         Bank0 is the boot rom */

  445. 		/*      else */

  446. 		/*         Bank1 is the boot rom */

  447. 		/*      endif */

  448. 		{

  449. 			{

  450. /*		.bank[0] = { */

  451. 				.probed = 0,

  452. 				.pChip  = NULL,

  453. 				.pBank  = NULL,

  454. 				.bank_number = 0,

  455. 				.base_address = FLASH_BANK0_BASE_U,

  456. 				.controller_address = 0x400e0800,

  457. 				.flash_wait_states = 6,	/* workaround silicon bug */

  458. 				.present = 1,

  459. 				.size_bytes = 128 * 1024,

  460. 				.nsectors   = 16,

  461. 				.sector_size = 8192,

  462. 				.page_size   = 256,

  463. 			},

  464. /*		.bank[1] = { */

  465. 			{

  466. 				.probed = 0,

  467. 				.pChip  = NULL,

  468. 				.pBank  = NULL,

  469. 				.bank_number = 1,

  470. 				.base_address = FLASH_BANK1_BASE_U,

  471. 				.controller_address = 0x400e0a00,

  472. 				.flash_wait_states = 6,	/* workaround silicon bug */

  473. 				.present = 1,

  474. 				.size_bytes = 128 * 1024,

  475. 				.nsectors   = 16,

  476. 				.sector_size = 8192,

  477. 				.page_size   = 256,

  478. 			},

  479. 		},

  480. 	},

  481. 

  482. 	{

  483. 		.chipid_cidr    = 0x280a0760,

  484. 		.name           = "at91sam3u2c",

  485. 		.total_flash_size     = 128 * 1024,

  486. 		.total_sram_size      = 36 * 1024,

  487. 		.n_gpnvms       = 2,

  488. 		.n_banks        = 1,

  489. 

  490. 		/* System boots at address 0x0 */

  491. 		/* gpnvm[1] = selects boot code */

  492. 		/*     if gpnvm[1] == 0 */

  493. 		/*         boot is via "SAMBA" (rom) */

  494. 		/*     else */

  495. 		/*         boot is via FLASH */

  496. 		/*         Selection is via gpnvm[2] */

  497. 		/*     endif */

  498. 		{

  499. /*		.bank[0] = { */

  500. 			{

  501. 				.probed = 0,

  502. 				.pChip  = NULL,

  503. 				.pBank  = NULL,

  504. 				.bank_number = 0,

  505. 				.base_address = FLASH_BANK0_BASE_U,

  506. 				.controller_address = 0x400e0800,

  507. 				.flash_wait_states = 6,	/* workaround silicon bug */

  508. 				.present = 1,

  509. 				.size_bytes = 128 * 1024,

  510. 				.nsectors   = 16,

  511. 				.sector_size = 8192,

  512. 				.page_size   = 256,

  513. 			},

  514. /*		.bank[1] = { */

  515. 			{

  516. 				.present = 0,

  517. 				.probed = 0,

  518. 				.bank_number = 1,

  519. 			},

  520. 		},

  521. 	},

  522. 	{

  523. 		.chipid_cidr    = 0x28090560,

  524. 		.name           = "at91sam3u1c",

  525. 		.total_flash_size     = 64 * 1024,

  526. 		.total_sram_size      = 20 * 1024,

  527. 		.n_gpnvms       = 2,

  528. 		.n_banks        = 1,

  529. 

  530. 		/* System boots at address 0x0 */

  531. 		/* gpnvm[1] = selects boot code */

  532. 		/*     if gpnvm[1] == 0 */

  533. 		/*         boot is via "SAMBA" (rom) */

  534. 		/*     else */

  535. 		/*         boot is via FLASH */

  536. 		/*         Selection is via gpnvm[2] */

  537. 		/*     endif */

  538. 		/*  */

  539. 

  540. 		{

  541. /*		.bank[0] = { */

  542. 			{

  543. 				.probed = 0,

  544. 				.pChip  = NULL,

  545. 				.pBank  = NULL,

  546. 				.bank_number = 0,

  547. 				.base_address = FLASH_BANK0_BASE_U,

  548. 				.controller_address = 0x400e0800,

  549. 				.flash_wait_states = 6,	/* workaround silicon bug */

  550. 				.present = 1,

  551. 				.size_bytes = 64 * 1024,

  552. 				.nsectors   = 8,

  553. 				.sector_size = 8192,

  554. 				.page_size   = 256,

  555. 			},

  556. /*		.bank[1] = { */

  557. 			{

  558. 				.present = 0,

  559. 				.probed = 0,

  560. 				.bank_number = 1,

  561. 

  562. 			},

  563. 		},

  564. 	},

  565. 

  566. 	/* Start at91sam3s* series */

  567. 

  568. 	/* Note: The preliminary at91sam3s datasheet says on page 302 */

  569. 	/* that the flash controller is at address 0x400E0800. */

  570. 	/* This is _not_ the case, the controller resides at address 0x400e0a0. */

  571. 	{

  572. 		.chipid_cidr    = 0x28A00960,

  573. 		.name           = "at91sam3s4c",

  574. 		.total_flash_size     = 256 * 1024,

  575. 		.total_sram_size      = 48 * 1024,

  576. 		.n_gpnvms       = 2,

  577. 		.n_banks        = 1,

  578. 		{

  579. /*		.bank[0] = { */

  580. 			{

  581. 				.probed = 0,

  582. 				.pChip  = NULL,

  583. 				.pBank  = NULL,

  584. 				.bank_number = 0,

  585. 				.base_address = FLASH_BANK_BASE_S,

  586. 				.controller_address = 0x400e0a00,

  587. 				.flash_wait_states = 6,	/* workaround silicon bug */

  588. 				.present = 1,

  589. 				.size_bytes = 256 * 1024,

  590. 				.nsectors   = 16,

  591. 				.sector_size = 16384,

  592. 				.page_size   = 256,

  593. 			},

  594. /*		.bank[1] = { */

  595. 			{

  596. 				.present = 0,

  597. 				.probed = 0,

  598. 				.bank_number = 1,

  599. 

  600. 			},

  601. 		},

  602. 	},

  603. 

  604. 	{

  605. 		.chipid_cidr    = 0x28900960,

  606. 		.name           = "at91sam3s4b",

  607. 		.total_flash_size     = 256 * 1024,

  608. 		.total_sram_size      = 48 * 1024,

  609. 		.n_gpnvms       = 2,

  610. 		.n_banks        = 1,

  611. 		{

  612. /*		.bank[0] = { */

  613. 			{

  614. 				.probed = 0,

  615. 				.pChip  = NULL,

  616. 				.pBank  = NULL,

  617. 				.bank_number = 0,

  618. 				.base_address = FLASH_BANK_BASE_S,

  619. 				.controller_address = 0x400e0a00,

  620. 				.flash_wait_states = 6,	/* workaround silicon bug */

  621. 				.present = 1,

  622. 				.size_bytes = 256 * 1024,

  623. 				.nsectors   = 16,

  624. 				.sector_size = 16384,

  625. 				.page_size   = 256,

  626. 			},

  627. /*		.bank[1] = { */

  628. 			{

  629. 				.present = 0,

  630. 				.probed = 0,

  631. 				.bank_number = 1,

  632. 

  633. 			},

  634. 		},

  635. 	},

  636. 	{

  637. 		.chipid_cidr    = 0x28800960,

  638. 		.name           = "at91sam3s4a",

  639. 		.total_flash_size     = 256 * 1024,

  640. 		.total_sram_size      = 48 * 1024,

  641. 		.n_gpnvms       = 2,

  642. 		.n_banks        = 1,

  643. 		{

  644. /*		.bank[0] = { */

  645. 			{

  646. 				.probed = 0,

  647. 				.pChip  = NULL,

  648. 				.pBank  = NULL,

  649. 				.bank_number = 0,

  650. 				.base_address = FLASH_BANK_BASE_S,

  651. 				.controller_address = 0x400e0a00,

  652. 				.flash_wait_states = 6,	/* workaround silicon bug */

  653. 				.present = 1,

  654. 				.size_bytes = 256 * 1024,

  655. 				.nsectors   = 16,

  656. 				.sector_size = 16384,

  657. 				.page_size   = 256,

  658. 			},

  659. /*		.bank[1] = { */

  660. 			{

  661. 				.present = 0,

  662. 				.probed = 0,

  663. 				.bank_number = 1,

  664. 

  665. 			},

  666. 		},

  667. 	},

  668. 	{

  669. 		.chipid_cidr    = 0x28AA0760,

  670. 		.name           = "at91sam3s2c",

  671. 		.total_flash_size     = 128 * 1024,

  672. 		.total_sram_size      = 32 * 1024,

  673. 		.n_gpnvms       = 2,

  674. 		.n_banks        = 1,

  675. 		{

  676. /*		.bank[0] = { */

  677. 			{

  678. 				.probed = 0,

  679. 				.pChip  = NULL,

  680. 				.pBank  = NULL,

  681. 				.bank_number = 0,

  682. 				.base_address = FLASH_BANK_BASE_S,

  683. 				.controller_address = 0x400e0a00,

  684. 				.flash_wait_states = 6,	/* workaround silicon bug */

  685. 				.present = 1,

  686. 				.size_bytes = 128 * 1024,

  687. 				.nsectors   = 8,

  688. 				.sector_size = 16384,

  689. 				.page_size   = 256,

  690. 			},

  691. /*		.bank[1] = { */

  692. 			{

  693. 				.present = 0,

  694. 				.probed = 0,

  695. 				.bank_number = 1,

  696. 

  697. 			},

  698. 		},

  699. 	},

  700. 	{

  701. 		.chipid_cidr    = 0x289A0760,

  702. 		.name           = "at91sam3s2b",

  703. 		.total_flash_size     = 128 * 1024,

  704. 		.total_sram_size      = 32 * 1024,

  705. 		.n_gpnvms       = 2,

  706. 		.n_banks        = 1,

  707. 		{

  708. /*		.bank[0] = { */

  709. 			{

  710. 				.probed = 0,

  711. 				.pChip  = NULL,

  712. 				.pBank  = NULL,

  713. 				.bank_number = 0,

  714. 				.base_address = FLASH_BANK_BASE_S,

  715. 				.controller_address = 0x400e0a00,

  716. 				.flash_wait_states = 6,	/* workaround silicon bug */

  717. 				.present = 1,

  718. 				.size_bytes = 128 * 1024,

  719. 				.nsectors   = 8,

  720. 				.sector_size = 16384,

  721. 				.page_size   = 256,

  722. 			},

  723. /*		.bank[1] = { */

  724. 			{

  725. 				.present = 0,

  726. 				.probed = 0,

  727. 				.bank_number = 1,

  728. 

  729. 			},

  730. 		},

  731. 	},

  732. 	{

  733. 		.chipid_cidr    = 0x29ab0a60,

  734. 		.name           = "at91sam3sd8c",

  735. 		.total_flash_size     = 512 * 1024,

  736. 		.total_sram_size      = 64 * 1024,

  737. 		.n_gpnvms       = 3,

  738. 		.n_banks        = 2,

  739. 		{

  740. /*			.bank[0] = { */

  741. 			{

  742. 				.probed = 0,

  743. 				.pChip  = NULL,

  744. 				.pBank  = NULL,

  745. 				.bank_number = 0,

  746. 				.base_address = FLASH_BANK0_BASE_SD,

  747. 				.controller_address = 0x400e0a00,

  748. 				.flash_wait_states = 6,	/* workaround silicon bug */

  749. 				.present = 1,

  750. 				.size_bytes =  256 * 1024,

  751. 				.nsectors   =  16,

  752. 				.sector_size = 16384,

  753. 				.page_size   = 256,

  754. 			  },

  755. /*			.bank[1] = { */

  756. 			  {

  757. 				.probed = 0,

  758. 				.pChip  = NULL,

  759. 				.pBank  = NULL,

  760. 				.bank_number = 1,

  761. 				.base_address = FLASH_BANK1_BASE_512K_SD,

  762. 				.controller_address = 0x400e0a00,

  763. 				.flash_wait_states = 6,	/* workaround silicon bug */

  764. 				.present = 1,

  765. 				.size_bytes =  256 * 1024,

  766. 				.nsectors   =  16,

  767. 				.sector_size = 16384,

  768. 				.page_size   = 256,

  769. 			},

  770. 		},

  771. 	},

  772. 	{

  773. 		.chipid_cidr    = 0x288A0760,

  774. 		.name           = "at91sam3s2a",

  775. 		.total_flash_size     = 128 * 1024,

  776. 		.total_sram_size      = 32 * 1024,

  777. 		.n_gpnvms       = 2,

  778. 		.n_banks        = 1,

  779. 		{

  780. /*		.bank[0] = { */

  781. 			{

  782. 				.probed = 0,

  783. 				.pChip  = NULL,

  784. 				.pBank  = NULL,

  785. 				.bank_number = 0,

  786. 				.base_address = FLASH_BANK_BASE_S,

  787. 				.controller_address = 0x400e0a00,

  788. 				.flash_wait_states = 6,	/* workaround silicon bug */

  789. 				.present = 1,

  790. 				.size_bytes = 128 * 1024,

  791. 				.nsectors   = 8,

  792. 				.sector_size = 16384,

  793. 				.page_size   = 256,

  794. 			},

  795. /*		.bank[1] = { */

  796. 			{

  797. 				.present = 0,

  798. 				.probed = 0,

  799. 				.bank_number = 1,

  800. 

  801. 			},

  802. 		},

  803. 	},

  804. 	{

  805. 		.chipid_cidr    = 0x28A90560,

  806. 		.name           = "at91sam3s1c",

  807. 		.total_flash_size     = 64 * 1024,

  808. 		.total_sram_size      = 16 * 1024,

  809. 		.n_gpnvms       = 2,

  810. 		.n_banks        = 1,

  811. 		{

  812. /*		.bank[0] = { */

  813. 			{

  814. 				.probed = 0,

  815. 				.pChip  = NULL,

  816. 				.pBank  = NULL,

  817. 				.bank_number = 0,

  818. 				.base_address = FLASH_BANK_BASE_S,

  819. 				.controller_address = 0x400e0a00,

  820. 				.flash_wait_states = 6,	/* workaround silicon bug */

  821. 				.present = 1,

  822. 				.size_bytes = 64 * 1024,

  823. 				.nsectors   = 4,

  824. 				.sector_size = 16384,

  825. 				.page_size   = 256,

  826. 			},

  827. /*		.bank[1] = { */

  828. 			{

  829. 				.present = 0,

  830. 				.probed = 0,

  831. 				.bank_number = 1,

  832. 

  833. 			},

  834. 		},

  835. 	},

  836. 	{

  837. 		.chipid_cidr    = 0x28990560,

  838. 		.name           = "at91sam3s1b",

  839. 		.total_flash_size     = 64 * 1024,

  840. 		.total_sram_size      = 16 * 1024,

  841. 		.n_gpnvms       = 2,

  842. 		.n_banks        = 1,

  843. 		{

  844. /*		.bank[0] = { */

  845. 			{

  846. 				.probed = 0,

  847. 				.pChip  = NULL,

  848. 				.pBank  = NULL,

  849. 				.bank_number = 0,

  850. 				.base_address = FLASH_BANK_BASE_S,

  851. 				.controller_address = 0x400e0a00,

  852. 				.flash_wait_states = 6,	/* workaround silicon bug */

  853. 				.present = 1,

  854. 				.size_bytes = 64 * 1024,

  855. 				.nsectors   = 4,

  856. 				.sector_size = 16384,

  857. 				.page_size   = 256,

  858. 			},

  859. /*		.bank[1] = { */

  860. 			{

  861. 				.present = 0,

  862. 				.probed = 0,

  863. 				.bank_number = 1,

  864. 

  865. 			},

  866. 		},

  867. 	},

  868. 	{

  869. 		.chipid_cidr    = 0x28890560,

  870. 		.name           = "at91sam3s1a",

  871. 		.total_flash_size     = 64 * 1024,

  872. 		.total_sram_size      = 16 * 1024,

  873. 		.n_gpnvms       = 2,

  874. 		.n_banks        = 1,

  875. 		{

  876. /*		.bank[0] = { */

  877. 			{

  878. 				.probed = 0,

  879. 				.pChip  = NULL,

  880. 				.pBank  = NULL,

  881. 				.bank_number = 0,

  882. 				.base_address = FLASH_BANK_BASE_S,

  883. 				.controller_address = 0x400e0a00,

  884. 				.flash_wait_states = 6,	/* workaround silicon bug */

  885. 				.present = 1,

  886. 				.size_bytes = 64 * 1024,

  887. 				.nsectors   = 4,

  888. 				.sector_size = 16384,

  889. 				.page_size   = 256,

  890. 			},

  891. /*		.bank[1] = { */

  892. 			{

  893. 				.present = 0,

  894. 				.probed = 0,

  895. 				.bank_number = 1,

  896. 

  897. 			},

  898. 		},

  899. 	},

  900. 

  901. 	/* Start at91sam3n* series */

  902. 	{

  903. 		.chipid_cidr    = 0x29540960,

  904. 		.name           = "at91sam3n4c",

  905. 		.total_flash_size     = 256 * 1024,

  906. 		.total_sram_size      = 24 * 1024,

  907. 		.n_gpnvms       = 3,

  908. 		.n_banks        = 1,

  909. 

  910. 		/* System boots at address 0x0 */

  911. 		/* gpnvm[1] = selects boot code */

  912. 		/*     if gpnvm[1] == 0 */

  913. 		/*         boot is via "SAMBA" (rom) */

  914. 		/*     else */

  915. 		/*         boot is via FLASH */

  916. 		/*         Selection is via gpnvm[2] */

  917. 		/*     endif */

  918. 		/*  */

  919. 		/* NOTE: banks 0 & 1 switch places */

  920. 		/*     if gpnvm[2] == 0 */

  921. 		/*         Bank0 is the boot rom */

  922. 		/*      else */

  923. 		/*         Bank1 is the boot rom */

  924. 		/*      endif */

  925. /*		.bank[0] = { */

  926. 		{

  927. 			{

  928. 				.probed = 0,

  929. 				.pChip  = NULL,

  930. 				.pBank  = NULL,

  931. 				.bank_number = 0,

  932. 				.base_address = FLASH_BANK_BASE_N,

  933. 				.controller_address = 0x400e0A00,

  934. 				.flash_wait_states = 6,	/* workaround silicon bug */

  935. 				.present = 1,

  936. 				.size_bytes = 256 * 1024,

  937. 				.nsectors   = 16,

  938. 				.sector_size = 16384,

  939. 				.page_size   = 256,

  940. 			},

  941. 

  942. /*		.bank[1] = { */

  943. 			{

  944. 				.present = 0,

  945. 				.probed = 0,

  946. 				.bank_number = 1,

  947. 			},

  948. 		},

  949. 	},

  950. 

  951. 	{

  952. 		.chipid_cidr    = 0x29440960,

  953. 		.name           = "at91sam3n4b",

  954. 		.total_flash_size     = 256 * 1024,

  955. 		.total_sram_size      = 24 * 1024,

  956. 		.n_gpnvms       = 3,

  957. 		.n_banks        = 1,

  958. 

  959. 		/* System boots at address 0x0 */

  960. 		/* gpnvm[1] = selects boot code */

  961. 		/*     if gpnvm[1] == 0 */

  962. 		/*         boot is via "SAMBA" (rom) */

  963. 		/*     else */

  964. 		/*         boot is via FLASH */

  965. 		/*         Selection is via gpnvm[2] */

  966. 		/*     endif */

  967. 		/*  */

  968. 		/* NOTE: banks 0 & 1 switch places */

  969. 		/*     if gpnvm[2] == 0 */

  970. 		/*         Bank0 is the boot rom */

  971. 		/*      else */

  972. 		/*         Bank1 is the boot rom */

  973. 		/*      endif */

  974. /*		.bank[0] = { */

  975. 		{

  976. 			{

  977. 				.probed = 0,

  978. 				.pChip  = NULL,

  979. 				.pBank  = NULL,

  980. 				.bank_number = 0,

  981. 				.base_address = FLASH_BANK_BASE_N,

  982. 				.controller_address = 0x400e0A00,

  983. 				.flash_wait_states = 6,	/* workaround silicon bug */

  984. 				.present = 1,

  985. 				.size_bytes = 256 * 1024,

  986. 				.nsectors   = 16,

  987. 				.sector_size = 16384,

  988. 				.page_size   = 256,

  989. 			},

  990. 

  991. /*		.bank[1] = { */

  992. 			{

  993. 				.present = 0,

  994. 				.probed = 0,

  995. 				.bank_number = 1,

  996. 			},

  997. 		},

  998. 	},

  999. 

  1000. 	{

  1001. 		.chipid_cidr    = 0x29340960,

  1002. 		.name           = "at91sam3n4a",

  1003. 		.total_flash_size     = 256 * 1024,

  1004. 		.total_sram_size      = 24 * 1024,

  1005. 		.n_gpnvms       = 3,

  1006. 		.n_banks        = 1,

  1007. 

  1008. 		/* System boots at address 0x0 */

  1009. 		/* gpnvm[1] = selects boot code */

  1010. 		/*     if gpnvm[1] == 0 */

  1011. 		/*         boot is via "SAMBA" (rom) */

  1012. 		/*     else */

  1013. 		/*         boot is via FLASH */

  1014. 		/*         Selection is via gpnvm[2] */

  1015. 		/*     endif */

  1016. 		/*  */

  1017. 		/* NOTE: banks 0 & 1 switch places */

  1018. 		/*     if gpnvm[2] == 0 */

  1019. 		/*         Bank0 is the boot rom */

  1020. 		/*      else */

  1021. 		/*         Bank1 is the boot rom */

  1022. 		/*      endif */

  1023. /*		.bank[0] = { */

  1024. 		{

  1025. 			{

  1026. 				.probed = 0,

  1027. 				.pChip  = NULL,

  1028. 				.pBank  = NULL,

  1029. 				.bank_number = 0,

  1030. 				.base_address = FLASH_BANK_BASE_N,

  1031. 				.controller_address = 0x400e0A00,

  1032. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1033. 				.present = 1,

  1034. 				.size_bytes = 256 * 1024,

  1035. 				.nsectors   = 16,

  1036. 				.sector_size = 16384,

  1037. 				.page_size   = 256,

  1038. 			},

  1039. 

  1040. /*		.bank[1] = { */

  1041. 			{

  1042. 				.present = 0,

  1043. 				.probed = 0,

  1044. 				.bank_number = 1,

  1045. 			},

  1046. 		},

  1047. 	},

  1048. 

  1049. 	{

  1050. 		.chipid_cidr    = 0x29590760,

  1051. 		.name           = "at91sam3n2c",

  1052. 		.total_flash_size     = 128 * 1024,

  1053. 		.total_sram_size      = 16 * 1024,

  1054. 		.n_gpnvms       = 3,

  1055. 		.n_banks        = 1,

  1056. 

  1057. 		/* System boots at address 0x0 */

  1058. 		/* gpnvm[1] = selects boot code */

  1059. 		/*     if gpnvm[1] == 0 */

  1060. 		/*         boot is via "SAMBA" (rom) */

  1061. 		/*     else */

  1062. 		/*         boot is via FLASH */

  1063. 		/*         Selection is via gpnvm[2] */

  1064. 		/*     endif */

  1065. 		/*  */

  1066. 		/* NOTE: banks 0 & 1 switch places */

  1067. 		/*     if gpnvm[2] == 0 */

  1068. 		/*         Bank0 is the boot rom */

  1069. 		/*      else */

  1070. 		/*         Bank1 is the boot rom */

  1071. 		/*      endif */

  1072. /*		.bank[0] = { */

  1073. 		{

  1074. 			{

  1075. 				.probed = 0,

  1076. 				.pChip  = NULL,

  1077. 				.pBank  = NULL,

  1078. 				.bank_number = 0,

  1079. 				.base_address = FLASH_BANK_BASE_N,

  1080. 				.controller_address = 0x400e0A00,

  1081. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1082. 				.present = 1,

  1083. 				.size_bytes = 128 * 1024,

  1084. 				.nsectors   = 8,

  1085. 				.sector_size = 16384,

  1086. 				.page_size   = 256,

  1087. 			},

  1088. 

  1089. /*		.bank[1] = { */

  1090. 			{

  1091. 				.present = 0,

  1092. 				.probed = 0,

  1093. 				.bank_number = 1,

  1094. 			},

  1095. 		},

  1096. 	},

  1097. 

  1098. 	{

  1099. 		.chipid_cidr    = 0x29490760,

  1100. 		.name           = "at91sam3n2b",

  1101. 		.total_flash_size     = 128 * 1024,

  1102. 		.total_sram_size      = 16 * 1024,

  1103. 		.n_gpnvms       = 3,

  1104. 		.n_banks        = 1,

  1105. 

  1106. 		/* System boots at address 0x0 */

  1107. 		/* gpnvm[1] = selects boot code */

  1108. 		/*     if gpnvm[1] == 0 */

  1109. 		/*         boot is via "SAMBA" (rom) */

  1110. 		/*     else */

  1111. 		/*         boot is via FLASH */

  1112. 		/*         Selection is via gpnvm[2] */

  1113. 		/*     endif */

  1114. 		/*  */

  1115. 		/* NOTE: banks 0 & 1 switch places */

  1116. 		/*     if gpnvm[2] == 0 */

  1117. 		/*         Bank0 is the boot rom */

  1118. 		/*      else */

  1119. 		/*         Bank1 is the boot rom */

  1120. 		/*      endif */

  1121. /*		.bank[0] = { */

  1122. 		{

  1123. 			{

  1124. 				.probed = 0,

  1125. 				.pChip  = NULL,

  1126. 				.pBank  = NULL,

  1127. 				.bank_number = 0,

  1128. 				.base_address = FLASH_BANK_BASE_N,

  1129. 				.controller_address = 0x400e0A00,

  1130. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1131. 				.present = 1,

  1132. 				.size_bytes = 128 * 1024,

  1133. 				.nsectors   = 8,

  1134. 				.sector_size = 16384,

  1135. 				.page_size   = 256,

  1136. 			},

  1137. 

  1138. /*		.bank[1] = { */

  1139. 			{

  1140. 				.present = 0,

  1141. 				.probed = 0,

  1142. 				.bank_number = 1,

  1143. 			},

  1144. 		},

  1145. 	},

  1146. 

  1147. 	{

  1148. 		.chipid_cidr    = 0x29390760,

  1149. 		.name           = "at91sam3n2a",

  1150. 		.total_flash_size     = 128 * 1024,

  1151. 		.total_sram_size      = 16 * 1024,

  1152. 		.n_gpnvms       = 3,

  1153. 		.n_banks        = 1,

  1154. 

  1155. 		/* System boots at address 0x0 */

  1156. 		/* gpnvm[1] = selects boot code */

  1157. 		/*     if gpnvm[1] == 0 */

  1158. 		/*         boot is via "SAMBA" (rom) */

  1159. 		/*     else */

  1160. 		/*         boot is via FLASH */

  1161. 		/*         Selection is via gpnvm[2] */

  1162. 		/*     endif */

  1163. 		/*  */

  1164. 		/* NOTE: banks 0 & 1 switch places */

  1165. 		/*     if gpnvm[2] == 0 */

  1166. 		/*         Bank0 is the boot rom */

  1167. 		/*      else */

  1168. 		/*         Bank1 is the boot rom */

  1169. 		/*      endif */

  1170. /*		.bank[0] = { */

  1171. 		{

  1172. 			{

  1173. 				.probed = 0,

  1174. 				.pChip  = NULL,

  1175. 				.pBank  = NULL,

  1176. 				.bank_number = 0,

  1177. 				.base_address = FLASH_BANK_BASE_N,

  1178. 				.controller_address = 0x400e0A00,

  1179. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1180. 				.present = 1,

  1181. 				.size_bytes = 128 * 1024,

  1182. 				.nsectors   = 8,

  1183. 				.sector_size = 16384,

  1184. 				.page_size   = 256,

  1185. 			},

  1186. 

  1187. /*		.bank[1] = { */

  1188. 			{

  1189. 				.present = 0,

  1190. 				.probed = 0,

  1191. 				.bank_number = 1,

  1192. 			},

  1193. 		},

  1194. 	},

  1195. 

  1196. 	{

  1197. 		.chipid_cidr    = 0x29580560,

  1198. 		.name           = "at91sam3n1c",

  1199. 		.total_flash_size     = 64 * 1024,

  1200. 		.total_sram_size      = 8 * 1024,

  1201. 		.n_gpnvms       = 3,

  1202. 		.n_banks        = 1,

  1203. 

  1204. 		/* System boots at address 0x0 */

  1205. 		/* gpnvm[1] = selects boot code */

  1206. 		/*     if gpnvm[1] == 0 */

  1207. 		/*         boot is via "SAMBA" (rom) */

  1208. 		/*     else */

  1209. 		/*         boot is via FLASH */

  1210. 		/*         Selection is via gpnvm[2] */

  1211. 		/*     endif */

  1212. 		/*  */

  1213. 		/* NOTE: banks 0 & 1 switch places */

  1214. 		/*     if gpnvm[2] == 0 */

  1215. 		/*         Bank0 is the boot rom */

  1216. 		/*      else */

  1217. 		/*         Bank1 is the boot rom */

  1218. 		/*      endif */

  1219. /*		.bank[0] = { */

  1220. 		{

  1221. 			{

  1222. 				.probed = 0,

  1223. 				.pChip  = NULL,

  1224. 				.pBank  = NULL,

  1225. 				.bank_number = 0,

  1226. 				.base_address = FLASH_BANK_BASE_N,

  1227. 				.controller_address = 0x400e0A00,

  1228. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1229. 				.present = 1,

  1230. 				.size_bytes = 64 * 1024,

  1231. 				.nsectors   = 4,

  1232. 				.sector_size = 16384,

  1233. 				.page_size   = 256,

  1234. 			},

  1235. 

  1236. /*		.bank[1] = { */

  1237. 			{

  1238. 				.present = 0,

  1239. 				.probed = 0,

  1240. 				.bank_number = 1,

  1241. 			},

  1242. 		},

  1243. 	},

  1244. 

  1245. 	{

  1246. 		.chipid_cidr    = 0x29480560,

  1247. 		.name           = "at91sam3n1b",

  1248. 		.total_flash_size     = 64 * 1024,

  1249. 		.total_sram_size      = 8 * 1024,

  1250. 		.n_gpnvms       = 3,

  1251. 		.n_banks        = 1,

  1252. 

  1253. 		/* System boots at address 0x0 */

  1254. 		/* gpnvm[1] = selects boot code */

  1255. 		/*     if gpnvm[1] == 0 */

  1256. 		/*         boot is via "SAMBA" (rom) */

  1257. 		/*     else */

  1258. 		/*         boot is via FLASH */

  1259. 		/*         Selection is via gpnvm[2] */

  1260. 		/*     endif */

  1261. 		/*  */

  1262. 		/* NOTE: banks 0 & 1 switch places */

  1263. 		/*     if gpnvm[2] == 0 */

  1264. 		/*         Bank0 is the boot rom */

  1265. 		/*      else */

  1266. 		/*         Bank1 is the boot rom */

  1267. 		/*      endif */

  1268. /*		.bank[0] = { */

  1269. 		{

  1270. 			{

  1271. 				.probed = 0,

  1272. 				.pChip  = NULL,

  1273. 				.pBank  = NULL,

  1274. 				.bank_number = 0,

  1275. 				.base_address = FLASH_BANK_BASE_N,

  1276. 				.controller_address = 0x400e0A00,

  1277. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1278. 				.present = 1,

  1279. 				.size_bytes = 64 * 1024,

  1280. 				.nsectors   = 4,

  1281. 				.sector_size = 16384,

  1282. 				.page_size   = 256,

  1283. 			},

  1284. 

  1285. /*		.bank[1] = { */

  1286. 			{

  1287. 				.present = 0,

  1288. 				.probed = 0,

  1289. 				.bank_number = 1,

  1290. 			},

  1291. 		},

  1292. 	},

  1293. 

  1294. 	{

  1295. 		.chipid_cidr    = 0x29380560,

  1296. 		.name           = "at91sam3n1a",

  1297. 		.total_flash_size     = 64 * 1024,

  1298. 		.total_sram_size      = 8 * 1024,

  1299. 		.n_gpnvms       = 3,

  1300. 		.n_banks        = 1,

  1301. 

  1302. 		/* System boots at address 0x0 */

  1303. 		/* gpnvm[1] = selects boot code */

  1304. 		/*     if gpnvm[1] == 0 */

  1305. 		/*         boot is via "SAMBA" (rom) */

  1306. 		/*     else */

  1307. 		/*         boot is via FLASH */

  1308. 		/*         Selection is via gpnvm[2] */

  1309. 		/*     endif */

  1310. 		/*  */

  1311. 		/* NOTE: banks 0 & 1 switch places */

  1312. 		/*     if gpnvm[2] == 0 */

  1313. 		/*         Bank0 is the boot rom */

  1314. 		/*      else */

  1315. 		/*         Bank1 is the boot rom */

  1316. 		/*      endif */

  1317. /*		.bank[0] = { */

  1318. 		{

  1319. 			{

  1320. 				.probed = 0,

  1321. 				.pChip  = NULL,

  1322. 				.pBank  = NULL,

  1323. 				.bank_number = 0,

  1324. 				.base_address = FLASH_BANK_BASE_N,

  1325. 				.controller_address = 0x400e0A00,

  1326. 				.flash_wait_states = 6,	/* workaround silicon bug */

  1327. 				.present = 1,

  1328. 				.size_bytes = 64 * 1024,

  1329. 				.nsectors   = 4,

  1330. 				.sector_size = 16384,

  1331. 				.page_size   = 256,

  1332. 			},

  1333. 

  1334. /*		.bank[1] = { */

  1335. 			{

  1336. 				.present = 0,

  1337. 				.probed = 0,

  1338. 				.bank_number = 1,

  1339. 			},

  1340. 		},

  1341. 	},

  1342. 

  1343. 	/* Start at91sam3a series*/

  1344. 	/* System boots at address 0x0 */

  1345. 	/* gpnvm[1] = selects boot code */

  1346. 	/*     if gpnvm[1] == 0 */

  1347. 	/*         boot is via "SAMBA" (rom) */

  1348. 	/*     else */

  1349. 	/*         boot is via FLASH */

  1350. 	/*         Selection is via gpnvm[2] */

  1351. 	/*     endif */

  1352. 	/*  */

  1353. 	/* NOTE: banks 0 & 1 switch places */

  1354. 	/*     if gpnvm[2] == 0 */

  1355. 	/*         Bank0 is the boot rom */

  1356. 	/*      else */

  1357. 	/*         Bank1 is the boot rom */

  1358. 	/*      endif */

  1359. 

  1360. 	{

  1361. 		.chipid_cidr    = 0x283E0A60,

  1362. 		.name           = "at91sam3a8c",

  1363. 		.total_flash_size     = 512 * 1024,

  1364. 		.total_sram_size      = 96 * 1024,

  1365. 		.n_gpnvms       = 3,

  1366. 		.n_banks        = 2,

  1367. 		{

  1368. /*		.bank[0] = { */

  1369. 		  {

  1370. 			.probed = 0,

  1371. 			.pChip  = NULL,

  1372. 			.pBank  = NULL,

  1373. 			.bank_number = 0,

  1374. 			.base_address = FLASH_BANK0_BASE_AX,

  1375. 			.controller_address = 0x400e0a00,

  1376. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1377. 			.present = 1,

  1378. 			.size_bytes =  256 * 1024,

  1379. 			.nsectors   =  16,

  1380. 			.sector_size = 16384,

  1381. 			.page_size   = 256,

  1382. 		  },

  1383. /*		.bank[1] = { */

  1384. 		  {

  1385. 			.probed = 0,

  1386. 			.pChip  = NULL,

  1387. 			.pBank  = NULL,

  1388. 			.bank_number = 1,

  1389. 			.base_address = FLASH_BANK1_BASE_512K_AX,

  1390. 			.controller_address = 0x400e0c00,

  1391. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1392. 			.present = 1,

  1393. 			.size_bytes =  256 * 1024,

  1394. 			.nsectors   =  16,

  1395. 			.sector_size = 16384,

  1396. 			.page_size   = 256,

  1397. 

  1398. 		  },

  1399. 		},

  1400. 	},

  1401. 	{

  1402. 		.chipid_cidr    = 0x283B0960,

  1403. 		.name           = "at91sam3a4c",

  1404. 		.total_flash_size     = 256 * 1024,

  1405. 		.total_sram_size      = 64 * 1024,

  1406. 		.n_gpnvms       = 3,

  1407. 		.n_banks        = 2,

  1408. 		{

  1409. /*		.bank[0] = { */

  1410. 		  {

  1411. 			.probed = 0,

  1412. 			.pChip  = NULL,

  1413. 			.pBank  = NULL,

  1414. 			.bank_number = 0,

  1415. 			.base_address = FLASH_BANK0_BASE_AX,

  1416. 			.controller_address = 0x400e0a00,

  1417. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1418. 			.present = 1,

  1419. 			.size_bytes =  128 * 1024,

  1420. 			.nsectors   =  8,

  1421. 			.sector_size = 16384,

  1422. 			.page_size   = 256,

  1423. 		  },

  1424. /*		.bank[1] = { */

  1425. 		  {

  1426. 			.probed = 0,

  1427. 			.pChip  = NULL,

  1428. 			.pBank  = NULL,

  1429. 			.bank_number = 1,

  1430. 			.base_address = FLASH_BANK1_BASE_256K_AX,

  1431. 			.controller_address = 0x400e0c00,

  1432. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1433. 			.present = 1,

  1434. 			.size_bytes =  128 * 1024,

  1435. 			.nsectors   =  8,

  1436. 			.sector_size = 16384,

  1437. 			.page_size   = 256,

  1438. 

  1439. 		  },

  1440. 		},

  1441. 	},

  1442. 

  1443. 	/* Start at91sam3x* series */

  1444. 	/* System boots at address 0x0 */

  1445. 	/* gpnvm[1] = selects boot code */

  1446. 	/*     if gpnvm[1] == 0 */

  1447. 	/*         boot is via "SAMBA" (rom) */

  1448. 	/*     else */

  1449. 	/*         boot is via FLASH */

  1450. 	/*         Selection is via gpnvm[2] */

  1451. 	/*     endif */

  1452. 	/*  */

  1453. 	/* NOTE: banks 0 & 1 switch places */

  1454. 	/*     if gpnvm[2] == 0 */

  1455. 	/*         Bank0 is the boot rom */

  1456. 	/*      else */

  1457. 	/*         Bank1 is the boot rom */

  1458. 	/*      endif */

  1459. 	/*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/

  1460. 	{

  1461. 		.chipid_cidr    = 0x286E0A20,

  1462. 		.name           = "at91sam3x8h - ES",

  1463. 		.total_flash_size     = 512 * 1024,

  1464. 		.total_sram_size      = 96 * 1024,

  1465. 		.n_gpnvms       = 3,

  1466. 		.n_banks        = 2,

  1467. 		{

  1468. /*		.bank[0] = { */

  1469. 		  {

  1470. 			.probed = 0,

  1471. 			.pChip  = NULL,

  1472. 			.pBank  = NULL,

  1473. 			.bank_number = 0,

  1474. 			.base_address = FLASH_BANK0_BASE_AX,

  1475. 			.controller_address = 0x400e0a00,

  1476. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1477. 			.present = 1,

  1478. 			.size_bytes =  256 * 1024,

  1479. 			.nsectors   =  16,

  1480. 			.sector_size = 16384,

  1481. 			.page_size   = 256,

  1482. 		  },

  1483. /*		.bank[1] = { */

  1484. 		  {

  1485. 			.probed = 0,

  1486. 			.pChip  = NULL,

  1487. 			.pBank  = NULL,

  1488. 			.bank_number = 1,

  1489. 			.base_address = FLASH_BANK1_BASE_512K_AX,

  1490. 			.controller_address = 0x400e0c00,

  1491. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1492. 			.present = 1,

  1493. 			.size_bytes =  256 * 1024,

  1494. 			.nsectors   =  16,

  1495. 			.sector_size = 16384,

  1496. 			.page_size   = 256,

  1497. 

  1498. 		  },

  1499. 		},

  1500. 	},

  1501. 	/*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/

  1502. 	{

  1503. 		.chipid_cidr    = 0x286E0A60,

  1504. 		.name           = "at91sam3x8h",

  1505. 		.total_flash_size     = 512 * 1024,

  1506. 		.total_sram_size      = 96 * 1024,

  1507. 		.n_gpnvms       = 3,

  1508. 		.n_banks        = 2,

  1509. 		{

  1510. /*		.bank[0] = { */

  1511. 		  {

  1512. 			.probed = 0,

  1513. 			.pChip  = NULL,

  1514. 			.pBank  = NULL,

  1515. 			.bank_number = 0,

  1516. 			.base_address = FLASH_BANK0_BASE_AX,

  1517. 			.controller_address = 0x400e0a00,

  1518. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1519. 			.present = 1,

  1520. 			.size_bytes =  256 * 1024,

  1521. 			.nsectors   =  16,

  1522. 			.sector_size = 16384,

  1523. 			.page_size   = 256,

  1524. 		  },

  1525. /*		.bank[1] = { */

  1526. 		  {

  1527. 			.probed = 0,

  1528. 			.pChip  = NULL,

  1529. 			.pBank  = NULL,

  1530. 			.bank_number = 1,

  1531. 			.base_address = FLASH_BANK1_BASE_512K_AX,

  1532. 			.controller_address = 0x400e0c00,

  1533. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1534. 			.present = 1,

  1535. 			.size_bytes =  256 * 1024,

  1536. 			.nsectors   =  16,

  1537. 			.sector_size = 16384,

  1538. 			.page_size   = 256,

  1539. 

  1540. 		  },

  1541. 		},

  1542. 	},

  1543. 	{

  1544. 		.chipid_cidr    = 0x285E0A60,

  1545. 		.name           = "at91sam3x8e",

  1546. 		.total_flash_size     = 512 * 1024,

  1547. 		.total_sram_size      = 96 * 1024,

  1548. 		.n_gpnvms       = 3,

  1549. 		.n_banks        = 2,

  1550. 		{

  1551. /*		.bank[0] = { */

  1552. 		  {

  1553. 			.probed = 0,

  1554. 			.pChip  = NULL,

  1555. 			.pBank  = NULL,

  1556. 			.bank_number = 0,

  1557. 			.base_address = FLASH_BANK0_BASE_AX,

  1558. 			.controller_address = 0x400e0a00,

  1559. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1560. 			.present = 1,

  1561. 			.size_bytes =  256 * 1024,

  1562. 			.nsectors   =  16,

  1563. 			.sector_size = 16384,

  1564. 			.page_size   = 256,

  1565. 		  },

  1566. /*		.bank[1] = { */

  1567. 		  {

  1568. 			.probed = 0,

  1569. 			.pChip  = NULL,

  1570. 			.pBank  = NULL,

  1571. 			.bank_number = 1,

  1572. 			.base_address = FLASH_BANK1_BASE_512K_AX,

  1573. 			.controller_address = 0x400e0c00,

  1574. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1575. 			.present = 1,

  1576. 			.size_bytes =  256 * 1024,

  1577. 			.nsectors   =  16,

  1578. 			.sector_size = 16384,

  1579. 			.page_size   = 256,

  1580. 

  1581. 		  },

  1582. 		},

  1583. 	},

  1584. 	{

  1585. 		.chipid_cidr    = 0x284E0A60,

  1586. 		.name           = "at91sam3x8c",

  1587. 		.total_flash_size     = 512 * 1024,

  1588. 		.total_sram_size      = 96 * 1024,

  1589. 		.n_gpnvms       = 3,

  1590. 		.n_banks        = 2,

  1591. 		{

  1592. /*		.bank[0] = { */

  1593. 		  {

  1594. 			.probed = 0,

  1595. 			.pChip  = NULL,

  1596. 			.pBank  = NULL,

  1597. 			.bank_number = 0,

  1598. 			.base_address = FLASH_BANK0_BASE_AX,

  1599. 			.controller_address = 0x400e0a00,

  1600. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1601. 			.present = 1,

  1602. 			.size_bytes =  256 * 1024,

  1603. 			.nsectors   =  16,

  1604. 			.sector_size = 16384,

  1605. 			.page_size   = 256,

  1606. 		  },

  1607. /*		.bank[1] = { */

  1608. 		  {

  1609. 			.probed = 0,

  1610. 			.pChip  = NULL,

  1611. 			.pBank  = NULL,

  1612. 			.bank_number = 1,

  1613. 			.base_address = FLASH_BANK1_BASE_512K_AX ,

  1614. 			.controller_address = 0x400e0c00,

  1615. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1616. 			.present = 1,

  1617. 			.size_bytes =  256 * 1024,

  1618. 			.nsectors   =  16,

  1619. 			.sector_size = 16384,

  1620. 			.page_size   = 256,

  1621. 

  1622. 		  },

  1623. 		},

  1624. 	},

  1625. 	{

  1626. 		.chipid_cidr    = 0x285B0960,

  1627. 		.name           = "at91sam3x4e",

  1628. 		.total_flash_size     = 256 * 1024,

  1629. 		.total_sram_size      = 64 * 1024,

  1630. 		.n_gpnvms       = 3,

  1631. 		.n_banks        = 2,

  1632. 		{

  1633. /*		.bank[0] = { */

  1634. 		  {

  1635. 			.probed = 0,

  1636. 			.pChip  = NULL,

  1637. 			.pBank  = NULL,

  1638. 			.bank_number = 0,

  1639. 			.base_address = FLASH_BANK0_BASE_AX,

  1640. 			.controller_address = 0x400e0a00,

  1641. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1642. 			.present = 1,

  1643. 			.size_bytes =  128 * 1024,

  1644. 			.nsectors   =  8,

  1645. 			.sector_size = 16384,

  1646. 			.page_size   = 256,

  1647. 		  },

  1648. /*		.bank[1] = { */

  1649. 		  {

  1650. 			.probed = 0,

  1651. 			.pChip  = NULL,

  1652. 			.pBank  = NULL,

  1653. 			.bank_number = 1,

  1654. 			.base_address = FLASH_BANK1_BASE_256K_AX,

  1655. 			.controller_address = 0x400e0c00,

  1656. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1657. 			.present = 1,

  1658. 			.size_bytes =  128 * 1024,

  1659. 			.nsectors   =  8,

  1660. 			.sector_size = 16384,

  1661. 			.page_size   = 256,

  1662. 

  1663. 		  },

  1664. 		},

  1665. 	},

  1666. 	{

  1667. 		.chipid_cidr    = 0x284B0960,

  1668. 		.name           = "at91sam3x4c",

  1669. 		.total_flash_size     = 256 * 1024,

  1670. 		.total_sram_size      = 64 * 1024,

  1671. 		.n_gpnvms       = 3,

  1672. 		.n_banks        = 2,

  1673. 		{

  1674. /*		.bank[0] = { */

  1675. 		  {

  1676. 			.probed = 0,

  1677. 			.pChip  = NULL,

  1678. 			.pBank  = NULL,

  1679. 			.bank_number = 0,

  1680. 			.base_address = FLASH_BANK0_BASE_AX,

  1681. 			.controller_address = 0x400e0a00,

  1682. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1683. 			.present = 1,

  1684. 			.size_bytes =  128 * 1024,

  1685. 			.nsectors   =  8,

  1686. 			.sector_size = 16384,

  1687. 			.page_size   = 256,

  1688. 		  },

  1689. /*		.bank[1] = { */

  1690. 		  {

  1691. 			.probed = 0,

  1692. 			.pChip  = NULL,

  1693. 			.pBank  = NULL,

  1694. 			.bank_number = 1,

  1695. 			.base_address = FLASH_BANK1_BASE_256K_AX,

  1696. 			.controller_address = 0x400e0c00,

  1697. 			.flash_wait_states = 6,	/* workaround silicon bug */

  1698. 			.present = 1,

  1699. 			.size_bytes =  128 * 1024,

  1700. 			.nsectors   =  8,

  1701. 			.sector_size = 16384,

  1702. 			.page_size   = 256,

  1703. 

  1704. 		  },

  1705. 		},

  1706. 	},

  1707. 	/* terminate */

  1708. 	{

  1709. 		.chipid_cidr    = 0,

  1710. 		.name                   = NULL,

  1711. 	}

  1712. };

  1713. 

  1714. /* Globals above */

  1715. /***********************************************************************

  1716.  **********************************************************************

  1717.  **********************************************************************

  1718.  **********************************************************************

  1719.  **********************************************************************

  1720.  **********************************************************************/

  1721. /* *ATMEL* style code - from the SAM3 driver code */

  1722. 

  1723. /**

  1724.  * Get the current status of the EEFC and

  1725.  * the value of some status bits (LOCKE, PROGE).

  1726.  * @param pPrivate - info about the bank

  1727.  * @param v        - result goes here

  1728.  */

  1729. static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)

  1730. {

  1731. 	int r;

  1732. 	r = target_read_u32(pPrivate->pChip->target,

  1733. 			pPrivate->controller_address + offset_EFC_FSR,

  1734. 			v);

  1735. 	LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",

  1736. 		(unsigned int)(*v),

  1737. 		((unsigned int)((*v >> 2) & 1)),

  1738. 		((unsigned int)((*v >> 1) & 1)),

  1739. 		((unsigned int)((*v >> 0) & 1)));

  1740. 

  1741. 	return r;

  1742. }

  1743. 

  1744. /**

  1745.  * Get the result of the last executed command.

  1746.  * @param pPrivate - info about the bank

  1747.  * @param v        - result goes here

  1748.  */

  1749. static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)

  1750. {

  1751. 	int r;

  1752. 	uint32_t rv;

  1753. 	r = target_read_u32(pPrivate->pChip->target,

  1754. 			pPrivate->controller_address + offset_EFC_FRR,

  1755. 			&rv);

  1756. 	if (v)

  1757. 		*v = rv;

  1758. 	LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));

  1759. 	return r;

  1760. }

  1761. 

  1762. static int EFC_StartCommand(struct sam3_bank_private *pPrivate,

  1763. 	unsigned command, unsigned argument)

  1764. {

  1765. 	uint32_t n, v;

  1766. 	int r;

  1767. 	int retry;

  1768. 

  1769. 	retry = 0;

  1770. do_retry:

  1771. 

  1772. 	/* Check command & argument */

  1773. 	switch (command) {

  1774. 

  1775. 		case AT91C_EFC_FCMD_WP:

  1776. 		case AT91C_EFC_FCMD_WPL:

  1777. 		case AT91C_EFC_FCMD_EWP:

  1778. 		case AT91C_EFC_FCMD_EWPL:

  1779. 		/* case AT91C_EFC_FCMD_EPL: */

  1780. 		/* case AT91C_EFC_FCMD_EPA: */

  1781. 		case AT91C_EFC_FCMD_SLB:

  1782. 		case AT91C_EFC_FCMD_CLB:

  1783. 			n = (pPrivate->size_bytes / pPrivate->page_size);

  1784. 			if (argument >= n)

  1785. 				LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));

  1786. 			break;

  1787. 

  1788. 		case AT91C_EFC_FCMD_SFB:

  1789. 		case AT91C_EFC_FCMD_CFB:

  1790. 			if (argument >= pPrivate->pChip->details.n_gpnvms) {

  1791. 				LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",

  1792. 						pPrivate->pChip->details.n_gpnvms);

  1793. 			}

  1794. 			break;

  1795. 

  1796. 		case AT91C_EFC_FCMD_GETD:

  1797. 		case AT91C_EFC_FCMD_EA:

  1798. 		case AT91C_EFC_FCMD_GLB:

  1799. 		case AT91C_EFC_FCMD_GFB:

  1800. 		case AT91C_EFC_FCMD_STUI:

  1801. 		case AT91C_EFC_FCMD_SPUI:

  1802. 			if (argument != 0)

  1803. 				LOG_ERROR("Argument is meaningless for cmd: %d", command);

  1804. 			break;

  1805. 		default:

  1806. 			LOG_ERROR("Unknown command %d", command);

  1807. 			break;

  1808. 	}

  1809. 

  1810. 	if (command == AT91C_EFC_FCMD_SPUI) {

  1811. 		/* this is a very special situation. */

  1812. 		/* Situation (1) - error/retry - see below */

  1813. 		/*      And we are being called recursively */

  1814. 		/* Situation (2) - normal, finished reading unique id */

  1815. 	} else {

  1816. 		/* it should be "ready" */

  1817. 		EFC_GetStatus(pPrivate, &v);

  1818. 		if (v & 1) {

  1819. 			/* then it is ready */

  1820. 			/* we go on */

  1821. 		} else {

  1822. 			if (retry) {

  1823. 				/* we have done this before */

  1824. 				/* the controller is not responding. */

  1825. 				LOG_ERROR("flash controller(%d) is not ready! Error",

  1826. 					pPrivate->bank_number);

  1827. 				return ERROR_FAIL;

  1828. 			} else {

  1829. 				retry++;

  1830. 				LOG_ERROR("Flash controller(%d) is not ready, attempting reset",

  1831. 					pPrivate->bank_number);

  1832. 				/* we do that by issuing the *STOP* command */

  1833. 				EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);

  1834. 				/* above is recursive, and further recursion is blocked by */

  1835. 				/* if (command == AT91C_EFC_FCMD_SPUI) above */

  1836. 				goto do_retry;

  1837. 			}

  1838. 		}

  1839. 	}

  1840. 

  1841. 	v = (0x5A << 24) | (argument << 8) | command;

  1842. 	LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));

  1843. 	r = target_write_u32(pPrivate->pBank->target,

  1844. 			pPrivate->controller_address + offset_EFC_FCR, v);

  1845. 	if (r != ERROR_OK)

  1846. 		LOG_DEBUG("Error Write failed");

  1847. 	return r;

  1848. }

  1849. 

  1850. /**

  1851.  * Performs the given command and wait until its completion (or an error).

  1852.  * @param pPrivate - info about the bank

  1853.  * @param command  - Command to perform.

  1854.  * @param argument - Optional command argument.

  1855.  * @param status   - put command status bits here

  1856.  */

  1857. static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,

  1858. 	unsigned command,

  1859. 	unsigned argument,

  1860. 	uint32_t *status)

  1861. {

  1862. 

  1863. 	int r;

  1864. 	uint32_t v;

  1865. 	long long ms_now, ms_end;

  1866. 

  1867. 	/* default */

  1868. 	if (status)

  1869. 		*status = 0;

  1870. 

  1871. 	r = EFC_StartCommand(pPrivate, command, argument);

  1872. 	if (r != ERROR_OK)

  1873. 		return r;

  1874. 

  1875. 	ms_end = 500 + timeval_ms();

  1876. 

  1877. 	do {

  1878. 		r = EFC_GetStatus(pPrivate, &v);

  1879. 		if (r != ERROR_OK)

  1880. 			return r;

  1881. 		ms_now = timeval_ms();

  1882. 		if (ms_now > ms_end) {

  1883. 			/* error */

  1884. 			LOG_ERROR("Command timeout");

  1885. 			return ERROR_FAIL;

  1886. 		}

  1887. 	} while ((v & 1) == 0);

  1888. 

  1889. 	/* error bits.. */

  1890. 	if (status)

  1891. 		*status = (v & 0x6);

  1892. 	return ERROR_OK;

  1893. 

  1894. }

  1895. 

  1896. /**

  1897.  * Read the unique ID.

  1898.  * @param pPrivate - info about the bank

  1899.  * The unique ID is stored in the 'pPrivate' structure.

  1900.  */

  1901. static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)

  1902. {

  1903. 	int r;

  1904. 	uint32_t v;

  1905. 	int x;

  1906. 	/* assume 0 */

  1907. 	pPrivate->pChip->cfg.unique_id[0] = 0;

  1908. 	pPrivate->pChip->cfg.unique_id[1] = 0;

  1909. 	pPrivate->pChip->cfg.unique_id[2] = 0;

  1910. 	pPrivate->pChip->cfg.unique_id[3] = 0;

  1911. 

  1912. 	LOG_DEBUG("Begin");

  1913. 	r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);

  1914. 	if (r < 0)

  1915. 		return r;

  1916. 

  1917. 	for (x = 0; x < 4; x++) {

  1918. 		r = target_read_u32(pPrivate->pChip->target,

  1919. 				pPrivate->pBank->base + (x * 4),

  1920. 				&v);

  1921. 		if (r < 0)

  1922. 			return r;

  1923. 		pPrivate->pChip->cfg.unique_id[x] = v;

  1924. 	}

  1925. 

  1926. 	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);

  1927. 	LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",

  1928. 		r,

  1929. 		(unsigned int)(pPrivate->pChip->cfg.unique_id[0]),

  1930. 		(unsigned int)(pPrivate->pChip->cfg.unique_id[1]),

  1931. 		(unsigned int)(pPrivate->pChip->cfg.unique_id[2]),

  1932. 		(unsigned int)(pPrivate->pChip->cfg.unique_id[3]));

  1933. 	return r;

  1934. 

  1935. }

  1936. 

  1937. /**

  1938.  * Erases the entire flash.

  1939.  * @param pPrivate - the info about the bank.

  1940.  */

  1941. static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)

  1942. {

  1943. 	LOG_DEBUG("Here");

  1944. 	return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);

  1945. }

  1946. 

  1947. /**

  1948.  * Gets current GPNVM state.

  1949.  * @param pPrivate - info about the bank.

  1950.  * @param gpnvm    -  GPNVM bit index.

  1951.  * @param puthere  - result stored here.

  1952.  */

  1953. /* ------------------------------------------------------------------------------ */

  1954. static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)

  1955. {

  1956. 	uint32_t v;

  1957. 	int r;

  1958. 

  1959. 	LOG_DEBUG("Here");

  1960. 	if (pPrivate->bank_number != 0) {

  1961. 		LOG_ERROR("GPNVM only works with Bank0");

  1962. 		return ERROR_FAIL;

  1963. 	}

  1964. 

  1965. 	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {

  1966. 		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",

  1967. 			gpnvm, pPrivate->pChip->details.n_gpnvms);

  1968. 		return ERROR_FAIL;

  1969. 	}

  1970. 

  1971. 	/* Get GPNVMs status */

  1972. 	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);

  1973. 	if (r != ERROR_OK) {

  1974. 		LOG_ERROR("Failed");

  1975. 		return r;

  1976. 	}

  1977. 

  1978. 	r = EFC_GetResult(pPrivate, &v);

  1979. 

  1980. 	if (puthere) {

  1981. 		/* Check if GPNVM is set */

  1982. 		/* get the bit and make it a 0/1 */

  1983. 		*puthere = (v >> gpnvm) & 1;

  1984. 	}

  1985. 

  1986. 	return r;

  1987. }

  1988. 

  1989. /**

  1990.  * Clears the selected GPNVM bit.

  1991.  * @param pPrivate info about the bank

  1992.  * @param gpnvm GPNVM index.

  1993.  * @returns 0 if successful; otherwise returns an error code.

  1994.  */

  1995. static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)

  1996. {

  1997. 	int r;

  1998. 	unsigned v;

  1999. 

  2000. 	LOG_DEBUG("Here");

  2001. 	if (pPrivate->bank_number != 0) {

  2002. 		LOG_ERROR("GPNVM only works with Bank0");

  2003. 		return ERROR_FAIL;

  2004. 	}

  2005. 

  2006. 	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {

  2007. 		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",

  2008. 			gpnvm, pPrivate->pChip->details.n_gpnvms);

  2009. 		return ERROR_FAIL;

  2010. 	}

  2011. 

  2012. 	r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);

  2013. 	if (r != ERROR_OK) {

  2014. 		LOG_DEBUG("Failed: %d", r);

  2015. 		return r;

  2016. 	}

  2017. 	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);

  2018. 	LOG_DEBUG("End: %d", r);

  2019. 	return r;

  2020. }

  2021. 

  2022. /**

  2023.  * Sets the selected GPNVM bit.

  2024.  * @param pPrivate info about the bank

  2025.  * @param gpnvm GPNVM index.

  2026.  */

  2027. static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)

  2028. {

  2029. 	int r;

  2030. 	unsigned v;

  2031. 

  2032. 	if (pPrivate->bank_number != 0) {

  2033. 		LOG_ERROR("GPNVM only works with Bank0");

  2034. 		return ERROR_FAIL;

  2035. 	}

  2036. 

  2037. 	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {

  2038. 		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",

  2039. 			gpnvm, pPrivate->pChip->details.n_gpnvms);

  2040. 		return ERROR_FAIL;

  2041. 	}

  2042. 

  2043. 	r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);

  2044. 	if (r != ERROR_OK)

  2045. 		return r;

  2046. 	if (v) {

  2047. 		/* already set */

  2048. 		r = ERROR_OK;

  2049. 	} else {

  2050. 		/* set it */

  2051. 		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);

  2052. 	}

  2053. 	return r;

  2054. }

  2055. 

  2056. /**

  2057.  * Returns a bit field (at most 64) of locked regions within a page.

  2058.  * @param pPrivate info about the bank

  2059.  * @param v where to store locked bits

  2060.  */

  2061. static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)

  2062. {

  2063. 	int r;

  2064. 	LOG_DEBUG("Here");

  2065. 	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);

  2066. 	if (r == ERROR_OK)

  2067. 		r = EFC_GetResult(pPrivate, v);

  2068. 	LOG_DEBUG("End: %d", r);

  2069. 	return r;

  2070. }

  2071. 

  2072. /**

  2073.  * Unlocks all the regions in the given address range.

  2074.  * @param pPrivate info about the bank

  2075.  * @param start_sector first sector to unlock

  2076.  * @param end_sector last (inclusive) to unlock

  2077.  */

  2078. 

  2079. static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,

  2080. 	unsigned start_sector,

  2081. 	unsigned end_sector)

  2082. {

  2083. 	int r;

  2084. 	uint32_t status;

  2085. 	uint32_t pg;

  2086. 	uint32_t pages_per_sector;

  2087. 

  2088. 	pages_per_sector = pPrivate->sector_size / pPrivate->page_size;

  2089. 

  2090. 	/* Unlock all pages */

  2091. 	while (start_sector <= end_sector) {

  2092. 		pg = start_sector * pages_per_sector;

  2093. 

  2094. 		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);

  2095. 		if (r != ERROR_OK)

  2096. 			return r;

  2097. 		start_sector++;

  2098. 	}

  2099. 

  2100. 	return ERROR_OK;

  2101. }

  2102. 

  2103. /**

  2104.  * Locks regions

  2105.  * @param pPrivate - info about the bank

  2106.  * @param start_sector - first sector to lock

  2107.  * @param end_sector   - last sector (inclusive) to lock

  2108.  */

  2109. static int FLASHD_Lock(struct sam3_bank_private *pPrivate,

  2110. 	unsigned start_sector,

  2111. 	unsigned end_sector)

  2112. {

  2113. 	uint32_t status;

  2114. 	uint32_t pg;

  2115. 	uint32_t pages_per_sector;

  2116. 	int r;

  2117. 

  2118. 	pages_per_sector = pPrivate->sector_size / pPrivate->page_size;

  2119. 

  2120. 	/* Lock all pages */

  2121. 	while (start_sector <= end_sector) {

  2122. 		pg = start_sector * pages_per_sector;

  2123. 

  2124. 		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);

  2125. 		if (r != ERROR_OK)

  2126. 			return r;

  2127. 		start_sector++;

  2128. 	}

  2129. 	return ERROR_OK;

  2130. }

  2131. 

  2132. /****** END SAM3 CODE ********/

  2133. 

  2134. /* begin helpful debug code */

  2135. /* print the fieldname, the field value, in dec & hex, and return field value */

  2136. static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,

  2137. 	const char *regname,

  2138. 	uint32_t value,

  2139. 	unsigned shift,

  2140. 	unsigned width)

  2141. {

  2142. 	uint32_t v;

  2143. 	int hwidth, dwidth;

  2144. 

  2145. 

  2146. 	/* extract the field */

  2147. 	v = value >> shift;

  2148. 	v = v & ((1 << width)-1);

  2149. 	if (width <= 16) {

  2150. 		hwidth = 4;

  2151. 		dwidth = 5;

  2152. 	} else {

  2153. 		hwidth = 8;

  2154. 		dwidth = 12;

  2155. 	}

  2156. 

  2157. 	/* show the basics */

  2158. 	LOG_USER_N("\t%*s: %*d [0x%0*x] ",

  2159. 		REG_NAME_WIDTH, regname,

  2160. 		dwidth, v,

  2161. 		hwidth, v);

  2162. 	return v;

  2163. }

  2164. 

  2165. static const char _unknown[] = "unknown";

  2166. static const char *const eproc_names[] = {

  2167. 	_unknown,					/* 0 */

  2168. 	"arm946es",					/* 1 */

  2169. 	"arm7tdmi",					/* 2 */

  2170. 	"cortex-m3",				/* 3 */

  2171. 	"arm920t",					/* 4 */

  2172. 	"arm926ejs",				/* 5 */

  2173. 	_unknown,					/* 6 */

  2174. 	_unknown,					/* 7 */

  2175. 	_unknown,					/* 8 */

  2176. 	_unknown,					/* 9 */

  2177. 	_unknown,					/* 10 */

  2178. 	_unknown,					/* 11 */

  2179. 	_unknown,					/* 12 */

  2180. 	_unknown,					/* 13 */

  2181. 	_unknown,					/* 14 */

  2182. 	_unknown,					/* 15 */

  2183. };

  2184. 

  2185. #define nvpsize2 nvpsize		/* these two tables are identical */

  2186. static const char *const nvpsize[] = {

  2187. 	"none",						/*  0 */

  2188. 	"8K bytes",					/*  1 */

  2189. 	"16K bytes",				/*  2 */

  2190. 	"32K bytes",				/*  3 */

  2191. 	_unknown,					/*  4 */

  2192. 	"64K bytes",				/*  5 */

  2193. 	_unknown,					/*  6 */

  2194. 	"128K bytes",				/*  7 */

  2195. 	_unknown,					/*  8 */

  2196. 	"256K bytes",				/*  9 */

  2197. 	"512K bytes",				/* 10 */

  2198. 	_unknown,					/* 11 */

  2199. 	"1024K bytes",				/* 12 */

  2200. 	_unknown,					/* 13 */

  2201. 	"2048K bytes",				/* 14 */

  2202. 	_unknown,					/* 15 */

  2203. };

  2204. 

  2205. static const char *const sramsize[] = {

  2206. 	"48K Bytes",				/*  0 */

  2207. 	"1K Bytes",					/*  1 */

  2208. 	"2K Bytes",					/*  2 */

  2209. 	"6K Bytes",					/*  3 */

  2210. 	"112K Bytes",				/*  4 */

  2211. 	"4K Bytes",					/*  5 */

  2212. 	"80K Bytes",				/*  6 */

  2213. 	"160K Bytes",				/*  7 */

  2214. 	"8K Bytes",					/*  8 */

  2215. 	"16K Bytes",				/*  9 */

  2216. 	"32K Bytes",				/* 10 */

  2217. 	"64K Bytes",				/* 11 */

  2218. 	"128K Bytes",				/* 12 */

  2219. 	"256K Bytes",				/* 13 */

  2220. 	"96K Bytes",				/* 14 */

  2221. 	"512K Bytes",				/* 15 */

  2222. 

  2223. };

  2224. 

  2225. static const struct archnames { unsigned value; const char *name; } archnames[] = {

  2226. 	{ 0x19,  "AT91SAM9xx Series"                                            },

  2227. 	{ 0x29,  "AT91SAM9XExx Series"                                          },

  2228. 	{ 0x34,  "AT91x34 Series"                                                       },

  2229. 	{ 0x37,  "CAP7 Series"                                                          },

  2230. 	{ 0x39,  "CAP9 Series"                                                          },

  2231. 	{ 0x3B,  "CAP11 Series"                                                         },

  2232. 	{ 0x40,  "AT91x40 Series"                                                       },

  2233. 	{ 0x42,  "AT91x42 Series"                                                       },

  2234. 	{ 0x55,  "AT91x55 Series"                                                       },

  2235. 	{ 0x60,  "AT91SAM7Axx Series"                                           },

  2236. 	{ 0x61,  "AT91SAM7AQxx Series"                                          },

  2237. 	{ 0x63,  "AT91x63 Series"                                                       },

  2238. 	{ 0x70,  "AT91SAM7Sxx Series"                                           },

  2239. 	{ 0x71,  "AT91SAM7XCxx Series"                                          },

  2240. 	{ 0x72,  "AT91SAM7SExx Series"                                          },

  2241. 	{ 0x73,  "AT91SAM7Lxx Series"                                           },

  2242. 	{ 0x75,  "AT91SAM7Xxx Series"                                           },

  2243. 	{ 0x76,  "AT91SAM7SLxx Series"                                          },

  2244. 	{ 0x80,  "ATSAM3UxC Series (100-pin version)"           },

  2245. 	{ 0x81,  "ATSAM3UxE Series (144-pin version)"           },

  2246. 	{ 0x83,  "ATSAM3AxC Series (100-pin version)"           },

  2247. 	{ 0x84,  "ATSAM3XxC Series (100-pin version)"           },

  2248. 	{ 0x85,  "ATSAM3XxE Series (144-pin version)"           },

  2249. 	{ 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },

  2250. 	{ 0x88,  "ATSAM3SxA Series (48-pin version)"            },

  2251. 	{ 0x89,  "ATSAM3SxB Series (64-pin version)"            },

  2252. 	{ 0x8A,  "ATSAM3SxC Series (100-pin version)"           },

  2253. 	{ 0x92,  "AT91x92 Series"                                                       },

  2254. 	{ 0x93,  "ATSAM3NxA Series (48-pin version)"            },

  2255. 	{ 0x94,  "ATSAM3NxB Series (64-pin version)"            },

  2256. 	{ 0x95,  "ATSAM3NxC Series (100-pin version)"           },

  2257. 	{ 0x98,  "ATSAM3SDxA Series (48-pin version)"           },

  2258. 	{ 0x99,  "ATSAM3SDxB Series (64-pin version)"           },

  2259. 	{ 0x9A,  "ATSAM3SDxC Series (100-pin version)"          },

  2260. 	{ 0xA5,  "ATSAM5A"                                                              },

  2261. 	{ 0xF0,  "AT75Cxx Series"                                                       },

  2262. 	{ -1, NULL },

  2263. };

  2264. 

  2265. static const char *const nvptype[] = {

  2266. 	"rom",	/* 0 */

  2267. 	"romless or onchip flash",	/* 1 */

  2268. 	"embedded flash memory",/* 2 */

  2269. 	"rom(nvpsiz) + embedded flash (nvpsiz2)",	/* 3 */

  2270. 	"sram emulating flash",	/* 4 */

  2271. 	_unknown,	/* 5 */

  2272. 	_unknown,	/* 6 */

  2273. 	_unknown,	/* 7 */

  2274. };

  2275. 

  2276. static const char *_yes_or_no(uint32_t v)

  2277. {

  2278. 	if (v)

  2279. 		return "YES";

  2280. 	else

  2281. 		return "NO";

  2282. }

  2283. 

  2284. static const char *const _rc_freq[] = {

  2285. 	"4 MHz", "8 MHz", "12 MHz", "reserved"

  2286. };

  2287. 

  2288. static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)

  2289. {

  2290. 	uint32_t v;

  2291. 	uint32_t rcen;

  2292. 

  2293. 	v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);

  2294. 	LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));

  2295. 	v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);

  2296. 	LOG_USER("(main osc bypass: %s)", _yes_or_no(v));

  2297. 	rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);

  2298. 	LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));

  2299. 	v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);

  2300. 	LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);

  2301. 

  2302. 	pChip->cfg.rc_freq = 0;

  2303. 	if (rcen) {

  2304. 		switch (v) {

  2305. 			default:

  2306. 				pChip->cfg.rc_freq = 0;

  2307. 				break;

  2308. 			case 0:

  2309. 				pChip->cfg.rc_freq = 4 * 1000 * 1000;

  2310. 				break;

  2311. 			case 1:

  2312. 				pChip->cfg.rc_freq = 8 * 1000 * 1000;

  2313. 				break;

  2314. 			case 2:

  2315. 				pChip->cfg.rc_freq = 12 * 1000 * 1000;

  2316. 				break;

  2317. 		}

  2318. 	}

  2319. 

  2320. 	v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);

  2321. 	LOG_USER("(startup clks, time= %f uSecs)",

  2322. 		((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));

  2323. 	v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);

  2324. 	LOG_USER("(mainosc source: %s)",

  2325. 		v ? "external xtal" : "internal RC");

  2326. 

  2327. 	v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);

  2328. 	LOG_USER("(clock failure enabled: %s)",

  2329. 		_yes_or_no(v));

  2330. }

  2331. 

  2332. static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)

  2333. {

  2334. 	int x;

  2335. 	uint32_t v;

  2336. 	const char *cp;

  2337. 

  2338. 	sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);

  2339. 	LOG_USER_N("\n");

  2340. 

  2341. 	v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);

  2342. 	LOG_USER("%s", eproc_names[v]);

  2343. 

  2344. 	v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);

  2345. 	LOG_USER("%s", nvpsize[v]);

  2346. 

  2347. 	v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);

  2348. 	LOG_USER("%s", nvpsize2[v]);

  2349. 

  2350. 	v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);

  2351. 	LOG_USER("%s", sramsize[v]);

  2352. 

  2353. 	v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);

  2354. 	cp = _unknown;

  2355. 	for (x = 0; archnames[x].name; x++) {

  2356. 		if (v == archnames[x].value) {

  2357. 			cp = archnames[x].name;

  2358. 			break;

  2359. 		}

  2360. 	}

  2361. 

  2362. 	LOG_USER("%s", cp);

  2363. 

  2364. 	v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);

  2365. 	LOG_USER("%s", nvptype[v]);

  2366. 

  2367. 	v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);

  2368. 	LOG_USER("(exists: %s)", _yes_or_no(v));

  2369. }

  2370. 

  2371. static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)

  2372. {

  2373. 	uint32_t v;

  2374. 

  2375. 	v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);

  2376. 	LOG_USER("(main ready: %s)", _yes_or_no(v));

  2377. 

  2378. 	v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);

  2379. 

  2380. 	v = (v * pChip->cfg.slow_freq) / 16;

  2381. 	pChip->cfg.mainosc_freq = v;

  2382. 

  2383. 	LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",

  2384. 		_tomhz(v),

  2385. 		pChip->cfg.slow_freq / 1000,

  2386. 		pChip->cfg.slow_freq % 1000);

  2387. }

  2388. 

  2389. static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)

  2390. {

  2391. 	uint32_t mula, diva;

  2392. 

  2393. 	diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);

  2394. 	LOG_USER_N("\n");

  2395. 	mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);

  2396. 	LOG_USER_N("\n");

  2397. 	pChip->cfg.plla_freq = 0;

  2398. 	if (mula == 0)

  2399. 		LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");

  2400. 	else if (diva == 0)

  2401. 		LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");

  2402. 	else if (diva >= 1) {

  2403. 		pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);

  2404. 		LOG_USER("\tPLLA Freq: %3.03f MHz",

  2405. 			_tomhz(pChip->cfg.plla_freq));

  2406. 	}

  2407. }

  2408. 

  2409. static void sam3_explain_mckr(struct sam3_chip *pChip)

  2410. {

  2411. 	uint32_t css, pres, fin = 0;

  2412. 	int pdiv = 0;

  2413. 	const char *cp = NULL;

  2414. 

  2415. 	css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);

  2416. 	switch (css & 3) {

  2417. 		case 0:

  2418. 			fin = pChip->cfg.slow_freq;

  2419. 			cp = "slowclk";

  2420. 			break;

  2421. 		case 1:

  2422. 			fin = pChip->cfg.mainosc_freq;

  2423. 			cp  = "mainosc";

  2424. 			break;

  2425. 		case 2:

  2426. 			fin = pChip->cfg.plla_freq;

  2427. 			cp  = "plla";

  2428. 			break;

  2429. 		case 3:

  2430. 			if (pChip->cfg.CKGR_UCKR & (1 << 16)) {

  2431. 				fin = 480 * 1000 * 1000;

  2432. 				cp = "upll";

  2433. 			} else {

  2434. 				fin = 0;

  2435. 				cp  = "upll (*ERROR* UPLL is disabled)";

  2436. 			}

  2437. 			break;

  2438. 		default:

  2439. 			assert(0);

  2440. 			break;

  2441. 	}

  2442. 

  2443. 	LOG_USER("%s (%3.03f Mhz)",

  2444. 		cp,

  2445. 		_tomhz(fin));

  2446. 	pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);

  2447. 	switch (pres & 0x07) {

  2448. 		case 0:

  2449. 			pdiv = 1;

  2450. 			cp = "selected clock";

  2451. 			break;

  2452. 		case 1:

  2453. 			pdiv = 2;

  2454. 			cp = "clock/2";

  2455. 			break;

  2456. 		case 2:

  2457. 			pdiv = 4;

  2458. 			cp = "clock/4";

  2459. 			break;

  2460. 		case 3:

  2461. 			pdiv = 8;

  2462. 			cp = "clock/8";

  2463. 			break;

  2464. 		case 4:

  2465. 			pdiv = 16;

  2466. 			cp = "clock/16";

  2467. 			break;

  2468. 		case 5:

  2469. 			pdiv = 32;

  2470. 			cp = "clock/32";

  2471. 			break;

  2472. 		case 6:

  2473. 			pdiv = 64;

  2474. 			cp = "clock/64";

  2475. 			break;

  2476. 		case 7:

  2477. 			pdiv = 6;

  2478. 			cp = "clock/6";

  2479. 			break;

  2480. 		default:

  2481. 			assert(0);

  2482. 			break;

  2483. 	}

  2484. 	LOG_USER("(%s)", cp);

  2485. 	fin = fin / pdiv;

  2486. 	/* sam3 has a *SINGLE* clock - */

  2487. 	/* other at91 series parts have divisors for these. */

  2488. 	pChip->cfg.cpu_freq = fin;

  2489. 	pChip->cfg.mclk_freq = fin;

  2490. 	pChip->cfg.fclk_freq = fin;

  2491. 	LOG_USER("\t\tResult CPU Freq: %3.03f",

  2492. 		_tomhz(fin));

  2493. }

  2494. 

  2495. #if 0

  2496. static struct sam3_chip *target2sam3(struct target *pTarget)

  2497. {

  2498. 	struct sam3_chip *pChip;

  2499. 

  2500. 	if (pTarget == NULL)

  2501. 		return NULL;

  2502. 

  2503. 	pChip = all_sam3_chips;

  2504. 	while (pChip) {

  2505. 		if (pChip->target == pTarget)

  2506. 			break;	/* return below */

  2507. 		else

  2508. 			pChip = pChip->next;

  2509. 	}

  2510. 	return pChip;

  2511. }

  2512. #endif

  2513. 

  2514. static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)

  2515. {

  2516. 	/* this function exists to help */

  2517. 	/* keep funky offsetof() errors */

  2518. 	/* and casting from causing bugs */

  2519. 

  2520. 	/* By using prototypes - we can detect what would */

  2521. 	/* be casting errors. */

  2522. 

  2523. 	return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);

  2524. }

  2525. 

  2526. 

  2527. #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \

  2528. 						  struct sam3_cfg, \

  2529. 						  NAME), # NAME, FUNC }

  2530. static const struct sam3_reg_list sam3_all_regs[] = {

  2531. 	SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),

  2532. 	SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),

  2533. 	SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),

  2534. 	SAM3_ENTRY(CKGR_UCKR, NULL),

  2535. 	SAM3_ENTRY(PMC_FSMR, NULL),

  2536. 	SAM3_ENTRY(PMC_FSPR, NULL),

  2537. 	SAM3_ENTRY(PMC_IMR, NULL),

  2538. 	SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),

  2539. 	SAM3_ENTRY(PMC_PCK0, NULL),

  2540. 	SAM3_ENTRY(PMC_PCK1, NULL),

  2541. 	SAM3_ENTRY(PMC_PCK2, NULL),

  2542. 	SAM3_ENTRY(PMC_PCSR, NULL),

  2543. 	SAM3_ENTRY(PMC_SCSR, NULL),

  2544. 	SAM3_ENTRY(PMC_SR, NULL),

  2545. 	SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),

  2546. 	SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),

  2547. 	SAM3_ENTRY(CHIPID_EXID, NULL),

  2548. 	SAM3_ENTRY(CHIPID_EXID2, NULL),

  2549. 	/* TERMINATE THE LIST */

  2550. 	{ .name = NULL }

  2551. };

  2552. #undef SAM3_ENTRY

  2553. 

  2554. static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)

  2555. {

  2556. 	return (struct sam3_bank_private *)(bank->driver_priv);

  2557. }

  2558. 

  2559. /**

  2560.  * Given a pointer to where it goes in the structure,

  2561.  * determine the register name, address from the all registers table.

  2562.  */

  2563. static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)

  2564. {

  2565. 	const struct sam3_reg_list *pReg;

  2566. 

  2567. 	pReg = &(sam3_all_regs[0]);

  2568. 	while (pReg->name) {

  2569. 		uint32_t *pPossible;

  2570. 

  2571. 		/* calculate where this one go.. */

  2572. 		/* it is "possibly" this register. */

  2573. 

  2574. 		pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));

  2575. 

  2576. 		/* well? Is it this register */

  2577. 		if (pPossible == goes_here) {

  2578. 			/* Jump for joy! */

  2579. 			return pReg;

  2580. 		}

  2581. 

  2582. 		/* next... */

  2583. 		pReg++;

  2584. 	}

  2585. 	/* This is *TOTAL*PANIC* - we are totally screwed. */

  2586. 	LOG_ERROR("INVALID SAM3 REGISTER");

  2587. 	return NULL;

  2588. }

  2589. 

  2590. static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)

  2591. {

  2592. 	const struct sam3_reg_list *pReg;

  2593. 	int r;

  2594. 

  2595. 	pReg = sam3_GetReg(pChip, goes_here);

  2596. 	if (!pReg)

  2597. 		return ERROR_FAIL;

  2598. 

  2599. 	r = target_read_u32(pChip->target, pReg->address, goes_here);

  2600. 	if (r != ERROR_OK) {

  2601. 		LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",

  2602. 			pReg->name, (unsigned)(pReg->address), r);

  2603. 	}

  2604. 	return r;

  2605. }

  2606. 

  2607. static int sam3_ReadAllRegs(struct sam3_chip *pChip)

  2608. {

  2609. 	int r;

  2610. 	const struct sam3_reg_list *pReg;

  2611. 

  2612. 	pReg = &(sam3_all_regs[0]);

  2613. 	while (pReg->name) {

  2614. 		r = sam3_ReadThisReg(pChip,

  2615. 				sam3_get_reg_ptr(&(pChip->cfg), pReg));

  2616. 		if (r != ERROR_OK) {

  2617. 			LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",

  2618. 				pReg->name, ((unsigned)(pReg->address)), r);

  2619. 			return r;

  2620. 		}

  2621. 		pReg++;

  2622. 	}

  2623. 

  2624. 	/* Chip identification register

  2625. 	*

  2626. 	* Unfortunately, the chip identification register is not at

  2627. 	* a constant address across all of the SAM3 series'. As a

  2628. 	* consequence, a simple heuristic is used to find where it's

  2629. 	* at...

  2630. 	*

  2631. 	* If the contents at the first address is zero, then we know

  2632. 	* that the second address is where the chip id register is.

  2633. 	* We can deduce this because for those SAM's that have the

  2634. 	* chip id @ 0x400e0940, the first address, 0x400e0740, is

  2635. 	* located in the memory map of the Power Management Controller

  2636. 	* (PMC). Furthermore, the address is not used by the PMC.

  2637. 	* So when read, the memory controller returns zero.*/

  2638. 	if (pChip->cfg.CHIPID_CIDR == 0)	{

  2639. 		/*Put the correct CIDR and EXID values in the pChip structure */

  2640. 		pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;

  2641. 		pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;

  2642. 	}

  2643. 	return ERROR_OK;

  2644. }

  2645. 

  2646. static int sam3_GetInfo(struct sam3_chip *pChip)

  2647. {

  2648. 	const struct sam3_reg_list *pReg;

  2649. 	uint32_t regval;

  2650. 

  2651. 	pReg = &(sam3_all_regs[0]);

  2652. 	while (pReg->name) {

  2653. 		/* display all regs */

  2654. 		LOG_DEBUG("Start: %s", pReg->name);

  2655. 		regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);

  2656. 		LOG_USER("%*s: [0x%08x] -> 0x%08x",

  2657. 			REG_NAME_WIDTH,

  2658. 			pReg->name,

  2659. 			pReg->address,

  2660. 			regval);

  2661. 		if (pReg->explain_func)

  2662. 			(*(pReg->explain_func))(pChip);

  2663. 		LOG_DEBUG("End: %s", pReg->name);

  2664. 		pReg++;

  2665. 	}

  2666. 	LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));

  2667. 	LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));

  2668. 	LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));

  2669. 	LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));

  2670. 	LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));

  2671. 

  2672. 	LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",

  2673. 		pChip->cfg.unique_id[0],

  2674. 		pChip->cfg.unique_id[1],

  2675. 		pChip->cfg.unique_id[2],

  2676. 		pChip->cfg.unique_id[3]);

  2677. 

  2678. 	return ERROR_OK;

  2679. }

  2680. 

  2681. static int sam3_erase_check(struct flash_bank *bank)

  2682. {

  2683. 	int x;

  2684. 

  2685. 	LOG_DEBUG("Here");

  2686. 	if (bank->target->state != TARGET_HALTED) {

  2687. 		LOG_ERROR("Target not halted");

  2688. 		return ERROR_TARGET_NOT_HALTED;

  2689. 	}

  2690. 	if (0 == bank->num_sectors) {

  2691. 		LOG_ERROR("Target: not supported/not probed");

  2692. 		return ERROR_FAIL;

  2693. 	}

  2694. 

  2695. 	LOG_INFO("sam3 - supports auto-erase, erase_check ignored");

  2696. 	for (x = 0; x < bank->num_sectors; x++)

  2697. 		bank->sectors[x].is_erased = 1;

  2698. 

  2699. 	LOG_DEBUG("Done");

  2700. 	return ERROR_OK;

  2701. }

  2702. 

  2703. static int sam3_protect_check(struct flash_bank *bank)

  2704. {

  2705. 	int r;

  2706. 	uint32_t v = 0;

  2707. 	unsigned x;

  2708. 	struct sam3_bank_private *pPrivate;

  2709. 

  2710. 	LOG_DEBUG("Begin");

  2711. 	if (bank->target->state != TARGET_HALTED) {

  2712. 		LOG_ERROR("Target not halted");

  2713. 		return ERROR_TARGET_NOT_HALTED;

  2714. 	}

  2715. 

  2716. 	pPrivate = get_sam3_bank_private(bank);

  2717. 	if (!pPrivate) {

  2718. 		LOG_ERROR("no private for this bank?");

  2719. 		return ERROR_FAIL;

  2720. 	}

  2721. 	if (!(pPrivate->probed))

  2722. 		return ERROR_FLASH_BANK_NOT_PROBED;

  2723. 

  2724. 	r = FLASHD_GetLockBits(pPrivate, &v);

  2725. 	if (r != ERROR_OK) {

  2726. 		LOG_DEBUG("Failed: %d", r);

  2727. 		return r;

  2728. 	}

  2729. 

  2730. 	for (x = 0; x < pPrivate->nsectors; x++)

  2731. 		bank->sectors[x].is_protected = (!!(v & (1 << x)));

  2732. 	LOG_DEBUG("Done");

  2733. 	return ERROR_OK;

  2734. }

  2735. 

  2736. FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)

  2737. {

  2738. 	struct sam3_chip *pChip;

  2739. 

  2740. 	pChip = all_sam3_chips;

  2741. 

  2742. 	/* is this an existing chip? */

  2743. 	while (pChip) {

  2744. 		if (pChip->target == bank->target)

  2745. 			break;

  2746. 		pChip = pChip->next;

  2747. 	}

  2748. 

  2749. 	if (!pChip) {

  2750. 		/* this is a *NEW* chip */

  2751. 		pChip = calloc(1, sizeof(struct sam3_chip));

  2752. 		if (!pChip) {

  2753. 			LOG_ERROR("NO RAM!");

  2754. 			return ERROR_FAIL;

  2755. 		}

  2756. 		pChip->target = bank->target;

  2757. 		/* insert at head */

  2758. 		pChip->next = all_sam3_chips;

  2759. 		all_sam3_chips = pChip;

  2760. 		pChip->target = bank->target;

  2761. 		/* assumption is this runs at 32khz */

  2762. 		pChip->cfg.slow_freq = 32768;

  2763. 		pChip->probed = 0;

  2764. 	}

  2765. 

  2766. 	switch (bank->base) {

  2767. 		default:

  2768. 			LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "

  2769. 			"[at91sam3u series] or 0x%08x [at91sam3s series] or "

  2770. 			"0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",

  2771. 			((unsigned int)(bank->base)),

  2772. 			((unsigned int)(FLASH_BANK0_BASE_U)),

  2773. 			((unsigned int)(FLASH_BANK1_BASE_U)),

  2774. 			((unsigned int)(FLASH_BANK_BASE_S)),

  2775. 			((unsigned int)(FLASH_BANK_BASE_N)),

  2776. 			((unsigned int)(FLASH_BANK0_BASE_AX)),

  2777. 		    ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),

  2778. 		    ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));

  2779. 			return ERROR_FAIL;

  2780. 			break;

  2781. 

  2782. 		/* at91sam3s and at91sam3n series only has bank 0*/

  2783. 		/* at91sam3u and at91sam3ax series has the same address for bank 0*/

  2784. 		case FLASH_BANK_BASE_S:

  2785. 		case FLASH_BANK0_BASE_U:

  2786. 			bank->driver_priv = &(pChip->details.bank[0]);

  2787. 			bank->bank_number = 0;

  2788. 			pChip->details.bank[0].pChip = pChip;

  2789. 			pChip->details.bank[0].pBank = bank;

  2790. 			break;

  2791. 

  2792. 		/* Bank 1 of at91sam3u or at91sam3ax series */

  2793. 		case FLASH_BANK1_BASE_U:

  2794. 		case FLASH_BANK1_BASE_256K_AX:

  2795. 		case FLASH_BANK1_BASE_512K_AX:

  2796. 			bank->driver_priv = &(pChip->details.bank[1]);

  2797. 			bank->bank_number = 1;

  2798. 			pChip->details.bank[1].pChip = pChip;

  2799. 			pChip->details.bank[1].pBank = bank;

  2800. 			break;

  2801. 	}

  2802. 

  2803. 	/* we initialize after probing. */

  2804. 	return ERROR_OK;

  2805. }

  2806. 

  2807. static int sam3_GetDetails(struct sam3_bank_private *pPrivate)

  2808. {

  2809. 	const struct sam3_chip_details *pDetails;

  2810. 	struct sam3_chip *pChip;

  2811. 	struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];

  2812. 	unsigned x;

  2813. 

  2814. 	LOG_DEBUG("Begin");

  2815. 	pDetails = all_sam3_details;

  2816. 	while (pDetails->name) {

  2817. 		/* Compare cidr without version bits */

  2818. 		if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))

  2819. 			break;

  2820. 		else

  2821. 			pDetails++;

  2822. 	}

  2823. 	if (pDetails->name == NULL) {

  2824. 		LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",

  2825. 			(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));

  2826. 		/* Help the victim, print details about the chip */

  2827. 		LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",

  2828. 			pPrivate->pChip->cfg.CHIPID_CIDR);

  2829. 		sam3_explain_chipid_cidr(pPrivate->pChip);

  2830. 		return ERROR_FAIL;

  2831. 	}

  2832. 

  2833. 	/* DANGER: THERE ARE DRAGONS HERE */

  2834. 

  2835. 	/* get our pChip - it is going */

  2836. 	/* to be over-written shortly */

  2837. 	pChip = pPrivate->pChip;

  2838. 

  2839. 	/* Note that, in reality: */

  2840. 	/*  */

  2841. 	/*     pPrivate = &(pChip->details.bank[0]) */

  2842. 	/* or  pPrivate = &(pChip->details.bank[1]) */

  2843. 	/*  */

  2844. 

  2845. 	/* save the "bank" pointers */

  2846. 	for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)

  2847. 		saved_banks[x] = pChip->details.bank[x].pBank;

  2848. 

  2849. 	/* Overwrite the "details" structure. */

  2850. 	memcpy(&(pPrivate->pChip->details),

  2851. 		pDetails,

  2852. 		sizeof(pPrivate->pChip->details));

  2853. 

  2854. 	/* now fix the ghosted pointers */

  2855. 	for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {

  2856. 		pChip->details.bank[x].pChip = pChip;

  2857. 		pChip->details.bank[x].pBank = saved_banks[x];

  2858. 	}

  2859. 

  2860. 	/* update the *BANK*SIZE* */

  2861. 

  2862. 	LOG_DEBUG("End");

  2863. 	return ERROR_OK;

  2864. }

  2865. 

  2866. static int _sam3_probe(struct flash_bank *bank, int noise)

  2867. {

  2868. 	unsigned x;

  2869. 	int r;

  2870. 	struct sam3_bank_private *pPrivate;

  2871. 

  2872. 

  2873. 	LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);

  2874. 	if (bank->target->state != TARGET_HALTED) {

  2875. 		LOG_ERROR("Target not halted");

  2876. 		return ERROR_TARGET_NOT_HALTED;

  2877. 	}

  2878. 

  2879. 	pPrivate = get_sam3_bank_private(bank);

  2880. 	if (!pPrivate) {

  2881. 		LOG_ERROR("Invalid/unknown bank number");

  2882. 		return ERROR_FAIL;

  2883. 	}

  2884. 

  2885. 	r = sam3_ReadAllRegs(pPrivate->pChip);

  2886. 	if (r != ERROR_OK)

  2887. 		return r;

  2888. 

  2889. 	LOG_DEBUG("Here");

  2890. 	if (pPrivate->pChip->probed)

  2891. 		r = sam3_GetInfo(pPrivate->pChip);

  2892. 	else

  2893. 		r = sam3_GetDetails(pPrivate);

  2894. 	if (r != ERROR_OK)

  2895. 		return r;

  2896. 

  2897. 	/* update the flash bank size */

  2898. 	for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {

  2899. 		if (bank->base == pPrivate->pChip->details.bank[x].base_address) {

  2900. 			bank->size = pPrivate->pChip->details.bank[x].size_bytes;

  2901. 			break;

  2902. 		}

  2903. 	}

  2904. 

  2905. 	if (bank->sectors == NULL) {

  2906. 		bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));

  2907. 		if (bank->sectors == NULL) {

  2908. 			LOG_ERROR("No memory!");

  2909. 			return ERROR_FAIL;

  2910. 		}

  2911. 		bank->num_sectors = pPrivate->nsectors;

  2912. 

  2913. 		for (x = 0; ((int)(x)) < bank->num_sectors; x++) {

  2914. 			bank->sectors[x].size = pPrivate->sector_size;

  2915. 			bank->sectors[x].offset = x * (pPrivate->sector_size);

  2916. 			/* mark as unknown */

  2917. 			bank->sectors[x].is_erased = -1;

  2918. 			bank->sectors[x].is_protected = -1;

  2919. 		}

  2920. 	}

  2921. 

  2922. 	pPrivate->probed = 1;

  2923. 

  2924. 	r = sam3_protect_check(bank);

  2925. 	if (r != ERROR_OK)

  2926. 		return r;

  2927. 

  2928. 	LOG_DEBUG("Bank = %d, nbanks = %d",

  2929. 		pPrivate->bank_number, pPrivate->pChip->details.n_banks);

  2930. 	if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {

  2931. 		/* read unique id, */

  2932. 		/* it appears to be associated with the *last* flash bank. */

  2933. 		FLASHD_ReadUniqueID(pPrivate);

  2934. 	}

  2935. 

  2936. 	return r;

  2937. }

  2938. 

  2939. static int sam3_probe(struct flash_bank *bank)

  2940. {

  2941. 	return _sam3_probe(bank, 1);

  2942. }

  2943. 

  2944. static int sam3_auto_probe(struct flash_bank *bank)

  2945. {

  2946. 	return _sam3_probe(bank, 0);

  2947. }

  2948. 

  2949. static int sam3_erase(struct flash_bank *bank, int first, int last)

  2950. {

  2951. 	struct sam3_bank_private *pPrivate;

  2952. 	int r;

  2953. 

  2954. 	LOG_DEBUG("Here");

  2955. 	if (bank->target->state != TARGET_HALTED) {

  2956. 		LOG_ERROR("Target not halted");

  2957. 		return ERROR_TARGET_NOT_HALTED;

  2958. 	}

  2959. 

  2960. 	r = sam3_auto_probe(bank);

  2961. 	if (r != ERROR_OK) {

  2962. 		LOG_DEBUG("Here,r=%d", r);

  2963. 		return r;

  2964. 	}

  2965. 

  2966. 	pPrivate = get_sam3_bank_private(bank);

  2967. 	if (!(pPrivate->probed))

  2968. 		return ERROR_FLASH_BANK_NOT_PROBED;

  2969. 

  2970. 	if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {

  2971. 		/* whole chip */

  2972. 		LOG_DEBUG("Here");

  2973. 		return FLASHD_EraseEntireBank(pPrivate);

  2974. 	}

  2975. 	LOG_INFO("sam3 auto-erases while programming (request ignored)");

  2976. 	return ERROR_OK;

  2977. }

  2978. 

  2979. static int sam3_protect(struct flash_bank *bank, int set, int first, int last)

  2980. {

  2981. 	struct sam3_bank_private *pPrivate;

  2982. 	int r;

  2983. 

  2984. 	LOG_DEBUG("Here");

  2985. 	if (bank->target->state != TARGET_HALTED) {

  2986. 		LOG_ERROR("Target not halted");

  2987. 		return ERROR_TARGET_NOT_HALTED;

  2988. 	}

  2989. 

  2990. 	pPrivate = get_sam3_bank_private(bank);

  2991. 	if (!(pPrivate->probed))

  2992. 		return ERROR_FLASH_BANK_NOT_PROBED;

  2993. 

  2994. 	if (set)

  2995. 		r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));

  2996. 	else

  2997. 		r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));

  2998. 	LOG_DEBUG("End: r=%d", r);

  2999. 

  3000. 	return r;

  3001. 

  3002. }

  3003. 

  3004. static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)

  3005. {

  3006. 	if (bank->target->state != TARGET_HALTED) {

  3007. 		LOG_ERROR("Target not halted");

  3008. 		return ERROR_TARGET_NOT_HALTED;

  3009. 	}

  3010. 	buf[0] = 0;

  3011. 	return ERROR_OK;

  3012. }

  3013. 

  3014. static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)

  3015. {

  3016. 	uint32_t adr;

  3017. 	int r;

  3018. 

  3019. 	adr = pagenum * pPrivate->page_size;

  3020. 	adr += pPrivate->base_address;

  3021. 

  3022. 	r = target_read_memory(pPrivate->pChip->target,

  3023. 			adr,

  3024. 			4,					/* THIS*MUST*BE* in 32bit values */

  3025. 			pPrivate->page_size / 4,

  3026. 			buf);

  3027. 	if (r != ERROR_OK)

  3028. 		LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",

  3029. 			(unsigned int)(adr));

  3030. 	return r;

  3031. }

  3032. 

  3033. /* The code below is basically this: */

  3034. /* compiled with */

  3035. /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */

  3036. /*  */

  3037. /* Only the *CPU* can write to the flash buffer. */

  3038. /* the DAP cannot... so - we download this 28byte thing */

  3039. /* Run the algorithm - (below) */

  3040. /* to program the device */

  3041. /*  */

  3042. /* ======================================== */

  3043. /* #include <stdint.h> */

  3044. /*  */

  3045. /* struct foo { */

  3046. /*   uint32_t *dst; */

  3047. /*   const uint32_t *src; */

  3048. /*   int   n; */

  3049. /*   volatile uint32_t *base; */

  3050. /*   uint32_t   cmd; */

  3051. /* }; */

  3052. /*  */

  3053. /*  */

  3054. /* uint32_t sam3_function(struct foo *p) */

  3055. /* { */

  3056. /*   volatile uint32_t *v; */

  3057. /*   uint32_t *d; */

  3058. /*   const uint32_t *s; */

  3059. /*   int   n; */

  3060. /*   uint32_t r; */

  3061. /*  */

  3062. /*   d = p->dst; */

  3063. /*   s = p->src; */

  3064. /*   n = p->n; */

  3065. /*  */

  3066. /*   do { */

  3067. /*     *d++ = *s++; */

  3068. /*   } while (--n) */

  3069. /*     ; */

  3070. /*  */

  3071. /*   v = p->base; */

  3072. /*  */

  3073. /*   v[ 1 ] = p->cmd; */

  3074. /*   do { */

  3075. /*     r = v[8/4]; */

  3076. /*   } while (!(r&1)) */

  3077. /*     ; */

  3078. /*   return r; */

  3079. /* } */

  3080. /* ======================================== */

  3081. 

  3082. static const uint8_t

  3083. 	sam3_page_write_opcodes[] = {

  3084. 	/*  24 0000 0446                mov	r4, r0 */

  3085. 	0x04, 0x46,

  3086. 	/*  25 0002 6168                ldr	r1, [r4, #4] */

  3087. 	0x61, 0x68,

  3088. 	/*  26 0004 0068                ldr	r0, [r0, #0] */

  3089. 	0x00, 0x68,

  3090. 	/*  27 0006 A268                ldr	r2, [r4, #8] */

  3091. 	0xa2, 0x68,

  3092. 	/*  28                          @ lr needed for prologue */

  3093. 	/*  29                  .L2: */

  3094. 	/*  30 0008 51F8043B            ldr	r3, [r1], #4 */

  3095. 	0x51, 0xf8, 0x04, 0x3b,

  3096. 	/*  31 000c 12F1FF32            adds	r2, r2, #-1 */

  3097. 	0x12, 0xf1, 0xff, 0x32,

  3098. 	/*  32 0010 40F8043B            str	r3, [r0], #4 */

  3099. 	0x40, 0xf8, 0x04, 0x3b,

  3100. 	/*  33 0014 F8D1                bne	.L2 */

  3101. 	0xf8, 0xd1,

  3102. 	/*  34 0016 E268                ldr	r2, [r4, #12] */

  3103. 	0xe2, 0x68,

  3104. 	/*  35 0018 2369                ldr	r3, [r4, #16] */

  3105. 	0x23, 0x69,

  3106. 	/*  36 001a 5360                str	r3, [r2, #4] */

  3107. 	0x53, 0x60,

  3108. 	/*  37 001c 0832                adds	r2, r2, #8 */

  3109. 	0x08, 0x32,

  3110. 	/*  38                  .L4: */

  3111. 	/*  39 001e 1068                ldr	r0, [r2, #0] */

  3112. 	0x10, 0x68,

  3113. 	/*  40 0020 10F0010F            tst	r0, #1 */

  3114. 	0x10, 0xf0, 0x01, 0x0f,

  3115. 	/*  41 0024 FBD0                beq	.L4 */

  3116. 	0xfb, 0xd0,

  3117. 	0x00, 0xBE				/* bkpt #0 */

  3118. };

  3119. 

  3120. static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)

  3121. {

  3122. 	uint32_t adr;

  3123. 	uint32_t status;

  3124. 	uint32_t fmr;	/* EEFC Flash Mode Register */

  3125. 	int r;

  3126. 

  3127. 	adr = pagenum * pPrivate->page_size;

  3128. 	adr += pPrivate->base_address;

  3129. 

  3130. 	/* Get flash mode register value */

  3131. 	r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);

  3132. 	if (r != ERROR_OK)

  3133. 		LOG_DEBUG("Error Read failed: read flash mode register");

  3134. 

  3135. 	/* Clear flash wait state field */

  3136. 	fmr &= 0xfffff0ff;

  3137. 

  3138. 	/* set FWS (flash wait states) field in the FMR (flash mode register) */

  3139. 	fmr |= (pPrivate->flash_wait_states << 8);

  3140. 

  3141. 	LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));

  3142. 	r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);

  3143. 	if (r != ERROR_OK)

  3144. 		LOG_DEBUG("Error Write failed: set flash mode register");

  3145. 

  3146. 	LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));

  3147. 	r = target_write_memory(pPrivate->pChip->target,

  3148. 			adr,

  3149. 			4,					/* THIS*MUST*BE* in 32bit values */

  3150. 			pPrivate->page_size / 4,

  3151. 			buf);

  3152. 	if (r != ERROR_OK) {

  3153. 		LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",

  3154. 			(unsigned int)(adr));

  3155. 		return r;

  3156. 	}

  3157. 

  3158. 	r = EFC_PerformCommand(pPrivate,

  3159. 			/* send Erase & Write Page */

  3160. 			AT91C_EFC_FCMD_EWP,

  3161. 			pagenum,

  3162. 			&status);

  3163. 

  3164. 	if (r != ERROR_OK)

  3165. 		LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",

  3166. 			(unsigned int)(adr));

  3167. 	if (status & (1 << 2)) {

  3168. 		LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));

  3169. 		return ERROR_FAIL;

  3170. 	}

  3171. 	if (status & (1 << 1)) {

  3172. 		LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));

  3173. 		return ERROR_FAIL;

  3174. 	}

  3175. 	return ERROR_OK;

  3176. }

  3177. 

  3178. static int sam3_write(struct flash_bank *bank,

  3179. 	uint8_t *buffer,

  3180. 	uint32_t offset,

  3181. 	uint32_t count)

  3182. {

  3183. 	int n;

  3184. 	unsigned page_cur;

  3185. 	unsigned page_end;

  3186. 	int r;

  3187. 	unsigned page_offset;

  3188. 	struct sam3_bank_private *pPrivate;

  3189. 	uint8_t *pagebuffer;

  3190. 

  3191. 	/* incase we bail further below, set this to null */

  3192. 	pagebuffer = NULL;

  3193. 

  3194. 	/* ignore dumb requests */

  3195. 	if (count == 0) {

  3196. 		r = ERROR_OK;

  3197. 		goto done;

  3198. 	}

  3199. 

  3200. 	if (bank->target->state != TARGET_HALTED) {

  3201. 		LOG_ERROR("Target not halted");

  3202. 		r = ERROR_TARGET_NOT_HALTED;

  3203. 		goto done;

  3204. 	}

  3205. 

  3206. 	pPrivate = get_sam3_bank_private(bank);

  3207. 	if (!(pPrivate->probed)) {

  3208. 		r = ERROR_FLASH_BANK_NOT_PROBED;

  3209. 		goto done;

  3210. 	}

  3211. 

  3212. 	if ((offset + count) > pPrivate->size_bytes) {

  3213. 		LOG_ERROR("Flash write error - past end of bank");

  3214. 		LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",

  3215. 			(unsigned int)(offset),

  3216. 			(unsigned int)(count),

  3217. 			(unsigned int)(pPrivate->size_bytes));

  3218. 		r = ERROR_FAIL;

  3219. 		goto done;

  3220. 	}

  3221. 

  3222. 	pagebuffer = malloc(pPrivate->page_size);

  3223. 	if (!pagebuffer) {

  3224. 		LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));

  3225. 		r = ERROR_FAIL;

  3226. 		goto done;

  3227. 	}

  3228. 

  3229. 	/* what page do we start & end in? */

  3230. 	page_cur = offset / pPrivate->page_size;

  3231. 	page_end = (offset + count - 1) / pPrivate->page_size;

  3232. 

  3233. 	LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));

  3234. 	LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));

  3235. 

  3236. 	/* Special case: all one page */

  3237. 	/*  */

  3238. 	/* Otherwise: */

  3239. 	/*    (1) non-aligned start */

  3240. 	/*    (2) body pages */

  3241. 	/*    (3) non-aligned end. */

  3242. 

  3243. 	/* Handle special case - all one page. */

  3244. 	if (page_cur == page_end) {

  3245. 		LOG_DEBUG("Special case, all in one page");

  3246. 		r = sam3_page_read(pPrivate, page_cur, pagebuffer);

  3247. 		if (r != ERROR_OK)

  3248. 			goto done;

  3249. 

  3250. 		page_offset = (offset & (pPrivate->page_size-1));

  3251. 		memcpy(pagebuffer + page_offset,

  3252. 			buffer,

  3253. 			count);

  3254. 

  3255. 		r = sam3_page_write(pPrivate, page_cur, pagebuffer);

  3256. 		if (r != ERROR_OK)

  3257. 			goto done;

  3258. 		r = ERROR_OK;

  3259. 		goto done;

  3260. 	}

  3261. 

  3262. 	/* non-aligned start */

  3263. 	page_offset = offset & (pPrivate->page_size - 1);

  3264. 	if (page_offset) {

  3265. 		LOG_DEBUG("Not-Aligned start");

  3266. 		/* read the partial */

  3267. 		r = sam3_page_read(pPrivate, page_cur, pagebuffer);

  3268. 		if (r != ERROR_OK)

  3269. 			goto done;

  3270. 

  3271. 		/* over-write with new data */

  3272. 		n = (pPrivate->page_size - page_offset);

  3273. 		memcpy(pagebuffer + page_offset,

  3274. 			buffer,

  3275. 			n);

  3276. 

  3277. 		r = sam3_page_write(pPrivate, page_cur, pagebuffer);

  3278. 		if (r != ERROR_OK)

  3279. 			goto done;

  3280. 

  3281. 		count  -= n;

  3282. 		offset += n;

  3283. 		buffer += n;

  3284. 		page_cur++;

  3285. 	}

  3286. 

  3287. 	/* By checking that offset is correct here, we also

  3288. 	fix a clang warning */

  3289. 	assert(offset % pPrivate->page_size == 0);

  3290. 

  3291. 	/* intermediate large pages */

  3292. 	/* also - the final *terminal* */

  3293. 	/* if that terminal page is a full page */

  3294. 	LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",

  3295. 		(int)page_cur, (int)page_end, (unsigned int)(count));

  3296. 

  3297. 	while ((page_cur < page_end) &&

  3298. 			(count >= pPrivate->page_size)) {

  3299. 		r = sam3_page_write(pPrivate, page_cur, buffer);

  3300. 		if (r != ERROR_OK)

  3301. 			goto done;

  3302. 		count -= pPrivate->page_size;

  3303. 		buffer += pPrivate->page_size;

  3304. 		page_cur += 1;

  3305. 	}

  3306. 

  3307. 	/* terminal partial page? */

  3308. 	if (count) {

  3309. 		LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));

  3310. 		/* we have a partial page */

  3311. 		r = sam3_page_read(pPrivate, page_cur, pagebuffer);

  3312. 		if (r != ERROR_OK)

  3313. 			goto done;

  3314. 					/* data goes at start */

  3315. 		memcpy(pagebuffer, buffer, count);

  3316. 		r = sam3_page_write(pPrivate, page_cur, pagebuffer);

  3317. 		if (r != ERROR_OK)

  3318. 			goto done;

  3319. 	}

  3320. 	LOG_DEBUG("Done!");

  3321. 	r = ERROR_OK;

  3322. done:

  3323. 	if (pagebuffer)

  3324. 		free(pagebuffer);

  3325. 	return r;

  3326. }

  3327. 

  3328. COMMAND_HANDLER(sam3_handle_info_command)

  3329. {

  3330. 	struct sam3_chip *pChip;

  3331. 	pChip = get_current_sam3(CMD_CTX);

  3332. 	if (!pChip)

  3333. 		return ERROR_OK;

  3334. 

  3335. 	unsigned x;

  3336. 	int r;

  3337. 

  3338. 	/* bank0 must exist before we can do anything */

  3339. 	if (pChip->details.bank[0].pBank == NULL) {

  3340. 		x = 0;

  3341. need_define:

  3342. 		command_print(CMD_CTX,

  3343. 			"Please define bank %d via command: flash bank %s ... ",

  3344. 			x,

  3345. 			at91sam3_flash.name);

  3346. 		return ERROR_FAIL;

  3347. 	}

  3348. 

  3349. 	/* if bank 0 is not probed, then probe it */

  3350. 	if (!(pChip->details.bank[0].probed)) {

  3351. 		r = sam3_auto_probe(pChip->details.bank[0].pBank);

  3352. 		if (r != ERROR_OK)

  3353. 			return ERROR_FAIL;

  3354. 	}

  3355. 	/* above guarantees the "chip details" structure is valid */

  3356. 	/* and thus, bank private areas are valid */

  3357. 	/* and we have a SAM3 chip, what a concept! */

  3358. 

  3359. 	/* auto-probe other banks, 0 done above */

  3360. 	for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {

  3361. 		/* skip banks not present */

  3362. 		if (!(pChip->details.bank[x].present))

  3363. 			continue;

  3364. 

  3365. 		if (pChip->details.bank[x].pBank == NULL)

  3366. 			goto need_define;

  3367. 

  3368. 		if (pChip->details.bank[x].probed)

  3369. 			continue;

  3370. 

  3371. 		r = sam3_auto_probe(pChip->details.bank[x].pBank);

  3372. 		if (r != ERROR_OK)

  3373. 			return r;

  3374. 	}

  3375. 

  3376. 	r = sam3_GetInfo(pChip);

  3377. 	if (r != ERROR_OK) {

  3378. 		LOG_DEBUG("Sam3Info, Failed %d", r);

  3379. 		return r;

  3380. 	}

  3381. 

  3382. 	return ERROR_OK;

  3383. }

  3384. 

  3385. COMMAND_HANDLER(sam3_handle_gpnvm_command)

  3386. {

  3387. 	unsigned x, v;

  3388. 	int r, who;

  3389. 	struct sam3_chip *pChip;

  3390. 

  3391. 	pChip = get_current_sam3(CMD_CTX);

  3392. 	if (!pChip)

  3393. 		return ERROR_OK;

  3394. 

  3395. 	if (pChip->target->state != TARGET_HALTED) {

  3396. 		LOG_ERROR("sam3 - target not halted");

  3397. 		return ERROR_TARGET_NOT_HALTED;

  3398. 	}

  3399. 

  3400. 	if (pChip->details.bank[0].pBank == NULL) {

  3401. 		command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",

  3402. 			at91sam3_flash.name);

  3403. 		return ERROR_FAIL;

  3404. 	}

  3405. 	if (!pChip->details.bank[0].probed) {

  3406. 		r = sam3_auto_probe(pChip->details.bank[0].pBank);

  3407. 		if (r != ERROR_OK)

  3408. 			return r;

  3409. 	}

  3410. 

  3411. 	switch (CMD_ARGC) {

  3412. 		default:

  3413. 			return ERROR_COMMAND_SYNTAX_ERROR;

  3414. 			break;

  3415. 		case 0:

  3416. 			goto showall;

  3417. 			break;

  3418. 		case 1:

  3419. 			who = -1;

  3420. 			break;

  3421. 		case 2:

  3422. 			if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))

  3423. 				who = -1;

  3424. 			else {

  3425. 				uint32_t v32;

  3426. 				COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);

  3427. 				who = v32;

  3428. 			}

  3429. 			break;

  3430. 	}

  3431. 

  3432. 	if (0 == strcmp("show", CMD_ARGV[0])) {

  3433. 		if (who == -1) {

  3434. showall:

  3435. 			r = ERROR_OK;

  3436. 			for (x = 0; x < pChip->details.n_gpnvms; x++) {

  3437. 				r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);

  3438. 				if (r != ERROR_OK)

  3439. 					break;

  3440. 				command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);

  3441. 			}

  3442. 			return r;

  3443. 		}

  3444. 		if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {

  3445. 			r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);

  3446. 			command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);

  3447. 			return r;

  3448. 		} else {

  3449. 			command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);

  3450. 			return ERROR_COMMAND_SYNTAX_ERROR;

  3451. 		}

  3452. 	}

  3453. 

  3454. 	if (who == -1) {

  3455. 		command_print(CMD_CTX, "Missing GPNVM number");

  3456. 		return ERROR_COMMAND_SYNTAX_ERROR;

  3457. 	}

  3458. 

  3459. 	if (0 == strcmp("set", CMD_ARGV[0]))

  3460. 		r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);

  3461. 	else if ((0 == strcmp("clr", CMD_ARGV[0])) ||

  3462. 		 (0 == strcmp("clear", CMD_ARGV[0])))			/* quietly accept both */

  3463. 		r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);

  3464. 	else {

  3465. 		command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);

  3466. 		r = ERROR_COMMAND_SYNTAX_ERROR;

  3467. 	}

  3468. 	return r;

  3469. }

  3470. 

  3471. COMMAND_HANDLER(sam3_handle_slowclk_command)

  3472. {

  3473. 	struct sam3_chip *pChip;

  3474. 

  3475. 	pChip = get_current_sam3(CMD_CTX);

  3476. 	if (!pChip)

  3477. 		return ERROR_OK;

  3478. 

  3479. 	switch (CMD_ARGC) {

  3480. 		case 0:

  3481. 			/* show */

  3482. 			break;

  3483. 		case 1:

  3484. 		{

  3485. 			/* set */

  3486. 			uint32_t v;

  3487. 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);

  3488. 			if (v > 200000) {

  3489. 				/* absurd slow clock of 200Khz? */

  3490. 				command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));

  3491. 				return ERROR_COMMAND_SYNTAX_ERROR;

  3492. 			}

  3493. 			pChip->cfg.slow_freq = v;

  3494. 			break;

  3495. 		}

  3496. 		default:

  3497. 			/* error */

  3498. 			command_print(CMD_CTX, "Too many parameters");

  3499. 			return ERROR_COMMAND_SYNTAX_ERROR;

  3500. 			break;

  3501. 	}

  3502. 	command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",

  3503. 		(int)(pChip->cfg.slow_freq / 1000),

  3504. 		(int)(pChip->cfg.slow_freq % 1000));

  3505. 	return ERROR_OK;

  3506. }

  3507. 

  3508. static const struct command_registration at91sam3_exec_command_handlers[] = {

  3509. 	{

  3510. 		.name = "gpnvm",

  3511. 		.handler = sam3_handle_gpnvm_command,

  3512. 		.mode = COMMAND_EXEC,

  3513. 		.usage = "[('clr'|'set'|'show') bitnum]",

  3514. 		.help = "Without arguments, shows all bits in the gpnvm "

  3515. 			"register.  Otherwise, clears, sets, or shows one "

  3516. 			"General Purpose Non-Volatile Memory (gpnvm) bit.",

  3517. 	},

  3518. 	{

  3519. 		.name = "info",

  3520. 		.handler = sam3_handle_info_command,

  3521. 		.mode = COMMAND_EXEC,

  3522. 		.help = "Print information about the current at91sam3 chip"

  3523. 			"and its flash configuration.",

  3524. 	},

  3525. 	{

  3526. 		.name = "slowclk",

  3527. 		.handler = sam3_handle_slowclk_command,

  3528. 		.mode = COMMAND_EXEC,

  3529. 		.usage = "[clock_hz]",

  3530. 		.help = "Display or set the slowclock frequency "

  3531. 			"(default 32768 Hz).",

  3532. 	},

  3533. 	COMMAND_REGISTRATION_DONE

  3534. };

  3535. static const struct command_registration at91sam3_command_handlers[] = {

  3536. 	{

  3537. 		.name = "at91sam3",

  3538. 		.mode = COMMAND_ANY,

  3539. 		.help = "at91sam3 flash command group",

  3540. 		.usage = "",

  3541. 		.chain = at91sam3_exec_command_handlers,

  3542. 	},

  3543. 	COMMAND_REGISTRATION_DONE

  3544. };

  3545. 

  3546. struct flash_driver at91sam3_flash = {

  3547. 	.name = "at91sam3",

  3548. 	.commands = at91sam3_command_handlers,

  3549. 	.flash_bank_command = sam3_flash_bank_command,

  3550. 	.erase = sam3_erase,

  3551. 	.protect = sam3_protect,

  3552. 	.write = sam3_write,

  3553. 	.read = default_flash_read,

  3554. 	.probe = sam3_probe,

  3555. 	.auto_probe = sam3_auto_probe,

  3556. 	.erase_check = sam3_erase_check,

  3557. 	.protect_check = sam3_protect_check,

  3558. 	.info = sam3_info,

  3559. };