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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Duane Ellis *
  3. * openocd@duaneellis.com *
  4. * *
  5. * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
  6. * olaf@uni-paderborn.de *
  7. * *
  8. * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
  9. * and Jim Norris *
  10. * This program is free software; you can redistribute it and/or modify *
  11. * it under the terms of the GNU General public License as published by *
  12. * the Free Software Foundation; either version 2 of the License, or *
  13. * (at your option) any later version. *
  14. * *
  15. * This program is distributed in the hope that it will be useful, *
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  17. * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
  18. * GNU General public License for more details. *
  19. * *
  20. * You should have received a copy of the GNU General public License *
  21. * along with this program; if not, write to the *
  22. * Free Software Foundation, Inc., *
  23. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  24. ****************************************************************************/
  25. /* Some of the the lower level code was based on code supplied by
  26. * ATMEL under this copyright. */
  27. /* BEGIN ATMEL COPYRIGHT */
  28. /* ----------------------------------------------------------------------------
  29. * ATMEL Microcontroller Software Support
  30. * ----------------------------------------------------------------------------
  31. * Copyright (c) 2009, Atmel Corporation
  32. *
  33. * All rights reserved.
  34. *
  35. * Redistribution and use in source and binary forms, with or without
  36. * modification, are permitted provided that the following conditions are met:
  37. *
  38. * - Redistributions of source code must retain the above copyright notice,
  39. * this list of conditions and the disclaimer below.
  40. *
  41. * Atmel's name may not be used to endorse or promote products derived from
  42. * this software without specific prior written permission.
  43. *
  44. * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  45. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  46. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  47. * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  48. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  50. * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  51. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  52. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  53. * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54. * ----------------------------------------------------------------------------
  55. */
  56. /* END ATMEL COPYRIGHT */
  57. #ifdef HAVE_CONFIG_H
  58. #include "config.h"
  59. #endif
  60. #include "imp.h"
  61. #include <helper/time_support.h>
  62. #define REG_NAME_WIDTH (12)
  63. /* at91sam3u series (has one or two flash banks) */
  64. #define FLASH_BANK0_BASE_U 0x00080000
  65. #define FLASH_BANK1_BASE_U 0x00100000
  66. /* at91sam3s series (has always one flash bank) */
  67. #define FLASH_BANK_BASE_S 0x00400000
  68. /* at91sam3n series (has always one flash bank) */
  69. #define FLASH_BANK_BASE_N 0x00400000
  70. /* at91sam3a/x series has two flash banks*/
  71. #define FLASH_BANK0_BASE_AX 0x00080000
  72. /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
  73. #define FLASH_BANK1_BASE_256K_AX 0x000A0000
  74. #define FLASH_BANK1_BASE_512K_AX 0x000C0000
  75. #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
  76. #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
  77. #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
  78. #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
  79. #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
  80. #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
  81. #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
  82. #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
  83. /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
  84. /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
  85. /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
  86. /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
  87. #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
  88. #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
  89. #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
  90. #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
  91. #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
  92. #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
  93. #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
  94. #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
  95. #define offset_EFC_FMR 0
  96. #define offset_EFC_FCR 4
  97. #define offset_EFC_FSR 8
  98. #define offset_EFC_FRR 12
  99. extern struct flash_driver at91sam3_flash;
  100. static float _tomhz(uint32_t freq_hz)
  101. {
  102. float f;
  103. f = ((float)(freq_hz)) / 1000000.0;
  104. return f;
  105. }
  106. /* How the chip is configured. */
  107. struct sam3_cfg {
  108. uint32_t unique_id[4];
  109. uint32_t slow_freq;
  110. uint32_t rc_freq;
  111. uint32_t mainosc_freq;
  112. uint32_t plla_freq;
  113. uint32_t mclk_freq;
  114. uint32_t cpu_freq;
  115. uint32_t fclk_freq;
  116. uint32_t pclk0_freq;
  117. uint32_t pclk1_freq;
  118. uint32_t pclk2_freq;
  119. #define SAM3_CHIPID_CIDR (0x400E0740)
  120. uint32_t CHIPID_CIDR;
  121. #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
  122. uint32_t CHIPID_CIDR2;
  123. #define SAM3_CHIPID_EXID (0x400E0744)
  124. uint32_t CHIPID_EXID;
  125. #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
  126. uint32_t CHIPID_EXID2;
  127. #define SAM3_PMC_BASE (0x400E0400)
  128. #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
  129. uint32_t PMC_SCSR;
  130. #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
  131. uint32_t PMC_PCSR;
  132. #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
  133. uint32_t CKGR_UCKR;
  134. #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
  135. uint32_t CKGR_MOR;
  136. #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
  137. uint32_t CKGR_MCFR;
  138. #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
  139. uint32_t CKGR_PLLAR;
  140. #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
  141. uint32_t PMC_MCKR;
  142. #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
  143. uint32_t PMC_PCK0;
  144. #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
  145. uint32_t PMC_PCK1;
  146. #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
  147. uint32_t PMC_PCK2;
  148. #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
  149. uint32_t PMC_SR;
  150. #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
  151. uint32_t PMC_IMR;
  152. #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
  153. uint32_t PMC_FSMR;
  154. #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
  155. uint32_t PMC_FSPR;
  156. };
  157. /*
  158. * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
  159. * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
  160. * the flash wait state (FWS) should be set to 6. It seems like that the
  161. * cause of the problem is not the flash itself, but the flash write
  162. * buffer. Ie the wait states have to be set before writing into the
  163. * buffer.
  164. * Tested and confirmed with SAM3N and SAM3U
  165. */
  166. struct sam3_bank_private {
  167. int probed;
  168. /* DANGER: THERE ARE DRAGONS HERE.. */
  169. /* NOTE: If you add more 'ghost' pointers */
  170. /* be aware that you must *manually* update */
  171. /* these pointers in the function sam3_GetDetails() */
  172. /* See the comment "Here there be dragons" */
  173. /* so we can find the chip we belong to */
  174. struct sam3_chip *pChip;
  175. /* so we can find the original bank pointer */
  176. struct flash_bank *pBank;
  177. unsigned bank_number;
  178. uint32_t controller_address;
  179. uint32_t base_address;
  180. uint32_t flash_wait_states;
  181. bool present;
  182. unsigned size_bytes;
  183. unsigned nsectors;
  184. unsigned sector_size;
  185. unsigned page_size;
  186. };
  187. struct sam3_chip_details {
  188. /* THERE ARE DRAGONS HERE.. */
  189. /* note: If you add pointers here */
  190. /* be careful about them as they */
  191. /* may need to be updated inside */
  192. /* the function: "sam3_GetDetails() */
  193. /* which copy/overwrites the */
  194. /* 'runtime' copy of this structure */
  195. uint32_t chipid_cidr;
  196. const char *name;
  197. unsigned n_gpnvms;
  198. #define SAM3_N_NVM_BITS 3
  199. unsigned gpnvm[SAM3_N_NVM_BITS];
  200. unsigned total_flash_size;
  201. unsigned total_sram_size;
  202. unsigned n_banks;
  203. #define SAM3_MAX_FLASH_BANKS 2
  204. /* these are "initialized" from the global const data */
  205. struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
  206. };
  207. struct sam3_chip {
  208. struct sam3_chip *next;
  209. int probed;
  210. /* this is "initialized" from the global const structure */
  211. struct sam3_chip_details details;
  212. struct target *target;
  213. struct sam3_cfg cfg;
  214. };
  215. struct sam3_reg_list {
  216. uint32_t address; size_t struct_offset; const char *name;
  217. void (*explain_func)(struct sam3_chip *pInfo);
  218. };
  219. static struct sam3_chip *all_sam3_chips;
  220. static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
  221. {
  222. struct target *t;
  223. static struct sam3_chip *p;
  224. t = get_current_target(cmd_ctx);
  225. if (!t) {
  226. command_print(cmd_ctx, "No current target?");
  227. return NULL;
  228. }
  229. p = all_sam3_chips;
  230. if (!p) {
  231. /* this should not happen */
  232. /* the command is not registered until the chip is created? */
  233. command_print(cmd_ctx, "No SAM3 chips exist?");
  234. return NULL;
  235. }
  236. while (p) {
  237. if (p->target == t)
  238. return p;
  239. p = p->next;
  240. }
  241. command_print(cmd_ctx, "Cannot find SAM3 chip?");
  242. return NULL;
  243. }
  244. /* these are used to *initialize* the "pChip->details" structure. */
  245. static const struct sam3_chip_details all_sam3_details[] = {
  246. /* Start at91sam3u* series */
  247. {
  248. .chipid_cidr = 0x28100960,
  249. .name = "at91sam3u4e",
  250. .total_flash_size = 256 * 1024,
  251. .total_sram_size = 52 * 1024,
  252. .n_gpnvms = 3,
  253. .n_banks = 2,
  254. /* System boots at address 0x0 */
  255. /* gpnvm[1] = selects boot code */
  256. /* if gpnvm[1] == 0 */
  257. /* boot is via "SAMBA" (rom) */
  258. /* else */
  259. /* boot is via FLASH */
  260. /* Selection is via gpnvm[2] */
  261. /* endif */
  262. /* */
  263. /* NOTE: banks 0 & 1 switch places */
  264. /* if gpnvm[2] == 0 */
  265. /* Bank0 is the boot rom */
  266. /* else */
  267. /* Bank1 is the boot rom */
  268. /* endif */
  269. /* .bank[0] = { */
  270. {
  271. {
  272. .probed = 0,
  273. .pChip = NULL,
  274. .pBank = NULL,
  275. .bank_number = 0,
  276. .base_address = FLASH_BANK0_BASE_U,
  277. .controller_address = 0x400e0800,
  278. .flash_wait_states = 6, /* workaround silicon bug */
  279. .present = 1,
  280. .size_bytes = 128 * 1024,
  281. .nsectors = 16,
  282. .sector_size = 8192,
  283. .page_size = 256,
  284. },
  285. /* .bank[1] = { */
  286. {
  287. .probed = 0,
  288. .pChip = NULL,
  289. .pBank = NULL,
  290. .bank_number = 1,
  291. .base_address = FLASH_BANK1_BASE_U,
  292. .controller_address = 0x400e0a00,
  293. .flash_wait_states = 6, /* workaround silicon bug */
  294. .present = 1,
  295. .size_bytes = 128 * 1024,
  296. .nsectors = 16,
  297. .sector_size = 8192,
  298. .page_size = 256,
  299. },
  300. },
  301. },
  302. {
  303. .chipid_cidr = 0x281a0760,
  304. .name = "at91sam3u2e",
  305. .total_flash_size = 128 * 1024,
  306. .total_sram_size = 36 * 1024,
  307. .n_gpnvms = 2,
  308. .n_banks = 1,
  309. /* System boots at address 0x0 */
  310. /* gpnvm[1] = selects boot code */
  311. /* if gpnvm[1] == 0 */
  312. /* boot is via "SAMBA" (rom) */
  313. /* else */
  314. /* boot is via FLASH */
  315. /* Selection is via gpnvm[2] */
  316. /* endif */
  317. /* .bank[0] = { */
  318. {
  319. {
  320. .probed = 0,
  321. .pChip = NULL,
  322. .pBank = NULL,
  323. .bank_number = 0,
  324. .base_address = FLASH_BANK0_BASE_U,
  325. .controller_address = 0x400e0800,
  326. .flash_wait_states = 6, /* workaround silicon bug */
  327. .present = 1,
  328. .size_bytes = 128 * 1024,
  329. .nsectors = 16,
  330. .sector_size = 8192,
  331. .page_size = 256,
  332. },
  333. /* .bank[1] = { */
  334. {
  335. .present = 0,
  336. .probed = 0,
  337. .bank_number = 1,
  338. },
  339. },
  340. },
  341. {
  342. .chipid_cidr = 0x28190560,
  343. .name = "at91sam3u1e",
  344. .total_flash_size = 64 * 1024,
  345. .total_sram_size = 20 * 1024,
  346. .n_gpnvms = 2,
  347. .n_banks = 1,
  348. /* System boots at address 0x0 */
  349. /* gpnvm[1] = selects boot code */
  350. /* if gpnvm[1] == 0 */
  351. /* boot is via "SAMBA" (rom) */
  352. /* else */
  353. /* boot is via FLASH */
  354. /* Selection is via gpnvm[2] */
  355. /* endif */
  356. /* */
  357. /* .bank[0] = { */
  358. {
  359. {
  360. .probed = 0,
  361. .pChip = NULL,
  362. .pBank = NULL,
  363. .bank_number = 0,
  364. .base_address = FLASH_BANK0_BASE_U,
  365. .controller_address = 0x400e0800,
  366. .flash_wait_states = 6, /* workaround silicon bug */
  367. .present = 1,
  368. .size_bytes = 64 * 1024,
  369. .nsectors = 8,
  370. .sector_size = 8192,
  371. .page_size = 256,
  372. },
  373. /* .bank[1] = { */
  374. {
  375. .present = 0,
  376. .probed = 0,
  377. .bank_number = 1,
  378. },
  379. },
  380. },
  381. {
  382. .chipid_cidr = 0x28000960,
  383. .name = "at91sam3u4c",
  384. .total_flash_size = 256 * 1024,
  385. .total_sram_size = 52 * 1024,
  386. .n_gpnvms = 3,
  387. .n_banks = 2,
  388. /* System boots at address 0x0 */
  389. /* gpnvm[1] = selects boot code */
  390. /* if gpnvm[1] == 0 */
  391. /* boot is via "SAMBA" (rom) */
  392. /* else */
  393. /* boot is via FLASH */
  394. /* Selection is via gpnvm[2] */
  395. /* endif */
  396. /* */
  397. /* NOTE: banks 0 & 1 switch places */
  398. /* if gpnvm[2] == 0 */
  399. /* Bank0 is the boot rom */
  400. /* else */
  401. /* Bank1 is the boot rom */
  402. /* endif */
  403. {
  404. {
  405. /* .bank[0] = { */
  406. .probed = 0,
  407. .pChip = NULL,
  408. .pBank = NULL,
  409. .bank_number = 0,
  410. .base_address = FLASH_BANK0_BASE_U,
  411. .controller_address = 0x400e0800,
  412. .flash_wait_states = 6, /* workaround silicon bug */
  413. .present = 1,
  414. .size_bytes = 128 * 1024,
  415. .nsectors = 16,
  416. .sector_size = 8192,
  417. .page_size = 256,
  418. },
  419. /* .bank[1] = { */
  420. {
  421. .probed = 0,
  422. .pChip = NULL,
  423. .pBank = NULL,
  424. .bank_number = 1,
  425. .base_address = FLASH_BANK1_BASE_U,
  426. .controller_address = 0x400e0a00,
  427. .flash_wait_states = 6, /* workaround silicon bug */
  428. .present = 1,
  429. .size_bytes = 128 * 1024,
  430. .nsectors = 16,
  431. .sector_size = 8192,
  432. .page_size = 256,
  433. },
  434. },
  435. },
  436. {
  437. .chipid_cidr = 0x280a0760,
  438. .name = "at91sam3u2c",
  439. .total_flash_size = 128 * 1024,
  440. .total_sram_size = 36 * 1024,
  441. .n_gpnvms = 2,
  442. .n_banks = 1,
  443. /* System boots at address 0x0 */
  444. /* gpnvm[1] = selects boot code */
  445. /* if gpnvm[1] == 0 */
  446. /* boot is via "SAMBA" (rom) */
  447. /* else */
  448. /* boot is via FLASH */
  449. /* Selection is via gpnvm[2] */
  450. /* endif */
  451. {
  452. /* .bank[0] = { */
  453. {
  454. .probed = 0,
  455. .pChip = NULL,
  456. .pBank = NULL,
  457. .bank_number = 0,
  458. .base_address = FLASH_BANK0_BASE_U,
  459. .controller_address = 0x400e0800,
  460. .flash_wait_states = 6, /* workaround silicon bug */
  461. .present = 1,
  462. .size_bytes = 128 * 1024,
  463. .nsectors = 16,
  464. .sector_size = 8192,
  465. .page_size = 256,
  466. },
  467. /* .bank[1] = { */
  468. {
  469. .present = 0,
  470. .probed = 0,
  471. .bank_number = 1,
  472. },
  473. },
  474. },
  475. {
  476. .chipid_cidr = 0x28090560,
  477. .name = "at91sam3u1c",
  478. .total_flash_size = 64 * 1024,
  479. .total_sram_size = 20 * 1024,
  480. .n_gpnvms = 2,
  481. .n_banks = 1,
  482. /* System boots at address 0x0 */
  483. /* gpnvm[1] = selects boot code */
  484. /* if gpnvm[1] == 0 */
  485. /* boot is via "SAMBA" (rom) */
  486. /* else */
  487. /* boot is via FLASH */
  488. /* Selection is via gpnvm[2] */
  489. /* endif */
  490. /* */
  491. {
  492. /* .bank[0] = { */
  493. {
  494. .probed = 0,
  495. .pChip = NULL,
  496. .pBank = NULL,
  497. .bank_number = 0,
  498. .base_address = FLASH_BANK0_BASE_U,
  499. .controller_address = 0x400e0800,
  500. .flash_wait_states = 6, /* workaround silicon bug */
  501. .present = 1,
  502. .size_bytes = 64 * 1024,
  503. .nsectors = 8,
  504. .sector_size = 8192,
  505. .page_size = 256,
  506. },
  507. /* .bank[1] = { */
  508. {
  509. .present = 0,
  510. .probed = 0,
  511. .bank_number = 1,
  512. },
  513. },
  514. },
  515. /* Start at91sam3s* series */
  516. /* Note: The preliminary at91sam3s datasheet says on page 302 */
  517. /* that the flash controller is at address 0x400E0800. */
  518. /* This is _not_ the case, the controller resides at address 0x400e0a0. */
  519. {
  520. .chipid_cidr = 0x28A00960,
  521. .name = "at91sam3s4c",
  522. .total_flash_size = 256 * 1024,
  523. .total_sram_size = 48 * 1024,
  524. .n_gpnvms = 2,
  525. .n_banks = 1,
  526. {
  527. /* .bank[0] = { */
  528. {
  529. .probed = 0,
  530. .pChip = NULL,
  531. .pBank = NULL,
  532. .bank_number = 0,
  533. .base_address = FLASH_BANK_BASE_S,
  534. .controller_address = 0x400e0a00,
  535. .flash_wait_states = 6, /* workaround silicon bug */
  536. .present = 1,
  537. .size_bytes = 256 * 1024,
  538. .nsectors = 16,
  539. .sector_size = 16384,
  540. .page_size = 256,
  541. },
  542. /* .bank[1] = { */
  543. {
  544. .present = 0,
  545. .probed = 0,
  546. .bank_number = 1,
  547. },
  548. },
  549. },
  550. {
  551. .chipid_cidr = 0x28900960,
  552. .name = "at91sam3s4b",
  553. .total_flash_size = 256 * 1024,
  554. .total_sram_size = 48 * 1024,
  555. .n_gpnvms = 2,
  556. .n_banks = 1,
  557. {
  558. /* .bank[0] = { */
  559. {
  560. .probed = 0,
  561. .pChip = NULL,
  562. .pBank = NULL,
  563. .bank_number = 0,
  564. .base_address = FLASH_BANK_BASE_S,
  565. .controller_address = 0x400e0a00,
  566. .flash_wait_states = 6, /* workaround silicon bug */
  567. .present = 1,
  568. .size_bytes = 256 * 1024,
  569. .nsectors = 16,
  570. .sector_size = 16384,
  571. .page_size = 256,
  572. },
  573. /* .bank[1] = { */
  574. {
  575. .present = 0,
  576. .probed = 0,
  577. .bank_number = 1,
  578. },
  579. },
  580. },
  581. {
  582. .chipid_cidr = 0x28800960,
  583. .name = "at91sam3s4a",
  584. .total_flash_size = 256 * 1024,
  585. .total_sram_size = 48 * 1024,
  586. .n_gpnvms = 2,
  587. .n_banks = 1,
  588. {
  589. /* .bank[0] = { */
  590. {
  591. .probed = 0,
  592. .pChip = NULL,
  593. .pBank = NULL,
  594. .bank_number = 0,
  595. .base_address = FLASH_BANK_BASE_S,
  596. .controller_address = 0x400e0a00,
  597. .flash_wait_states = 6, /* workaround silicon bug */
  598. .present = 1,
  599. .size_bytes = 256 * 1024,
  600. .nsectors = 16,
  601. .sector_size = 16384,
  602. .page_size = 256,
  603. },
  604. /* .bank[1] = { */
  605. {
  606. .present = 0,
  607. .probed = 0,
  608. .bank_number = 1,
  609. },
  610. },
  611. },
  612. {
  613. .chipid_cidr = 0x28AA0760,
  614. .name = "at91sam3s2c",
  615. .total_flash_size = 128 * 1024,
  616. .total_sram_size = 32 * 1024,
  617. .n_gpnvms = 2,
  618. .n_banks = 1,
  619. {
  620. /* .bank[0] = { */
  621. {
  622. .probed = 0,
  623. .pChip = NULL,
  624. .pBank = NULL,
  625. .bank_number = 0,
  626. .base_address = FLASH_BANK_BASE_S,
  627. .controller_address = 0x400e0a00,
  628. .flash_wait_states = 6, /* workaround silicon bug */
  629. .present = 1,
  630. .size_bytes = 128 * 1024,
  631. .nsectors = 8,
  632. .sector_size = 16384,
  633. .page_size = 256,
  634. },
  635. /* .bank[1] = { */
  636. {
  637. .present = 0,
  638. .probed = 0,
  639. .bank_number = 1,
  640. },
  641. },
  642. },
  643. {
  644. .chipid_cidr = 0x289A0760,
  645. .name = "at91sam3s2b",
  646. .total_flash_size = 128 * 1024,
  647. .total_sram_size = 32 * 1024,
  648. .n_gpnvms = 2,
  649. .n_banks = 1,
  650. {
  651. /* .bank[0] = { */
  652. {
  653. .probed = 0,
  654. .pChip = NULL,
  655. .pBank = NULL,
  656. .bank_number = 0,
  657. .base_address = FLASH_BANK_BASE_S,
  658. .controller_address = 0x400e0a00,
  659. .flash_wait_states = 6, /* workaround silicon bug */
  660. .present = 1,
  661. .size_bytes = 128 * 1024,
  662. .nsectors = 8,
  663. .sector_size = 16384,
  664. .page_size = 256,
  665. },
  666. /* .bank[1] = { */
  667. {
  668. .present = 0,
  669. .probed = 0,
  670. .bank_number = 1,
  671. },
  672. },
  673. },
  674. {
  675. .chipid_cidr = 0x29ab0a60,
  676. .name = "at91sam3sd8c",
  677. .total_flash_size = 512 * 1024,
  678. .total_sram_size = 64 * 1024,
  679. .n_gpnvms = 3,
  680. .n_banks = 2,
  681. {
  682. /* .bank[0] = { */
  683. {
  684. .probed = 0,
  685. .pChip = NULL,
  686. .pBank = NULL,
  687. .bank_number = 0,
  688. .base_address = FLASH_BANK0_BASE_SD,
  689. .controller_address = 0x400e0a00,
  690. .flash_wait_states = 6, /* workaround silicon bug */
  691. .present = 1,
  692. .size_bytes = 256 * 1024,
  693. .nsectors = 16,
  694. .sector_size = 16384,
  695. .page_size = 256,
  696. },
  697. /* .bank[1] = { */
  698. {
  699. .probed = 0,
  700. .pChip = NULL,
  701. .pBank = NULL,
  702. .bank_number = 1,
  703. .base_address = FLASH_BANK1_BASE_512K_SD,
  704. .controller_address = 0x400e0a00,
  705. .flash_wait_states = 6, /* workaround silicon bug */
  706. .present = 1,
  707. .size_bytes = 256 * 1024,
  708. .nsectors = 16,
  709. .sector_size = 16384,
  710. .page_size = 256,
  711. },
  712. },
  713. },
  714. {
  715. .chipid_cidr = 0x288A0760,
  716. .name = "at91sam3s2a",
  717. .total_flash_size = 128 * 1024,
  718. .total_sram_size = 32 * 1024,
  719. .n_gpnvms = 2,
  720. .n_banks = 1,
  721. {
  722. /* .bank[0] = { */
  723. {
  724. .probed = 0,
  725. .pChip = NULL,
  726. .pBank = NULL,
  727. .bank_number = 0,
  728. .base_address = FLASH_BANK_BASE_S,
  729. .controller_address = 0x400e0a00,
  730. .flash_wait_states = 6, /* workaround silicon bug */
  731. .present = 1,
  732. .size_bytes = 128 * 1024,
  733. .nsectors = 8,
  734. .sector_size = 16384,
  735. .page_size = 256,
  736. },
  737. /* .bank[1] = { */
  738. {
  739. .present = 0,
  740. .probed = 0,
  741. .bank_number = 1,
  742. },
  743. },
  744. },
  745. {
  746. .chipid_cidr = 0x28A90560,
  747. .name = "at91sam3s1c",
  748. .total_flash_size = 64 * 1024,
  749. .total_sram_size = 16 * 1024,
  750. .n_gpnvms = 2,
  751. .n_banks = 1,
  752. {
  753. /* .bank[0] = { */
  754. {
  755. .probed = 0,
  756. .pChip = NULL,
  757. .pBank = NULL,
  758. .bank_number = 0,
  759. .base_address = FLASH_BANK_BASE_S,
  760. .controller_address = 0x400e0a00,
  761. .flash_wait_states = 6, /* workaround silicon bug */
  762. .present = 1,
  763. .size_bytes = 64 * 1024,
  764. .nsectors = 4,
  765. .sector_size = 16384,
  766. .page_size = 256,
  767. },
  768. /* .bank[1] = { */
  769. {
  770. .present = 0,
  771. .probed = 0,
  772. .bank_number = 1,
  773. },
  774. },
  775. },
  776. {
  777. .chipid_cidr = 0x28990560,
  778. .name = "at91sam3s1b",
  779. .total_flash_size = 64 * 1024,
  780. .total_sram_size = 16 * 1024,
  781. .n_gpnvms = 2,
  782. .n_banks = 1,
  783. {
  784. /* .bank[0] = { */
  785. {
  786. .probed = 0,
  787. .pChip = NULL,
  788. .pBank = NULL,
  789. .bank_number = 0,
  790. .base_address = FLASH_BANK_BASE_S,
  791. .controller_address = 0x400e0a00,
  792. .flash_wait_states = 6, /* workaround silicon bug */
  793. .present = 1,
  794. .size_bytes = 64 * 1024,
  795. .nsectors = 4,
  796. .sector_size = 16384,
  797. .page_size = 256,
  798. },
  799. /* .bank[1] = { */
  800. {
  801. .present = 0,
  802. .probed = 0,
  803. .bank_number = 1,
  804. },
  805. },
  806. },
  807. {
  808. .chipid_cidr = 0x28890560,
  809. .name = "at91sam3s1a",
  810. .total_flash_size = 64 * 1024,
  811. .total_sram_size = 16 * 1024,
  812. .n_gpnvms = 2,
  813. .n_banks = 1,
  814. {
  815. /* .bank[0] = { */
  816. {
  817. .probed = 0,
  818. .pChip = NULL,
  819. .pBank = NULL,
  820. .bank_number = 0,
  821. .base_address = FLASH_BANK_BASE_S,
  822. .controller_address = 0x400e0a00,
  823. .flash_wait_states = 6, /* workaround silicon bug */
  824. .present = 1,
  825. .size_bytes = 64 * 1024,
  826. .nsectors = 4,
  827. .sector_size = 16384,
  828. .page_size = 256,
  829. },
  830. /* .bank[1] = { */
  831. {
  832. .present = 0,
  833. .probed = 0,
  834. .bank_number = 1,
  835. },
  836. },
  837. },
  838. /* Start at91sam3n* series */
  839. {
  840. .chipid_cidr = 0x29540960,
  841. .name = "at91sam3n4c",
  842. .total_flash_size = 256 * 1024,
  843. .total_sram_size = 24 * 1024,
  844. .n_gpnvms = 3,
  845. .n_banks = 1,
  846. /* System boots at address 0x0 */
  847. /* gpnvm[1] = selects boot code */
  848. /* if gpnvm[1] == 0 */
  849. /* boot is via "SAMBA" (rom) */
  850. /* else */
  851. /* boot is via FLASH */
  852. /* Selection is via gpnvm[2] */
  853. /* endif */
  854. /* */
  855. /* NOTE: banks 0 & 1 switch places */
  856. /* if gpnvm[2] == 0 */
  857. /* Bank0 is the boot rom */
  858. /* else */
  859. /* Bank1 is the boot rom */
  860. /* endif */
  861. /* .bank[0] = { */
  862. {
  863. {
  864. .probed = 0,
  865. .pChip = NULL,
  866. .pBank = NULL,
  867. .bank_number = 0,
  868. .base_address = FLASH_BANK_BASE_N,
  869. .controller_address = 0x400e0A00,
  870. .flash_wait_states = 6, /* workaround silicon bug */
  871. .present = 1,
  872. .size_bytes = 256 * 1024,
  873. .nsectors = 16,
  874. .sector_size = 16384,
  875. .page_size = 256,
  876. },
  877. /* .bank[1] = { */
  878. {
  879. .present = 0,
  880. .probed = 0,
  881. .bank_number = 1,
  882. },
  883. },
  884. },
  885. {
  886. .chipid_cidr = 0x29440960,
  887. .name = "at91sam3n4b",
  888. .total_flash_size = 256 * 1024,
  889. .total_sram_size = 24 * 1024,
  890. .n_gpnvms = 3,
  891. .n_banks = 1,
  892. /* System boots at address 0x0 */
  893. /* gpnvm[1] = selects boot code */
  894. /* if gpnvm[1] == 0 */
  895. /* boot is via "SAMBA" (rom) */
  896. /* else */
  897. /* boot is via FLASH */
  898. /* Selection is via gpnvm[2] */
  899. /* endif */
  900. /* */
  901. /* NOTE: banks 0 & 1 switch places */
  902. /* if gpnvm[2] == 0 */
  903. /* Bank0 is the boot rom */
  904. /* else */
  905. /* Bank1 is the boot rom */
  906. /* endif */
  907. /* .bank[0] = { */
  908. {
  909. {
  910. .probed = 0,
  911. .pChip = NULL,
  912. .pBank = NULL,
  913. .bank_number = 0,
  914. .base_address = FLASH_BANK_BASE_N,
  915. .controller_address = 0x400e0A00,
  916. .flash_wait_states = 6, /* workaround silicon bug */
  917. .present = 1,
  918. .size_bytes = 256 * 1024,
  919. .nsectors = 16,
  920. .sector_size = 16384,
  921. .page_size = 256,
  922. },
  923. /* .bank[1] = { */
  924. {
  925. .present = 0,
  926. .probed = 0,
  927. .bank_number = 1,
  928. },
  929. },
  930. },
  931. {
  932. .chipid_cidr = 0x29340960,
  933. .name = "at91sam3n4a",
  934. .total_flash_size = 256 * 1024,
  935. .total_sram_size = 24 * 1024,
  936. .n_gpnvms = 3,
  937. .n_banks = 1,
  938. /* System boots at address 0x0 */
  939. /* gpnvm[1] = selects boot code */
  940. /* if gpnvm[1] == 0 */
  941. /* boot is via "SAMBA" (rom) */
  942. /* else */
  943. /* boot is via FLASH */
  944. /* Selection is via gpnvm[2] */
  945. /* endif */
  946. /* */
  947. /* NOTE: banks 0 & 1 switch places */
  948. /* if gpnvm[2] == 0 */
  949. /* Bank0 is the boot rom */
  950. /* else */
  951. /* Bank1 is the boot rom */
  952. /* endif */
  953. /* .bank[0] = { */
  954. {
  955. {
  956. .probed = 0,
  957. .pChip = NULL,
  958. .pBank = NULL,
  959. .bank_number = 0,
  960. .base_address = FLASH_BANK_BASE_N,
  961. .controller_address = 0x400e0A00,
  962. .flash_wait_states = 6, /* workaround silicon bug */
  963. .present = 1,
  964. .size_bytes = 256 * 1024,
  965. .nsectors = 16,
  966. .sector_size = 16384,
  967. .page_size = 256,
  968. },
  969. /* .bank[1] = { */
  970. {
  971. .present = 0,
  972. .probed = 0,
  973. .bank_number = 1,
  974. },
  975. },
  976. },
  977. {
  978. .chipid_cidr = 0x29590760,
  979. .name = "at91sam3n2c",
  980. .total_flash_size = 128 * 1024,
  981. .total_sram_size = 16 * 1024,
  982. .n_gpnvms = 3,
  983. .n_banks = 1,
  984. /* System boots at address 0x0 */
  985. /* gpnvm[1] = selects boot code */
  986. /* if gpnvm[1] == 0 */
  987. /* boot is via "SAMBA" (rom) */
  988. /* else */
  989. /* boot is via FLASH */
  990. /* Selection is via gpnvm[2] */
  991. /* endif */
  992. /* */
  993. /* NOTE: banks 0 & 1 switch places */
  994. /* if gpnvm[2] == 0 */
  995. /* Bank0 is the boot rom */
  996. /* else */
  997. /* Bank1 is the boot rom */
  998. /* endif */
  999. /* .bank[0] = { */
  1000. {
  1001. {
  1002. .probed = 0,
  1003. .pChip = NULL,
  1004. .pBank = NULL,
  1005. .bank_number = 0,
  1006. .base_address = FLASH_BANK_BASE_N,
  1007. .controller_address = 0x400e0A00,
  1008. .flash_wait_states = 6, /* workaround silicon bug */
  1009. .present = 1,
  1010. .size_bytes = 128 * 1024,
  1011. .nsectors = 8,
  1012. .sector_size = 16384,
  1013. .page_size = 256,
  1014. },
  1015. /* .bank[1] = { */
  1016. {
  1017. .present = 0,
  1018. .probed = 0,
  1019. .bank_number = 1,
  1020. },
  1021. },
  1022. },
  1023. {
  1024. .chipid_cidr = 0x29490760,
  1025. .name = "at91sam3n2b",
  1026. .total_flash_size = 128 * 1024,
  1027. .total_sram_size = 16 * 1024,
  1028. .n_gpnvms = 3,
  1029. .n_banks = 1,
  1030. /* System boots at address 0x0 */
  1031. /* gpnvm[1] = selects boot code */
  1032. /* if gpnvm[1] == 0 */
  1033. /* boot is via "SAMBA" (rom) */
  1034. /* else */
  1035. /* boot is via FLASH */
  1036. /* Selection is via gpnvm[2] */
  1037. /* endif */
  1038. /* */
  1039. /* NOTE: banks 0 & 1 switch places */
  1040. /* if gpnvm[2] == 0 */
  1041. /* Bank0 is the boot rom */
  1042. /* else */
  1043. /* Bank1 is the boot rom */
  1044. /* endif */
  1045. /* .bank[0] = { */
  1046. {
  1047. {
  1048. .probed = 0,
  1049. .pChip = NULL,
  1050. .pBank = NULL,
  1051. .bank_number = 0,
  1052. .base_address = FLASH_BANK_BASE_N,
  1053. .controller_address = 0x400e0A00,
  1054. .flash_wait_states = 6, /* workaround silicon bug */
  1055. .present = 1,
  1056. .size_bytes = 128 * 1024,
  1057. .nsectors = 8,
  1058. .sector_size = 16384,
  1059. .page_size = 256,
  1060. },
  1061. /* .bank[1] = { */
  1062. {
  1063. .present = 0,
  1064. .probed = 0,
  1065. .bank_number = 1,
  1066. },
  1067. },
  1068. },
  1069. {
  1070. .chipid_cidr = 0x29390760,
  1071. .name = "at91sam3n2a",
  1072. .total_flash_size = 128 * 1024,
  1073. .total_sram_size = 16 * 1024,
  1074. .n_gpnvms = 3,
  1075. .n_banks = 1,
  1076. /* System boots at address 0x0 */
  1077. /* gpnvm[1] = selects boot code */
  1078. /* if gpnvm[1] == 0 */
  1079. /* boot is via "SAMBA" (rom) */
  1080. /* else */
  1081. /* boot is via FLASH */
  1082. /* Selection is via gpnvm[2] */
  1083. /* endif */
  1084. /* */
  1085. /* NOTE: banks 0 & 1 switch places */
  1086. /* if gpnvm[2] == 0 */
  1087. /* Bank0 is the boot rom */
  1088. /* else */
  1089. /* Bank1 is the boot rom */
  1090. /* endif */
  1091. /* .bank[0] = { */
  1092. {
  1093. {
  1094. .probed = 0,
  1095. .pChip = NULL,
  1096. .pBank = NULL,
  1097. .bank_number = 0,
  1098. .base_address = FLASH_BANK_BASE_N,
  1099. .controller_address = 0x400e0A00,
  1100. .flash_wait_states = 6, /* workaround silicon bug */
  1101. .present = 1,
  1102. .size_bytes = 128 * 1024,
  1103. .nsectors = 8,
  1104. .sector_size = 16384,
  1105. .page_size = 256,
  1106. },
  1107. /* .bank[1] = { */
  1108. {
  1109. .present = 0,
  1110. .probed = 0,
  1111. .bank_number = 1,
  1112. },
  1113. },
  1114. },
  1115. {
  1116. .chipid_cidr = 0x29580560,
  1117. .name = "at91sam3n1c",
  1118. .total_flash_size = 64 * 1024,
  1119. .total_sram_size = 8 * 1024,
  1120. .n_gpnvms = 3,
  1121. .n_banks = 1,
  1122. /* System boots at address 0x0 */
  1123. /* gpnvm[1] = selects boot code */
  1124. /* if gpnvm[1] == 0 */
  1125. /* boot is via "SAMBA" (rom) */
  1126. /* else */
  1127. /* boot is via FLASH */
  1128. /* Selection is via gpnvm[2] */
  1129. /* endif */
  1130. /* */
  1131. /* NOTE: banks 0 & 1 switch places */
  1132. /* if gpnvm[2] == 0 */
  1133. /* Bank0 is the boot rom */
  1134. /* else */
  1135. /* Bank1 is the boot rom */
  1136. /* endif */
  1137. /* .bank[0] = { */
  1138. {
  1139. {
  1140. .probed = 0,
  1141. .pChip = NULL,
  1142. .pBank = NULL,
  1143. .bank_number = 0,
  1144. .base_address = FLASH_BANK_BASE_N,
  1145. .controller_address = 0x400e0A00,
  1146. .flash_wait_states = 6, /* workaround silicon bug */
  1147. .present = 1,
  1148. .size_bytes = 64 * 1024,
  1149. .nsectors = 4,
  1150. .sector_size = 16384,
  1151. .page_size = 256,
  1152. },
  1153. /* .bank[1] = { */
  1154. {
  1155. .present = 0,
  1156. .probed = 0,
  1157. .bank_number = 1,
  1158. },
  1159. },
  1160. },
  1161. {
  1162. .chipid_cidr = 0x29480560,
  1163. .name = "at91sam3n1b",
  1164. .total_flash_size = 64 * 1024,
  1165. .total_sram_size = 8 * 1024,
  1166. .n_gpnvms = 3,
  1167. .n_banks = 1,
  1168. /* System boots at address 0x0 */
  1169. /* gpnvm[1] = selects boot code */
  1170. /* if gpnvm[1] == 0 */
  1171. /* boot is via "SAMBA" (rom) */
  1172. /* else */
  1173. /* boot is via FLASH */
  1174. /* Selection is via gpnvm[2] */
  1175. /* endif */
  1176. /* */
  1177. /* NOTE: banks 0 & 1 switch places */
  1178. /* if gpnvm[2] == 0 */
  1179. /* Bank0 is the boot rom */
  1180. /* else */
  1181. /* Bank1 is the boot rom */
  1182. /* endif */
  1183. /* .bank[0] = { */
  1184. {
  1185. {
  1186. .probed = 0,
  1187. .pChip = NULL,
  1188. .pBank = NULL,
  1189. .bank_number = 0,
  1190. .base_address = FLASH_BANK_BASE_N,
  1191. .controller_address = 0x400e0A00,
  1192. .flash_wait_states = 6, /* workaround silicon bug */
  1193. .present = 1,
  1194. .size_bytes = 64 * 1024,
  1195. .nsectors = 4,
  1196. .sector_size = 16384,
  1197. .page_size = 256,
  1198. },
  1199. /* .bank[1] = { */
  1200. {
  1201. .present = 0,
  1202. .probed = 0,
  1203. .bank_number = 1,
  1204. },
  1205. },
  1206. },
  1207. {
  1208. .chipid_cidr = 0x29380560,
  1209. .name = "at91sam3n1a",
  1210. .total_flash_size = 64 * 1024,
  1211. .total_sram_size = 8 * 1024,
  1212. .n_gpnvms = 3,
  1213. .n_banks = 1,
  1214. /* System boots at address 0x0 */
  1215. /* gpnvm[1] = selects boot code */
  1216. /* if gpnvm[1] == 0 */
  1217. /* boot is via "SAMBA" (rom) */
  1218. /* else */
  1219. /* boot is via FLASH */
  1220. /* Selection is via gpnvm[2] */
  1221. /* endif */
  1222. /* */
  1223. /* NOTE: banks 0 & 1 switch places */
  1224. /* if gpnvm[2] == 0 */
  1225. /* Bank0 is the boot rom */
  1226. /* else */
  1227. /* Bank1 is the boot rom */
  1228. /* endif */
  1229. /* .bank[0] = { */
  1230. {
  1231. {
  1232. .probed = 0,
  1233. .pChip = NULL,
  1234. .pBank = NULL,
  1235. .bank_number = 0,
  1236. .base_address = FLASH_BANK_BASE_N,
  1237. .controller_address = 0x400e0A00,
  1238. .flash_wait_states = 6, /* workaround silicon bug */
  1239. .present = 1,
  1240. .size_bytes = 64 * 1024,
  1241. .nsectors = 4,
  1242. .sector_size = 16384,
  1243. .page_size = 256,
  1244. },
  1245. /* .bank[1] = { */
  1246. {
  1247. .present = 0,
  1248. .probed = 0,
  1249. .bank_number = 1,
  1250. },
  1251. },
  1252. },
  1253. /* Start at91sam3a series*/
  1254. /* System boots at address 0x0 */
  1255. /* gpnvm[1] = selects boot code */
  1256. /* if gpnvm[1] == 0 */
  1257. /* boot is via "SAMBA" (rom) */
  1258. /* else */
  1259. /* boot is via FLASH */
  1260. /* Selection is via gpnvm[2] */
  1261. /* endif */
  1262. /* */
  1263. /* NOTE: banks 0 & 1 switch places */
  1264. /* if gpnvm[2] == 0 */
  1265. /* Bank0 is the boot rom */
  1266. /* else */
  1267. /* Bank1 is the boot rom */
  1268. /* endif */
  1269. {
  1270. .chipid_cidr = 0x283E0A60,
  1271. .name = "at91sam3a8c",
  1272. .total_flash_size = 512 * 1024,
  1273. .total_sram_size = 96 * 1024,
  1274. .n_gpnvms = 3,
  1275. .n_banks = 2,
  1276. {
  1277. /* .bank[0] = { */
  1278. {
  1279. .probed = 0,
  1280. .pChip = NULL,
  1281. .pBank = NULL,
  1282. .bank_number = 0,
  1283. .base_address = FLASH_BANK0_BASE_AX,
  1284. .controller_address = 0x400e0a00,
  1285. .flash_wait_states = 6, /* workaround silicon bug */
  1286. .present = 1,
  1287. .size_bytes = 256 * 1024,
  1288. .nsectors = 16,
  1289. .sector_size = 16384,
  1290. .page_size = 256,
  1291. },
  1292. /* .bank[1] = { */
  1293. {
  1294. .probed = 0,
  1295. .pChip = NULL,
  1296. .pBank = NULL,
  1297. .bank_number = 1,
  1298. .base_address = FLASH_BANK1_BASE_512K_AX,
  1299. .controller_address = 0x400e0c00,
  1300. .flash_wait_states = 6, /* workaround silicon bug */
  1301. .present = 1,
  1302. .size_bytes = 256 * 1024,
  1303. .nsectors = 16,
  1304. .sector_size = 16384,
  1305. .page_size = 256,
  1306. },
  1307. },
  1308. },
  1309. {
  1310. .chipid_cidr = 0x283B0960,
  1311. .name = "at91sam3a4c",
  1312. .total_flash_size = 256 * 1024,
  1313. .total_sram_size = 64 * 1024,
  1314. .n_gpnvms = 3,
  1315. .n_banks = 2,
  1316. {
  1317. /* .bank[0] = { */
  1318. {
  1319. .probed = 0,
  1320. .pChip = NULL,
  1321. .pBank = NULL,
  1322. .bank_number = 0,
  1323. .base_address = FLASH_BANK0_BASE_AX,
  1324. .controller_address = 0x400e0a00,
  1325. .flash_wait_states = 6, /* workaround silicon bug */
  1326. .present = 1,
  1327. .size_bytes = 128 * 1024,
  1328. .nsectors = 8,
  1329. .sector_size = 16384,
  1330. .page_size = 256,
  1331. },
  1332. /* .bank[1] = { */
  1333. {
  1334. .probed = 0,
  1335. .pChip = NULL,
  1336. .pBank = NULL,
  1337. .bank_number = 1,
  1338. .base_address = FLASH_BANK1_BASE_256K_AX,
  1339. .controller_address = 0x400e0c00,
  1340. .flash_wait_states = 6, /* workaround silicon bug */
  1341. .present = 1,
  1342. .size_bytes = 128 * 1024,
  1343. .nsectors = 8,
  1344. .sector_size = 16384,
  1345. .page_size = 256,
  1346. },
  1347. },
  1348. },
  1349. /* Start at91sam3x* series */
  1350. /* System boots at address 0x0 */
  1351. /* gpnvm[1] = selects boot code */
  1352. /* if gpnvm[1] == 0 */
  1353. /* boot is via "SAMBA" (rom) */
  1354. /* else */
  1355. /* boot is via FLASH */
  1356. /* Selection is via gpnvm[2] */
  1357. /* endif */
  1358. /* */
  1359. /* NOTE: banks 0 & 1 switch places */
  1360. /* if gpnvm[2] == 0 */
  1361. /* Bank0 is the boot rom */
  1362. /* else */
  1363. /* Bank1 is the boot rom */
  1364. /* endif */
  1365. /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
  1366. {
  1367. .chipid_cidr = 0x286E0A20,
  1368. .name = "at91sam3x8h - ES",
  1369. .total_flash_size = 512 * 1024,
  1370. .total_sram_size = 96 * 1024,
  1371. .n_gpnvms = 3,
  1372. .n_banks = 2,
  1373. {
  1374. /* .bank[0] = { */
  1375. {
  1376. .probed = 0,
  1377. .pChip = NULL,
  1378. .pBank = NULL,
  1379. .bank_number = 0,
  1380. .base_address = FLASH_BANK0_BASE_AX,
  1381. .controller_address = 0x400e0a00,
  1382. .flash_wait_states = 6, /* workaround silicon bug */
  1383. .present = 1,
  1384. .size_bytes = 256 * 1024,
  1385. .nsectors = 16,
  1386. .sector_size = 16384,
  1387. .page_size = 256,
  1388. },
  1389. /* .bank[1] = { */
  1390. {
  1391. .probed = 0,
  1392. .pChip = NULL,
  1393. .pBank = NULL,
  1394. .bank_number = 1,
  1395. .base_address = FLASH_BANK1_BASE_512K_AX,
  1396. .controller_address = 0x400e0c00,
  1397. .flash_wait_states = 6, /* workaround silicon bug */
  1398. .present = 1,
  1399. .size_bytes = 256 * 1024,
  1400. .nsectors = 16,
  1401. .sector_size = 16384,
  1402. .page_size = 256,
  1403. },
  1404. },
  1405. },
  1406. /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
  1407. {
  1408. .chipid_cidr = 0x286E0A60,
  1409. .name = "at91sam3x8h",
  1410. .total_flash_size = 512 * 1024,
  1411. .total_sram_size = 96 * 1024,
  1412. .n_gpnvms = 3,
  1413. .n_banks = 2,
  1414. {
  1415. /* .bank[0] = { */
  1416. {
  1417. .probed = 0,
  1418. .pChip = NULL,
  1419. .pBank = NULL,
  1420. .bank_number = 0,
  1421. .base_address = FLASH_BANK0_BASE_AX,
  1422. .controller_address = 0x400e0a00,
  1423. .flash_wait_states = 6, /* workaround silicon bug */
  1424. .present = 1,
  1425. .size_bytes = 256 * 1024,
  1426. .nsectors = 16,
  1427. .sector_size = 16384,
  1428. .page_size = 256,
  1429. },
  1430. /* .bank[1] = { */
  1431. {
  1432. .probed = 0,
  1433. .pChip = NULL,
  1434. .pBank = NULL,
  1435. .bank_number = 1,
  1436. .base_address = FLASH_BANK1_BASE_512K_AX,
  1437. .controller_address = 0x400e0c00,
  1438. .flash_wait_states = 6, /* workaround silicon bug */
  1439. .present = 1,
  1440. .size_bytes = 256 * 1024,
  1441. .nsectors = 16,
  1442. .sector_size = 16384,
  1443. .page_size = 256,
  1444. },
  1445. },
  1446. },
  1447. {
  1448. .chipid_cidr = 0x285E0A60,
  1449. .name = "at91sam3x8e",
  1450. .total_flash_size = 512 * 1024,
  1451. .total_sram_size = 96 * 1024,
  1452. .n_gpnvms = 3,
  1453. .n_banks = 2,
  1454. {
  1455. /* .bank[0] = { */
  1456. {
  1457. .probed = 0,
  1458. .pChip = NULL,
  1459. .pBank = NULL,
  1460. .bank_number = 0,
  1461. .base_address = FLASH_BANK0_BASE_AX,
  1462. .controller_address = 0x400e0a00,
  1463. .flash_wait_states = 6, /* workaround silicon bug */
  1464. .present = 1,
  1465. .size_bytes = 256 * 1024,
  1466. .nsectors = 16,
  1467. .sector_size = 16384,
  1468. .page_size = 256,
  1469. },
  1470. /* .bank[1] = { */
  1471. {
  1472. .probed = 0,
  1473. .pChip = NULL,
  1474. .pBank = NULL,
  1475. .bank_number = 1,
  1476. .base_address = FLASH_BANK1_BASE_512K_AX,
  1477. .controller_address = 0x400e0c00,
  1478. .flash_wait_states = 6, /* workaround silicon bug */
  1479. .present = 1,
  1480. .size_bytes = 256 * 1024,
  1481. .nsectors = 16,
  1482. .sector_size = 16384,
  1483. .page_size = 256,
  1484. },
  1485. },
  1486. },
  1487. {
  1488. .chipid_cidr = 0x284E0A60,
  1489. .name = "at91sam3x8c",
  1490. .total_flash_size = 512 * 1024,
  1491. .total_sram_size = 96 * 1024,
  1492. .n_gpnvms = 3,
  1493. .n_banks = 2,
  1494. {
  1495. /* .bank[0] = { */
  1496. {
  1497. .probed = 0,
  1498. .pChip = NULL,
  1499. .pBank = NULL,
  1500. .bank_number = 0,
  1501. .base_address = FLASH_BANK0_BASE_AX,
  1502. .controller_address = 0x400e0a00,
  1503. .flash_wait_states = 6, /* workaround silicon bug */
  1504. .present = 1,
  1505. .size_bytes = 256 * 1024,
  1506. .nsectors = 16,
  1507. .sector_size = 16384,
  1508. .page_size = 256,
  1509. },
  1510. /* .bank[1] = { */
  1511. {
  1512. .probed = 0,
  1513. .pChip = NULL,
  1514. .pBank = NULL,
  1515. .bank_number = 1,
  1516. .base_address = FLASH_BANK1_BASE_512K_AX ,
  1517. .controller_address = 0x400e0c00,
  1518. .flash_wait_states = 6, /* workaround silicon bug */
  1519. .present = 1,
  1520. .size_bytes = 256 * 1024,
  1521. .nsectors = 16,
  1522. .sector_size = 16384,
  1523. .page_size = 256,
  1524. },
  1525. },
  1526. },
  1527. {
  1528. .chipid_cidr = 0x285B0960,
  1529. .name = "at91sam3x4e",
  1530. .total_flash_size = 256 * 1024,
  1531. .total_sram_size = 64 * 1024,
  1532. .n_gpnvms = 3,
  1533. .n_banks = 2,
  1534. {
  1535. /* .bank[0] = { */
  1536. {
  1537. .probed = 0,
  1538. .pChip = NULL,
  1539. .pBank = NULL,
  1540. .bank_number = 0,
  1541. .base_address = FLASH_BANK0_BASE_AX,
  1542. .controller_address = 0x400e0a00,
  1543. .flash_wait_states = 6, /* workaround silicon bug */
  1544. .present = 1,
  1545. .size_bytes = 128 * 1024,
  1546. .nsectors = 8,
  1547. .sector_size = 16384,
  1548. .page_size = 256,
  1549. },
  1550. /* .bank[1] = { */
  1551. {
  1552. .probed = 0,
  1553. .pChip = NULL,
  1554. .pBank = NULL,
  1555. .bank_number = 1,
  1556. .base_address = FLASH_BANK1_BASE_256K_AX,
  1557. .controller_address = 0x400e0c00,
  1558. .flash_wait_states = 6, /* workaround silicon bug */
  1559. .present = 1,
  1560. .size_bytes = 128 * 1024,
  1561. .nsectors = 8,
  1562. .sector_size = 16384,
  1563. .page_size = 256,
  1564. },
  1565. },
  1566. },
  1567. {
  1568. .chipid_cidr = 0x284B0960,
  1569. .name = "at91sam3x4c",
  1570. .total_flash_size = 256 * 1024,
  1571. .total_sram_size = 64 * 1024,
  1572. .n_gpnvms = 3,
  1573. .n_banks = 2,
  1574. {
  1575. /* .bank[0] = { */
  1576. {
  1577. .probed = 0,
  1578. .pChip = NULL,
  1579. .pBank = NULL,
  1580. .bank_number = 0,
  1581. .base_address = FLASH_BANK0_BASE_AX,
  1582. .controller_address = 0x400e0a00,
  1583. .flash_wait_states = 6, /* workaround silicon bug */
  1584. .present = 1,
  1585. .size_bytes = 128 * 1024,
  1586. .nsectors = 8,
  1587. .sector_size = 16384,
  1588. .page_size = 256,
  1589. },
  1590. /* .bank[1] = { */
  1591. {
  1592. .probed = 0,
  1593. .pChip = NULL,
  1594. .pBank = NULL,
  1595. .bank_number = 1,
  1596. .base_address = FLASH_BANK1_BASE_256K_AX,
  1597. .controller_address = 0x400e0c00,
  1598. .flash_wait_states = 6, /* workaround silicon bug */
  1599. .present = 1,
  1600. .size_bytes = 128 * 1024,
  1601. .nsectors = 8,
  1602. .sector_size = 16384,
  1603. .page_size = 256,
  1604. },
  1605. },
  1606. },
  1607. /* terminate */
  1608. {
  1609. .chipid_cidr = 0,
  1610. .name = NULL,
  1611. }
  1612. };
  1613. /* Globals above */
  1614. /***********************************************************************
  1615. **********************************************************************
  1616. **********************************************************************
  1617. **********************************************************************
  1618. **********************************************************************
  1619. **********************************************************************/
  1620. /* *ATMEL* style code - from the SAM3 driver code */
  1621. /**
  1622. * Get the current status of the EEFC and
  1623. * the value of some status bits (LOCKE, PROGE).
  1624. * @param pPrivate - info about the bank
  1625. * @param v - result goes here
  1626. */
  1627. static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
  1628. {
  1629. int r;
  1630. r = target_read_u32(pPrivate->pChip->target,
  1631. pPrivate->controller_address + offset_EFC_FSR,
  1632. v);
  1633. LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
  1634. (unsigned int)(*v),
  1635. ((unsigned int)((*v >> 2) & 1)),
  1636. ((unsigned int)((*v >> 1) & 1)),
  1637. ((unsigned int)((*v >> 0) & 1)));
  1638. return r;
  1639. }
  1640. /**
  1641. * Get the result of the last executed command.
  1642. * @param pPrivate - info about the bank
  1643. * @param v - result goes here
  1644. */
  1645. static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
  1646. {
  1647. int r;
  1648. uint32_t rv;
  1649. r = target_read_u32(pPrivate->pChip->target,
  1650. pPrivate->controller_address + offset_EFC_FRR,
  1651. &rv);
  1652. if (v)
  1653. *v = rv;
  1654. LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
  1655. return r;
  1656. }
  1657. static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
  1658. unsigned command, unsigned argument)
  1659. {
  1660. uint32_t n, v;
  1661. int r;
  1662. int retry;
  1663. retry = 0;
  1664. do_retry:
  1665. /* Check command & argument */
  1666. switch (command) {
  1667. case AT91C_EFC_FCMD_WP:
  1668. case AT91C_EFC_FCMD_WPL:
  1669. case AT91C_EFC_FCMD_EWP:
  1670. case AT91C_EFC_FCMD_EWPL:
  1671. /* case AT91C_EFC_FCMD_EPL: */
  1672. /* case AT91C_EFC_FCMD_EPA: */
  1673. case AT91C_EFC_FCMD_SLB:
  1674. case AT91C_EFC_FCMD_CLB:
  1675. n = (pPrivate->size_bytes / pPrivate->page_size);
  1676. if (argument >= n)
  1677. LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
  1678. break;
  1679. case AT91C_EFC_FCMD_SFB:
  1680. case AT91C_EFC_FCMD_CFB:
  1681. if (argument >= pPrivate->pChip->details.n_gpnvms) {
  1682. LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
  1683. pPrivate->pChip->details.n_gpnvms);
  1684. }
  1685. break;
  1686. case AT91C_EFC_FCMD_GETD:
  1687. case AT91C_EFC_FCMD_EA:
  1688. case AT91C_EFC_FCMD_GLB:
  1689. case AT91C_EFC_FCMD_GFB:
  1690. case AT91C_EFC_FCMD_STUI:
  1691. case AT91C_EFC_FCMD_SPUI:
  1692. if (argument != 0)
  1693. LOG_ERROR("Argument is meaningless for cmd: %d", command);
  1694. break;
  1695. default:
  1696. LOG_ERROR("Unknown command %d", command);
  1697. break;
  1698. }
  1699. if (command == AT91C_EFC_FCMD_SPUI) {
  1700. /* this is a very special situation. */
  1701. /* Situation (1) - error/retry - see below */
  1702. /* And we are being called recursively */
  1703. /* Situation (2) - normal, finished reading unique id */
  1704. } else {
  1705. /* it should be "ready" */
  1706. EFC_GetStatus(pPrivate, &v);
  1707. if (v & 1) {
  1708. /* then it is ready */
  1709. /* we go on */
  1710. } else {
  1711. if (retry) {
  1712. /* we have done this before */
  1713. /* the controller is not responding. */
  1714. LOG_ERROR("flash controller(%d) is not ready! Error",
  1715. pPrivate->bank_number);
  1716. return ERROR_FAIL;
  1717. } else {
  1718. retry++;
  1719. LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
  1720. pPrivate->bank_number);
  1721. /* we do that by issuing the *STOP* command */
  1722. EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
  1723. /* above is recursive, and further recursion is blocked by */
  1724. /* if (command == AT91C_EFC_FCMD_SPUI) above */
  1725. goto do_retry;
  1726. }
  1727. }
  1728. }
  1729. v = (0x5A << 24) | (argument << 8) | command;
  1730. LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
  1731. r = target_write_u32(pPrivate->pBank->target,
  1732. pPrivate->controller_address + offset_EFC_FCR, v);
  1733. if (r != ERROR_OK)
  1734. LOG_DEBUG("Error Write failed");
  1735. return r;
  1736. }
  1737. /**
  1738. * Performs the given command and wait until its completion (or an error).
  1739. * @param pPrivate - info about the bank
  1740. * @param command - Command to perform.
  1741. * @param argument - Optional command argument.
  1742. * @param status - put command status bits here
  1743. */
  1744. static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
  1745. unsigned command,
  1746. unsigned argument,
  1747. uint32_t *status)
  1748. {
  1749. int r;
  1750. uint32_t v;
  1751. long long ms_now, ms_end;
  1752. /* default */
  1753. if (status)
  1754. *status = 0;
  1755. r = EFC_StartCommand(pPrivate, command, argument);
  1756. if (r != ERROR_OK)
  1757. return r;
  1758. ms_end = 500 + timeval_ms();
  1759. do {
  1760. r = EFC_GetStatus(pPrivate, &v);
  1761. if (r != ERROR_OK)
  1762. return r;
  1763. ms_now = timeval_ms();
  1764. if (ms_now > ms_end) {
  1765. /* error */
  1766. LOG_ERROR("Command timeout");
  1767. return ERROR_FAIL;
  1768. }
  1769. } while ((v & 1) == 0);
  1770. /* error bits.. */
  1771. if (status)
  1772. *status = (v & 0x6);
  1773. return ERROR_OK;
  1774. }
  1775. /**
  1776. * Read the unique ID.
  1777. * @param pPrivate - info about the bank
  1778. * The unique ID is stored in the 'pPrivate' structure.
  1779. */
  1780. static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
  1781. {
  1782. int r;
  1783. uint32_t v;
  1784. int x;
  1785. /* assume 0 */
  1786. pPrivate->pChip->cfg.unique_id[0] = 0;
  1787. pPrivate->pChip->cfg.unique_id[1] = 0;
  1788. pPrivate->pChip->cfg.unique_id[2] = 0;
  1789. pPrivate->pChip->cfg.unique_id[3] = 0;
  1790. LOG_DEBUG("Begin");
  1791. r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
  1792. if (r < 0)
  1793. return r;
  1794. for (x = 0; x < 4; x++) {
  1795. r = target_read_u32(pPrivate->pChip->target,
  1796. pPrivate->pBank->base + (x * 4),
  1797. &v);
  1798. if (r < 0)
  1799. return r;
  1800. pPrivate->pChip->cfg.unique_id[x] = v;
  1801. }
  1802. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
  1803. LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
  1804. r,
  1805. (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
  1806. (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
  1807. (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
  1808. (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
  1809. return r;
  1810. }
  1811. /**
  1812. * Erases the entire flash.
  1813. * @param pPrivate - the info about the bank.
  1814. */
  1815. static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
  1816. {
  1817. LOG_DEBUG("Here");
  1818. return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
  1819. }
  1820. /**
  1821. * Gets current GPNVM state.
  1822. * @param pPrivate - info about the bank.
  1823. * @param gpnvm - GPNVM bit index.
  1824. * @param puthere - result stored here.
  1825. */
  1826. /* ------------------------------------------------------------------------------ */
  1827. static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
  1828. {
  1829. uint32_t v;
  1830. int r;
  1831. LOG_DEBUG("Here");
  1832. if (pPrivate->bank_number != 0) {
  1833. LOG_ERROR("GPNVM only works with Bank0");
  1834. return ERROR_FAIL;
  1835. }
  1836. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1837. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1838. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1839. return ERROR_FAIL;
  1840. }
  1841. /* Get GPNVMs status */
  1842. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
  1843. if (r != ERROR_OK) {
  1844. LOG_ERROR("Failed");
  1845. return r;
  1846. }
  1847. r = EFC_GetResult(pPrivate, &v);
  1848. if (puthere) {
  1849. /* Check if GPNVM is set */
  1850. /* get the bit and make it a 0/1 */
  1851. *puthere = (v >> gpnvm) & 1;
  1852. }
  1853. return r;
  1854. }
  1855. /**
  1856. * Clears the selected GPNVM bit.
  1857. * @param pPrivate info about the bank
  1858. * @param gpnvm GPNVM index.
  1859. * @returns 0 if successful; otherwise returns an error code.
  1860. */
  1861. static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
  1862. {
  1863. int r;
  1864. unsigned v;
  1865. LOG_DEBUG("Here");
  1866. if (pPrivate->bank_number != 0) {
  1867. LOG_ERROR("GPNVM only works with Bank0");
  1868. return ERROR_FAIL;
  1869. }
  1870. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1871. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1872. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1873. return ERROR_FAIL;
  1874. }
  1875. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  1876. if (r != ERROR_OK) {
  1877. LOG_DEBUG("Failed: %d", r);
  1878. return r;
  1879. }
  1880. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
  1881. LOG_DEBUG("End: %d", r);
  1882. return r;
  1883. }
  1884. /**
  1885. * Sets the selected GPNVM bit.
  1886. * @param pPrivate info about the bank
  1887. * @param gpnvm GPNVM index.
  1888. */
  1889. static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
  1890. {
  1891. int r;
  1892. unsigned v;
  1893. if (pPrivate->bank_number != 0) {
  1894. LOG_ERROR("GPNVM only works with Bank0");
  1895. return ERROR_FAIL;
  1896. }
  1897. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1898. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1899. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1900. return ERROR_FAIL;
  1901. }
  1902. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  1903. if (r != ERROR_OK)
  1904. return r;
  1905. if (v) {
  1906. /* already set */
  1907. r = ERROR_OK;
  1908. } else {
  1909. /* set it */
  1910. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
  1911. }
  1912. return r;
  1913. }
  1914. /**
  1915. * Returns a bit field (at most 64) of locked regions within a page.
  1916. * @param pPrivate info about the bank
  1917. * @param v where to store locked bits
  1918. */
  1919. static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
  1920. {
  1921. int r;
  1922. LOG_DEBUG("Here");
  1923. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
  1924. if (r == ERROR_OK)
  1925. r = EFC_GetResult(pPrivate, v);
  1926. LOG_DEBUG("End: %d", r);
  1927. return r;
  1928. }
  1929. /**
  1930. * Unlocks all the regions in the given address range.
  1931. * @param pPrivate info about the bank
  1932. * @param start_sector first sector to unlock
  1933. * @param end_sector last (inclusive) to unlock
  1934. */
  1935. static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
  1936. unsigned start_sector,
  1937. unsigned end_sector)
  1938. {
  1939. int r;
  1940. uint32_t status;
  1941. uint32_t pg;
  1942. uint32_t pages_per_sector;
  1943. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  1944. /* Unlock all pages */
  1945. while (start_sector <= end_sector) {
  1946. pg = start_sector * pages_per_sector;
  1947. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
  1948. if (r != ERROR_OK)
  1949. return r;
  1950. start_sector++;
  1951. }
  1952. return ERROR_OK;
  1953. }
  1954. /**
  1955. * Locks regions
  1956. * @param pPrivate - info about the bank
  1957. * @param start_sector - first sector to lock
  1958. * @param end_sector - last sector (inclusive) to lock
  1959. */
  1960. static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
  1961. unsigned start_sector,
  1962. unsigned end_sector)
  1963. {
  1964. uint32_t status;
  1965. uint32_t pg;
  1966. uint32_t pages_per_sector;
  1967. int r;
  1968. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  1969. /* Lock all pages */
  1970. while (start_sector <= end_sector) {
  1971. pg = start_sector * pages_per_sector;
  1972. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
  1973. if (r != ERROR_OK)
  1974. return r;
  1975. start_sector++;
  1976. }
  1977. return ERROR_OK;
  1978. }
  1979. /****** END SAM3 CODE ********/
  1980. /* begin helpful debug code */
  1981. /* print the fieldname, the field value, in dec & hex, and return field value */
  1982. static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
  1983. const char *regname,
  1984. uint32_t value,
  1985. unsigned shift,
  1986. unsigned width)
  1987. {
  1988. uint32_t v;
  1989. int hwidth, dwidth;
  1990. /* extract the field */
  1991. v = value >> shift;
  1992. v = v & ((1 << width)-1);
  1993. if (width <= 16) {
  1994. hwidth = 4;
  1995. dwidth = 5;
  1996. } else {
  1997. hwidth = 8;
  1998. dwidth = 12;
  1999. }
  2000. /* show the basics */
  2001. LOG_USER_N("\t%*s: %*d [0x%0*x] ",
  2002. REG_NAME_WIDTH, regname,
  2003. dwidth, v,
  2004. hwidth, v);
  2005. return v;
  2006. }
  2007. static const char _unknown[] = "unknown";
  2008. static const char *const eproc_names[] = {
  2009. _unknown, /* 0 */
  2010. "arm946es", /* 1 */
  2011. "arm7tdmi", /* 2 */
  2012. "cortex-m3", /* 3 */
  2013. "arm920t", /* 4 */
  2014. "arm926ejs", /* 5 */
  2015. _unknown, /* 6 */
  2016. _unknown, /* 7 */
  2017. _unknown, /* 8 */
  2018. _unknown, /* 9 */
  2019. _unknown, /* 10 */
  2020. _unknown, /* 11 */
  2021. _unknown, /* 12 */
  2022. _unknown, /* 13 */
  2023. _unknown, /* 14 */
  2024. _unknown, /* 15 */
  2025. };
  2026. #define nvpsize2 nvpsize /* these two tables are identical */
  2027. static const char *const nvpsize[] = {
  2028. "none", /* 0 */
  2029. "8K bytes", /* 1 */
  2030. "16K bytes", /* 2 */
  2031. "32K bytes", /* 3 */
  2032. _unknown, /* 4 */
  2033. "64K bytes", /* 5 */
  2034. _unknown, /* 6 */
  2035. "128K bytes", /* 7 */
  2036. _unknown, /* 8 */
  2037. "256K bytes", /* 9 */
  2038. "512K bytes", /* 10 */
  2039. _unknown, /* 11 */
  2040. "1024K bytes", /* 12 */
  2041. _unknown, /* 13 */
  2042. "2048K bytes", /* 14 */
  2043. _unknown, /* 15 */
  2044. };
  2045. static const char *const sramsize[] = {
  2046. "48K Bytes", /* 0 */
  2047. "1K Bytes", /* 1 */
  2048. "2K Bytes", /* 2 */
  2049. "6K Bytes", /* 3 */
  2050. "112K Bytes", /* 4 */
  2051. "4K Bytes", /* 5 */
  2052. "80K Bytes", /* 6 */
  2053. "160K Bytes", /* 7 */
  2054. "8K Bytes", /* 8 */
  2055. "16K Bytes", /* 9 */
  2056. "32K Bytes", /* 10 */
  2057. "64K Bytes", /* 11 */
  2058. "128K Bytes", /* 12 */
  2059. "256K Bytes", /* 13 */
  2060. "96K Bytes", /* 14 */
  2061. "512K Bytes", /* 15 */
  2062. };
  2063. static const struct archnames { unsigned value; const char *name; } archnames[] = {
  2064. { 0x19, "AT91SAM9xx Series" },
  2065. { 0x29, "AT91SAM9XExx Series" },
  2066. { 0x34, "AT91x34 Series" },
  2067. { 0x37, "CAP7 Series" },
  2068. { 0x39, "CAP9 Series" },
  2069. { 0x3B, "CAP11 Series" },
  2070. { 0x40, "AT91x40 Series" },
  2071. { 0x42, "AT91x42 Series" },
  2072. { 0x55, "AT91x55 Series" },
  2073. { 0x60, "AT91SAM7Axx Series" },
  2074. { 0x61, "AT91SAM7AQxx Series" },
  2075. { 0x63, "AT91x63 Series" },
  2076. { 0x70, "AT91SAM7Sxx Series" },
  2077. { 0x71, "AT91SAM7XCxx Series" },
  2078. { 0x72, "AT91SAM7SExx Series" },
  2079. { 0x73, "AT91SAM7Lxx Series" },
  2080. { 0x75, "AT91SAM7Xxx Series" },
  2081. { 0x76, "AT91SAM7SLxx Series" },
  2082. { 0x80, "ATSAM3UxC Series (100-pin version)" },
  2083. { 0x81, "ATSAM3UxE Series (144-pin version)" },
  2084. { 0x83, "ATSAM3AxC Series (100-pin version)" },
  2085. { 0x84, "ATSAM3XxC Series (100-pin version)" },
  2086. { 0x85, "ATSAM3XxE Series (144-pin version)" },
  2087. { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
  2088. { 0x88, "ATSAM3SxA Series (48-pin version)" },
  2089. { 0x89, "ATSAM3SxB Series (64-pin version)" },
  2090. { 0x8A, "ATSAM3SxC Series (100-pin version)" },
  2091. { 0x92, "AT91x92 Series" },
  2092. { 0x93, "ATSAM3NxA Series (48-pin version)" },
  2093. { 0x94, "ATSAM3NxB Series (64-pin version)" },
  2094. { 0x95, "ATSAM3NxC Series (100-pin version)" },
  2095. { 0x98, "ATSAM3SDxA Series (48-pin version)" },
  2096. { 0x99, "ATSAM3SDxB Series (64-pin version)" },
  2097. { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
  2098. { 0xA5, "ATSAM5A" },
  2099. { 0xF0, "AT75Cxx Series" },
  2100. { -1, NULL },
  2101. };
  2102. static const char *const nvptype[] = {
  2103. "rom", /* 0 */
  2104. "romless or onchip flash", /* 1 */
  2105. "embedded flash memory",/* 2 */
  2106. "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
  2107. "sram emulating flash", /* 4 */
  2108. _unknown, /* 5 */
  2109. _unknown, /* 6 */
  2110. _unknown, /* 7 */
  2111. };
  2112. static const char *_yes_or_no(uint32_t v)
  2113. {
  2114. if (v)
  2115. return "YES";
  2116. else
  2117. return "NO";
  2118. }
  2119. static const char *const _rc_freq[] = {
  2120. "4 MHz", "8 MHz", "12 MHz", "reserved"
  2121. };
  2122. static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
  2123. {
  2124. uint32_t v;
  2125. uint32_t rcen;
  2126. v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
  2127. LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
  2128. v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
  2129. LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
  2130. rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
  2131. LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
  2132. v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
  2133. LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
  2134. pChip->cfg.rc_freq = 0;
  2135. if (rcen) {
  2136. switch (v) {
  2137. default:
  2138. pChip->cfg.rc_freq = 0;
  2139. break;
  2140. case 0:
  2141. pChip->cfg.rc_freq = 4 * 1000 * 1000;
  2142. break;
  2143. case 1:
  2144. pChip->cfg.rc_freq = 8 * 1000 * 1000;
  2145. break;
  2146. case 2:
  2147. pChip->cfg.rc_freq = 12 * 1000 * 1000;
  2148. break;
  2149. }
  2150. }
  2151. v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
  2152. LOG_USER("(startup clks, time= %f uSecs)",
  2153. ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
  2154. v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
  2155. LOG_USER("(mainosc source: %s)",
  2156. v ? "external xtal" : "internal RC");
  2157. v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
  2158. LOG_USER("(clock failure enabled: %s)",
  2159. _yes_or_no(v));
  2160. }
  2161. static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
  2162. {
  2163. int x;
  2164. uint32_t v;
  2165. const char *cp;
  2166. sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
  2167. LOG_USER_N("\n");
  2168. v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
  2169. LOG_USER("%s", eproc_names[v]);
  2170. v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
  2171. LOG_USER("%s", nvpsize[v]);
  2172. v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
  2173. LOG_USER("%s", nvpsize2[v]);
  2174. v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
  2175. LOG_USER("%s", sramsize[v]);
  2176. v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
  2177. cp = _unknown;
  2178. for (x = 0; archnames[x].name; x++) {
  2179. if (v == archnames[x].value) {
  2180. cp = archnames[x].name;
  2181. break;
  2182. }
  2183. }
  2184. LOG_USER("%s", cp);
  2185. v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
  2186. LOG_USER("%s", nvptype[v]);
  2187. v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
  2188. LOG_USER("(exists: %s)", _yes_or_no(v));
  2189. }
  2190. static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
  2191. {
  2192. uint32_t v;
  2193. v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
  2194. LOG_USER("(main ready: %s)", _yes_or_no(v));
  2195. v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
  2196. v = (v * pChip->cfg.slow_freq) / 16;
  2197. pChip->cfg.mainosc_freq = v;
  2198. LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
  2199. _tomhz(v),
  2200. pChip->cfg.slow_freq / 1000,
  2201. pChip->cfg.slow_freq % 1000);
  2202. }
  2203. static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
  2204. {
  2205. uint32_t mula, diva;
  2206. diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
  2207. LOG_USER_N("\n");
  2208. mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
  2209. LOG_USER_N("\n");
  2210. pChip->cfg.plla_freq = 0;
  2211. if (mula == 0)
  2212. LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
  2213. else if (diva == 0)
  2214. LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
  2215. else if (diva >= 1) {
  2216. pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
  2217. LOG_USER("\tPLLA Freq: %3.03f MHz",
  2218. _tomhz(pChip->cfg.plla_freq));
  2219. }
  2220. }
  2221. static void sam3_explain_mckr(struct sam3_chip *pChip)
  2222. {
  2223. uint32_t css, pres, fin = 0;
  2224. int pdiv = 0;
  2225. const char *cp = NULL;
  2226. css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
  2227. switch (css & 3) {
  2228. case 0:
  2229. fin = pChip->cfg.slow_freq;
  2230. cp = "slowclk";
  2231. break;
  2232. case 1:
  2233. fin = pChip->cfg.mainosc_freq;
  2234. cp = "mainosc";
  2235. break;
  2236. case 2:
  2237. fin = pChip->cfg.plla_freq;
  2238. cp = "plla";
  2239. break;
  2240. case 3:
  2241. if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
  2242. fin = 480 * 1000 * 1000;
  2243. cp = "upll";
  2244. } else {
  2245. fin = 0;
  2246. cp = "upll (*ERROR* UPLL is disabled)";
  2247. }
  2248. break;
  2249. default:
  2250. assert(0);
  2251. break;
  2252. }
  2253. LOG_USER("%s (%3.03f Mhz)",
  2254. cp,
  2255. _tomhz(fin));
  2256. pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
  2257. switch (pres & 0x07) {
  2258. case 0:
  2259. pdiv = 1;
  2260. cp = "selected clock";
  2261. break;
  2262. case 1:
  2263. pdiv = 2;
  2264. cp = "clock/2";
  2265. break;
  2266. case 2:
  2267. pdiv = 4;
  2268. cp = "clock/4";
  2269. break;
  2270. case 3:
  2271. pdiv = 8;
  2272. cp = "clock/8";
  2273. break;
  2274. case 4:
  2275. pdiv = 16;
  2276. cp = "clock/16";
  2277. break;
  2278. case 5:
  2279. pdiv = 32;
  2280. cp = "clock/32";
  2281. break;
  2282. case 6:
  2283. pdiv = 64;
  2284. cp = "clock/64";
  2285. break;
  2286. case 7:
  2287. pdiv = 6;
  2288. cp = "clock/6";
  2289. break;
  2290. default:
  2291. assert(0);
  2292. break;
  2293. }
  2294. LOG_USER("(%s)", cp);
  2295. fin = fin / pdiv;
  2296. /* sam3 has a *SINGLE* clock - */
  2297. /* other at91 series parts have divisors for these. */
  2298. pChip->cfg.cpu_freq = fin;
  2299. pChip->cfg.mclk_freq = fin;
  2300. pChip->cfg.fclk_freq = fin;
  2301. LOG_USER("\t\tResult CPU Freq: %3.03f",
  2302. _tomhz(fin));
  2303. }
  2304. #if 0
  2305. static struct sam3_chip *target2sam3(struct target *pTarget)
  2306. {
  2307. struct sam3_chip *pChip;
  2308. if (pTarget == NULL)
  2309. return NULL;
  2310. pChip = all_sam3_chips;
  2311. while (pChip) {
  2312. if (pChip->target == pTarget)
  2313. break; /* return below */
  2314. else
  2315. pChip = pChip->next;
  2316. }
  2317. return pChip;
  2318. }
  2319. #endif
  2320. static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
  2321. {
  2322. /* this function exists to help */
  2323. /* keep funky offsetof() errors */
  2324. /* and casting from causing bugs */
  2325. /* By using prototypes - we can detect what would */
  2326. /* be casting errors. */
  2327. return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
  2328. }
  2329. #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
  2330. struct sam3_cfg, \
  2331. NAME), # NAME, FUNC }
  2332. static const struct sam3_reg_list sam3_all_regs[] = {
  2333. SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
  2334. SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
  2335. SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
  2336. SAM3_ENTRY(CKGR_UCKR, NULL),
  2337. SAM3_ENTRY(PMC_FSMR, NULL),
  2338. SAM3_ENTRY(PMC_FSPR, NULL),
  2339. SAM3_ENTRY(PMC_IMR, NULL),
  2340. SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
  2341. SAM3_ENTRY(PMC_PCK0, NULL),
  2342. SAM3_ENTRY(PMC_PCK1, NULL),
  2343. SAM3_ENTRY(PMC_PCK2, NULL),
  2344. SAM3_ENTRY(PMC_PCSR, NULL),
  2345. SAM3_ENTRY(PMC_SCSR, NULL),
  2346. SAM3_ENTRY(PMC_SR, NULL),
  2347. SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
  2348. SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
  2349. SAM3_ENTRY(CHIPID_EXID, NULL),
  2350. SAM3_ENTRY(CHIPID_EXID2, NULL),
  2351. /* TERMINATE THE LIST */
  2352. { .name = NULL }
  2353. };
  2354. #undef SAM3_ENTRY
  2355. static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
  2356. {
  2357. return (struct sam3_bank_private *)(bank->driver_priv);
  2358. }
  2359. /**
  2360. * Given a pointer to where it goes in the structure,
  2361. * determine the register name, address from the all registers table.
  2362. */
  2363. static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
  2364. {
  2365. const struct sam3_reg_list *pReg;
  2366. pReg = &(sam3_all_regs[0]);
  2367. while (pReg->name) {
  2368. uint32_t *pPossible;
  2369. /* calculate where this one go.. */
  2370. /* it is "possibly" this register. */
  2371. pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
  2372. /* well? Is it this register */
  2373. if (pPossible == goes_here) {
  2374. /* Jump for joy! */
  2375. return pReg;
  2376. }
  2377. /* next... */
  2378. pReg++;
  2379. }
  2380. /* This is *TOTAL*PANIC* - we are totally screwed. */
  2381. LOG_ERROR("INVALID SAM3 REGISTER");
  2382. return NULL;
  2383. }
  2384. static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
  2385. {
  2386. const struct sam3_reg_list *pReg;
  2387. int r;
  2388. pReg = sam3_GetReg(pChip, goes_here);
  2389. if (!pReg)
  2390. return ERROR_FAIL;
  2391. r = target_read_u32(pChip->target, pReg->address, goes_here);
  2392. if (r != ERROR_OK) {
  2393. LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
  2394. pReg->name, (unsigned)(pReg->address), r);
  2395. }
  2396. return r;
  2397. }
  2398. static int sam3_ReadAllRegs(struct sam3_chip *pChip)
  2399. {
  2400. int r;
  2401. const struct sam3_reg_list *pReg;
  2402. pReg = &(sam3_all_regs[0]);
  2403. while (pReg->name) {
  2404. r = sam3_ReadThisReg(pChip,
  2405. sam3_get_reg_ptr(&(pChip->cfg), pReg));
  2406. if (r != ERROR_OK) {
  2407. LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
  2408. pReg->name, ((unsigned)(pReg->address)), r);
  2409. return r;
  2410. }
  2411. pReg++;
  2412. }
  2413. /* Chip identification register
  2414. *
  2415. * Unfortunately, the chip identification register is not at
  2416. * a constant address across all of the SAM3 series'. As a
  2417. * consequence, a simple heuristic is used to find where it's
  2418. * at...
  2419. *
  2420. * If the contents at the first address is zero, then we know
  2421. * that the second address is where the chip id register is.
  2422. * We can deduce this because for those SAM's that have the
  2423. * chip id @ 0x400e0940, the first address, 0x400e0740, is
  2424. * located in the memory map of the Power Management Controller
  2425. * (PMC). Furthermore, the address is not used by the PMC.
  2426. * So when read, the memory controller returns zero.*/
  2427. if (pChip->cfg.CHIPID_CIDR == 0) {
  2428. /*Put the correct CIDR and EXID values in the pChip structure */
  2429. pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
  2430. pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
  2431. }
  2432. return ERROR_OK;
  2433. }
  2434. static int sam3_GetInfo(struct sam3_chip *pChip)
  2435. {
  2436. const struct sam3_reg_list *pReg;
  2437. uint32_t regval;
  2438. pReg = &(sam3_all_regs[0]);
  2439. while (pReg->name) {
  2440. /* display all regs */
  2441. LOG_DEBUG("Start: %s", pReg->name);
  2442. regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
  2443. LOG_USER("%*s: [0x%08x] -> 0x%08x",
  2444. REG_NAME_WIDTH,
  2445. pReg->name,
  2446. pReg->address,
  2447. regval);
  2448. if (pReg->explain_func)
  2449. (*(pReg->explain_func))(pChip);
  2450. LOG_DEBUG("End: %s", pReg->name);
  2451. pReg++;
  2452. }
  2453. LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
  2454. LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
  2455. LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
  2456. LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
  2457. LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
  2458. LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
  2459. pChip->cfg.unique_id[0],
  2460. pChip->cfg.unique_id[1],
  2461. pChip->cfg.unique_id[2],
  2462. pChip->cfg.unique_id[3]);
  2463. return ERROR_OK;
  2464. }
  2465. static int sam3_erase_check(struct flash_bank *bank)
  2466. {
  2467. int x;
  2468. LOG_DEBUG("Here");
  2469. if (bank->target->state != TARGET_HALTED) {
  2470. LOG_ERROR("Target not halted");
  2471. return ERROR_TARGET_NOT_HALTED;
  2472. }
  2473. if (0 == bank->num_sectors) {
  2474. LOG_ERROR("Target: not supported/not probed");
  2475. return ERROR_FAIL;
  2476. }
  2477. LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
  2478. for (x = 0; x < bank->num_sectors; x++)
  2479. bank->sectors[x].is_erased = 1;
  2480. LOG_DEBUG("Done");
  2481. return ERROR_OK;
  2482. }
  2483. static int sam3_protect_check(struct flash_bank *bank)
  2484. {
  2485. int r;
  2486. uint32_t v = 0;
  2487. unsigned x;
  2488. struct sam3_bank_private *pPrivate;
  2489. LOG_DEBUG("Begin");
  2490. if (bank->target->state != TARGET_HALTED) {
  2491. LOG_ERROR("Target not halted");
  2492. return ERROR_TARGET_NOT_HALTED;
  2493. }
  2494. pPrivate = get_sam3_bank_private(bank);
  2495. if (!pPrivate) {
  2496. LOG_ERROR("no private for this bank?");
  2497. return ERROR_FAIL;
  2498. }
  2499. if (!(pPrivate->probed))
  2500. return ERROR_FLASH_BANK_NOT_PROBED;
  2501. r = FLASHD_GetLockBits(pPrivate, &v);
  2502. if (r != ERROR_OK) {
  2503. LOG_DEBUG("Failed: %d", r);
  2504. return r;
  2505. }
  2506. for (x = 0; x < pPrivate->nsectors; x++)
  2507. bank->sectors[x].is_protected = (!!(v & (1 << x)));
  2508. LOG_DEBUG("Done");
  2509. return ERROR_OK;
  2510. }
  2511. FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
  2512. {
  2513. struct sam3_chip *pChip;
  2514. pChip = all_sam3_chips;
  2515. /* is this an existing chip? */
  2516. while (pChip) {
  2517. if (pChip->target == bank->target)
  2518. break;
  2519. pChip = pChip->next;
  2520. }
  2521. if (!pChip) {
  2522. /* this is a *NEW* chip */
  2523. pChip = calloc(1, sizeof(struct sam3_chip));
  2524. if (!pChip) {
  2525. LOG_ERROR("NO RAM!");
  2526. return ERROR_FAIL;
  2527. }
  2528. pChip->target = bank->target;
  2529. /* insert at head */
  2530. pChip->next = all_sam3_chips;
  2531. all_sam3_chips = pChip;
  2532. pChip->target = bank->target;
  2533. /* assumption is this runs at 32khz */
  2534. pChip->cfg.slow_freq = 32768;
  2535. pChip->probed = 0;
  2536. }
  2537. switch (bank->base) {
  2538. default:
  2539. LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
  2540. "[at91sam3u series] or 0x%08x [at91sam3s series] or "
  2541. "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
  2542. ((unsigned int)(bank->base)),
  2543. ((unsigned int)(FLASH_BANK0_BASE_U)),
  2544. ((unsigned int)(FLASH_BANK1_BASE_U)),
  2545. ((unsigned int)(FLASH_BANK_BASE_S)),
  2546. ((unsigned int)(FLASH_BANK_BASE_N)),
  2547. ((unsigned int)(FLASH_BANK0_BASE_AX)),
  2548. ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
  2549. ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
  2550. return ERROR_FAIL;
  2551. break;
  2552. /* at91sam3s and at91sam3n series only has bank 0*/
  2553. /* at91sam3u and at91sam3ax series has the same address for bank 0*/
  2554. case FLASH_BANK_BASE_S:
  2555. case FLASH_BANK0_BASE_U:
  2556. bank->driver_priv = &(pChip->details.bank[0]);
  2557. bank->bank_number = 0;
  2558. pChip->details.bank[0].pChip = pChip;
  2559. pChip->details.bank[0].pBank = bank;
  2560. break;
  2561. /* Bank 1 of at91sam3u or at91sam3ax series */
  2562. case FLASH_BANK1_BASE_U:
  2563. case FLASH_BANK1_BASE_256K_AX:
  2564. case FLASH_BANK1_BASE_512K_AX:
  2565. bank->driver_priv = &(pChip->details.bank[1]);
  2566. bank->bank_number = 1;
  2567. pChip->details.bank[1].pChip = pChip;
  2568. pChip->details.bank[1].pBank = bank;
  2569. break;
  2570. }
  2571. /* we initialize after probing. */
  2572. return ERROR_OK;
  2573. }
  2574. static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
  2575. {
  2576. const struct sam3_chip_details *pDetails;
  2577. struct sam3_chip *pChip;
  2578. struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
  2579. unsigned x;
  2580. LOG_DEBUG("Begin");
  2581. pDetails = all_sam3_details;
  2582. while (pDetails->name) {
  2583. /* Compare cidr without version bits */
  2584. if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
  2585. break;
  2586. else
  2587. pDetails++;
  2588. }
  2589. if (pDetails->name == NULL) {
  2590. LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
  2591. (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
  2592. /* Help the victim, print details about the chip */
  2593. LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
  2594. pPrivate->pChip->cfg.CHIPID_CIDR);
  2595. sam3_explain_chipid_cidr(pPrivate->pChip);
  2596. return ERROR_FAIL;
  2597. }
  2598. /* DANGER: THERE ARE DRAGONS HERE */
  2599. /* get our pChip - it is going */
  2600. /* to be over-written shortly */
  2601. pChip = pPrivate->pChip;
  2602. /* Note that, in reality: */
  2603. /* */
  2604. /* pPrivate = &(pChip->details.bank[0]) */
  2605. /* or pPrivate = &(pChip->details.bank[1]) */
  2606. /* */
  2607. /* save the "bank" pointers */
  2608. for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
  2609. saved_banks[x] = pChip->details.bank[x].pBank;
  2610. /* Overwrite the "details" structure. */
  2611. memcpy(&(pPrivate->pChip->details),
  2612. pDetails,
  2613. sizeof(pPrivate->pChip->details));
  2614. /* now fix the ghosted pointers */
  2615. for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
  2616. pChip->details.bank[x].pChip = pChip;
  2617. pChip->details.bank[x].pBank = saved_banks[x];
  2618. }
  2619. /* update the *BANK*SIZE* */
  2620. LOG_DEBUG("End");
  2621. return ERROR_OK;
  2622. }
  2623. static int _sam3_probe(struct flash_bank *bank, int noise)
  2624. {
  2625. unsigned x;
  2626. int r;
  2627. struct sam3_bank_private *pPrivate;
  2628. LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
  2629. if (bank->target->state != TARGET_HALTED) {
  2630. LOG_ERROR("Target not halted");
  2631. return ERROR_TARGET_NOT_HALTED;
  2632. }
  2633. pPrivate = get_sam3_bank_private(bank);
  2634. if (!pPrivate) {
  2635. LOG_ERROR("Invalid/unknown bank number");
  2636. return ERROR_FAIL;
  2637. }
  2638. r = sam3_ReadAllRegs(pPrivate->pChip);
  2639. if (r != ERROR_OK)
  2640. return r;
  2641. LOG_DEBUG("Here");
  2642. if (pPrivate->pChip->probed)
  2643. r = sam3_GetInfo(pPrivate->pChip);
  2644. else
  2645. r = sam3_GetDetails(pPrivate);
  2646. if (r != ERROR_OK)
  2647. return r;
  2648. /* update the flash bank size */
  2649. for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
  2650. if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
  2651. bank->size = pPrivate->pChip->details.bank[x].size_bytes;
  2652. break;
  2653. }
  2654. }
  2655. if (bank->sectors == NULL) {
  2656. bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
  2657. if (bank->sectors == NULL) {
  2658. LOG_ERROR("No memory!");
  2659. return ERROR_FAIL;
  2660. }
  2661. bank->num_sectors = pPrivate->nsectors;
  2662. for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
  2663. bank->sectors[x].size = pPrivate->sector_size;
  2664. bank->sectors[x].offset = x * (pPrivate->sector_size);
  2665. /* mark as unknown */
  2666. bank->sectors[x].is_erased = -1;
  2667. bank->sectors[x].is_protected = -1;
  2668. }
  2669. }
  2670. pPrivate->probed = 1;
  2671. r = sam3_protect_check(bank);
  2672. if (r != ERROR_OK)
  2673. return r;
  2674. LOG_DEBUG("Bank = %d, nbanks = %d",
  2675. pPrivate->bank_number, pPrivate->pChip->details.n_banks);
  2676. if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
  2677. /* read unique id, */
  2678. /* it appears to be associated with the *last* flash bank. */
  2679. FLASHD_ReadUniqueID(pPrivate);
  2680. }
  2681. return r;
  2682. }
  2683. static int sam3_probe(struct flash_bank *bank)
  2684. {
  2685. return _sam3_probe(bank, 1);
  2686. }
  2687. static int sam3_auto_probe(struct flash_bank *bank)
  2688. {
  2689. return _sam3_probe(bank, 0);
  2690. }
  2691. static int sam3_erase(struct flash_bank *bank, int first, int last)
  2692. {
  2693. struct sam3_bank_private *pPrivate;
  2694. int r;
  2695. LOG_DEBUG("Here");
  2696. if (bank->target->state != TARGET_HALTED) {
  2697. LOG_ERROR("Target not halted");
  2698. return ERROR_TARGET_NOT_HALTED;
  2699. }
  2700. r = sam3_auto_probe(bank);
  2701. if (r != ERROR_OK) {
  2702. LOG_DEBUG("Here,r=%d", r);
  2703. return r;
  2704. }
  2705. pPrivate = get_sam3_bank_private(bank);
  2706. if (!(pPrivate->probed))
  2707. return ERROR_FLASH_BANK_NOT_PROBED;
  2708. if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
  2709. /* whole chip */
  2710. LOG_DEBUG("Here");
  2711. return FLASHD_EraseEntireBank(pPrivate);
  2712. }
  2713. LOG_INFO("sam3 auto-erases while programming (request ignored)");
  2714. return ERROR_OK;
  2715. }
  2716. static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
  2717. {
  2718. struct sam3_bank_private *pPrivate;
  2719. int r;
  2720. LOG_DEBUG("Here");
  2721. if (bank->target->state != TARGET_HALTED) {
  2722. LOG_ERROR("Target not halted");
  2723. return ERROR_TARGET_NOT_HALTED;
  2724. }
  2725. pPrivate = get_sam3_bank_private(bank);
  2726. if (!(pPrivate->probed))
  2727. return ERROR_FLASH_BANK_NOT_PROBED;
  2728. if (set)
  2729. r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
  2730. else
  2731. r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
  2732. LOG_DEBUG("End: r=%d", r);
  2733. return r;
  2734. }
  2735. static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
  2736. {
  2737. if (bank->target->state != TARGET_HALTED) {
  2738. LOG_ERROR("Target not halted");
  2739. return ERROR_TARGET_NOT_HALTED;
  2740. }
  2741. buf[0] = 0;
  2742. return ERROR_OK;
  2743. }
  2744. static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  2745. {
  2746. uint32_t adr;
  2747. int r;
  2748. adr = pagenum * pPrivate->page_size;
  2749. adr += pPrivate->base_address;
  2750. r = target_read_memory(pPrivate->pChip->target,
  2751. adr,
  2752. 4, /* THIS*MUST*BE* in 32bit values */
  2753. pPrivate->page_size / 4,
  2754. buf);
  2755. if (r != ERROR_OK)
  2756. LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
  2757. (unsigned int)(adr));
  2758. return r;
  2759. }
  2760. /* The code below is basically this: */
  2761. /* compiled with */
  2762. /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
  2763. /* */
  2764. /* Only the *CPU* can write to the flash buffer. */
  2765. /* the DAP cannot... so - we download this 28byte thing */
  2766. /* Run the algorithm - (below) */
  2767. /* to program the device */
  2768. /* */
  2769. /* ======================================== */
  2770. /* #include <stdint.h> */
  2771. /* */
  2772. /* struct foo { */
  2773. /* uint32_t *dst; */
  2774. /* const uint32_t *src; */
  2775. /* int n; */
  2776. /* volatile uint32_t *base; */
  2777. /* uint32_t cmd; */
  2778. /* }; */
  2779. /* */
  2780. /* */
  2781. /* uint32_t sam3_function(struct foo *p) */
  2782. /* { */
  2783. /* volatile uint32_t *v; */
  2784. /* uint32_t *d; */
  2785. /* const uint32_t *s; */
  2786. /* int n; */
  2787. /* uint32_t r; */
  2788. /* */
  2789. /* d = p->dst; */
  2790. /* s = p->src; */
  2791. /* n = p->n; */
  2792. /* */
  2793. /* do { */
  2794. /* *d++ = *s++; */
  2795. /* } while (--n) */
  2796. /* ; */
  2797. /* */
  2798. /* v = p->base; */
  2799. /* */
  2800. /* v[ 1 ] = p->cmd; */
  2801. /* do { */
  2802. /* r = v[8/4]; */
  2803. /* } while (!(r&1)) */
  2804. /* ; */
  2805. /* return r; */
  2806. /* } */
  2807. /* ======================================== */
  2808. static const uint8_t
  2809. sam3_page_write_opcodes[] = {
  2810. /* 24 0000 0446 mov r4, r0 */
  2811. 0x04, 0x46,
  2812. /* 25 0002 6168 ldr r1, [r4, #4] */
  2813. 0x61, 0x68,
  2814. /* 26 0004 0068 ldr r0, [r0, #0] */
  2815. 0x00, 0x68,
  2816. /* 27 0006 A268 ldr r2, [r4, #8] */
  2817. 0xa2, 0x68,
  2818. /* 28 @ lr needed for prologue */
  2819. /* 29 .L2: */
  2820. /* 30 0008 51F8043B ldr r3, [r1], #4 */
  2821. 0x51, 0xf8, 0x04, 0x3b,
  2822. /* 31 000c 12F1FF32 adds r2, r2, #-1 */
  2823. 0x12, 0xf1, 0xff, 0x32,
  2824. /* 32 0010 40F8043B str r3, [r0], #4 */
  2825. 0x40, 0xf8, 0x04, 0x3b,
  2826. /* 33 0014 F8D1 bne .L2 */
  2827. 0xf8, 0xd1,
  2828. /* 34 0016 E268 ldr r2, [r4, #12] */
  2829. 0xe2, 0x68,
  2830. /* 35 0018 2369 ldr r3, [r4, #16] */
  2831. 0x23, 0x69,
  2832. /* 36 001a 5360 str r3, [r2, #4] */
  2833. 0x53, 0x60,
  2834. /* 37 001c 0832 adds r2, r2, #8 */
  2835. 0x08, 0x32,
  2836. /* 38 .L4: */
  2837. /* 39 001e 1068 ldr r0, [r2, #0] */
  2838. 0x10, 0x68,
  2839. /* 40 0020 10F0010F tst r0, #1 */
  2840. 0x10, 0xf0, 0x01, 0x0f,
  2841. /* 41 0024 FBD0 beq .L4 */
  2842. 0xfb, 0xd0,
  2843. 0x00, 0xBE /* bkpt #0 */
  2844. };
  2845. static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  2846. {
  2847. uint32_t adr;
  2848. uint32_t status;
  2849. uint32_t fmr; /* EEFC Flash Mode Register */
  2850. int r;
  2851. adr = pagenum * pPrivate->page_size;
  2852. adr += pPrivate->base_address;
  2853. /* Get flash mode register value */
  2854. r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
  2855. if (r != ERROR_OK)
  2856. LOG_DEBUG("Error Read failed: read flash mode register");
  2857. /* Clear flash wait state field */
  2858. fmr &= 0xfffff0ff;
  2859. /* set FWS (flash wait states) field in the FMR (flash mode register) */
  2860. fmr |= (pPrivate->flash_wait_states << 8);
  2861. LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
  2862. r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
  2863. if (r != ERROR_OK)
  2864. LOG_DEBUG("Error Write failed: set flash mode register");
  2865. LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
  2866. r = target_write_memory(pPrivate->pChip->target,
  2867. adr,
  2868. 4, /* THIS*MUST*BE* in 32bit values */
  2869. pPrivate->page_size / 4,
  2870. buf);
  2871. if (r != ERROR_OK) {
  2872. LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
  2873. (unsigned int)(adr));
  2874. return r;
  2875. }
  2876. r = EFC_PerformCommand(pPrivate,
  2877. /* send Erase & Write Page */
  2878. AT91C_EFC_FCMD_EWP,
  2879. pagenum,
  2880. &status);
  2881. if (r != ERROR_OK)
  2882. LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
  2883. (unsigned int)(adr));
  2884. if (status & (1 << 2)) {
  2885. LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
  2886. return ERROR_FAIL;
  2887. }
  2888. if (status & (1 << 1)) {
  2889. LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
  2890. return ERROR_FAIL;
  2891. }
  2892. return ERROR_OK;
  2893. }
  2894. static int sam3_write(struct flash_bank *bank,
  2895. uint8_t *buffer,
  2896. uint32_t offset,
  2897. uint32_t count)
  2898. {
  2899. int n;
  2900. unsigned page_cur;
  2901. unsigned page_end;
  2902. int r;
  2903. unsigned page_offset;
  2904. struct sam3_bank_private *pPrivate;
  2905. uint8_t *pagebuffer;
  2906. /* incase we bail further below, set this to null */
  2907. pagebuffer = NULL;
  2908. /* ignore dumb requests */
  2909. if (count == 0) {
  2910. r = ERROR_OK;
  2911. goto done;
  2912. }
  2913. if (bank->target->state != TARGET_HALTED) {
  2914. LOG_ERROR("Target not halted");
  2915. r = ERROR_TARGET_NOT_HALTED;
  2916. goto done;
  2917. }
  2918. pPrivate = get_sam3_bank_private(bank);
  2919. if (!(pPrivate->probed)) {
  2920. r = ERROR_FLASH_BANK_NOT_PROBED;
  2921. goto done;
  2922. }
  2923. if ((offset + count) > pPrivate->size_bytes) {
  2924. LOG_ERROR("Flash write error - past end of bank");
  2925. LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
  2926. (unsigned int)(offset),
  2927. (unsigned int)(count),
  2928. (unsigned int)(pPrivate->size_bytes));
  2929. r = ERROR_FAIL;
  2930. goto done;
  2931. }
  2932. pagebuffer = malloc(pPrivate->page_size);
  2933. if (!pagebuffer) {
  2934. LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
  2935. r = ERROR_FAIL;
  2936. goto done;
  2937. }
  2938. /* what page do we start & end in? */
  2939. page_cur = offset / pPrivate->page_size;
  2940. page_end = (offset + count - 1) / pPrivate->page_size;
  2941. LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
  2942. LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
  2943. /* Special case: all one page */
  2944. /* */
  2945. /* Otherwise: */
  2946. /* (1) non-aligned start */
  2947. /* (2) body pages */
  2948. /* (3) non-aligned end. */
  2949. /* Handle special case - all one page. */
  2950. if (page_cur == page_end) {
  2951. LOG_DEBUG("Special case, all in one page");
  2952. r = sam3_page_read(pPrivate, page_cur, pagebuffer);
  2953. if (r != ERROR_OK)
  2954. goto done;
  2955. page_offset = (offset & (pPrivate->page_size-1));
  2956. memcpy(pagebuffer + page_offset,
  2957. buffer,
  2958. count);
  2959. r = sam3_page_write(pPrivate, page_cur, pagebuffer);
  2960. if (r != ERROR_OK)
  2961. goto done;
  2962. r = ERROR_OK;
  2963. goto done;
  2964. }
  2965. /* non-aligned start */
  2966. page_offset = offset & (pPrivate->page_size - 1);
  2967. if (page_offset) {
  2968. LOG_DEBUG("Not-Aligned start");
  2969. /* read the partial */
  2970. r = sam3_page_read(pPrivate, page_cur, pagebuffer);
  2971. if (r != ERROR_OK)
  2972. goto done;
  2973. /* over-write with new data */
  2974. n = (pPrivate->page_size - page_offset);
  2975. memcpy(pagebuffer + page_offset,
  2976. buffer,
  2977. n);
  2978. r = sam3_page_write(pPrivate, page_cur, pagebuffer);
  2979. if (r != ERROR_OK)
  2980. goto done;
  2981. count -= n;
  2982. offset += n;
  2983. buffer += n;
  2984. page_cur++;
  2985. }
  2986. /* By checking that offset is correct here, we also
  2987. fix a clang warning */
  2988. assert(offset % pPrivate->page_size == 0);
  2989. /* intermediate large pages */
  2990. /* also - the final *terminal* */
  2991. /* if that terminal page is a full page */
  2992. LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
  2993. (int)page_cur, (int)page_end, (unsigned int)(count));
  2994. while ((page_cur < page_end) &&
  2995. (count >= pPrivate->page_size)) {
  2996. r = sam3_page_write(pPrivate, page_cur, buffer);
  2997. if (r != ERROR_OK)
  2998. goto done;
  2999. count -= pPrivate->page_size;
  3000. buffer += pPrivate->page_size;
  3001. page_cur += 1;
  3002. }
  3003. /* terminal partial page? */
  3004. if (count) {
  3005. LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
  3006. /* we have a partial page */
  3007. r = sam3_page_read(pPrivate, page_cur, pagebuffer);
  3008. if (r != ERROR_OK)
  3009. goto done;
  3010. /* data goes at start */
  3011. memcpy(pagebuffer, buffer, count);
  3012. r = sam3_page_write(pPrivate, page_cur, pagebuffer);
  3013. if (r != ERROR_OK)
  3014. goto done;
  3015. }
  3016. LOG_DEBUG("Done!");
  3017. r = ERROR_OK;
  3018. done:
  3019. if (pagebuffer)
  3020. free(pagebuffer);
  3021. return r;
  3022. }
  3023. COMMAND_HANDLER(sam3_handle_info_command)
  3024. {
  3025. struct sam3_chip *pChip;
  3026. pChip = get_current_sam3(CMD_CTX);
  3027. if (!pChip)
  3028. return ERROR_OK;
  3029. unsigned x;
  3030. int r;
  3031. /* bank0 must exist before we can do anything */
  3032. if (pChip->details.bank[0].pBank == NULL) {
  3033. x = 0;
  3034. need_define:
  3035. command_print(CMD_CTX,
  3036. "Please define bank %d via command: flash bank %s ... ",
  3037. x,
  3038. at91sam3_flash.name);
  3039. return ERROR_FAIL;
  3040. }
  3041. /* if bank 0 is not probed, then probe it */
  3042. if (!(pChip->details.bank[0].probed)) {
  3043. r = sam3_auto_probe(pChip->details.bank[0].pBank);
  3044. if (r != ERROR_OK)
  3045. return ERROR_FAIL;
  3046. }
  3047. /* above guarantees the "chip details" structure is valid */
  3048. /* and thus, bank private areas are valid */
  3049. /* and we have a SAM3 chip, what a concept! */
  3050. /* auto-probe other banks, 0 done above */
  3051. for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
  3052. /* skip banks not present */
  3053. if (!(pChip->details.bank[x].present))
  3054. continue;
  3055. if (pChip->details.bank[x].pBank == NULL)
  3056. goto need_define;
  3057. if (pChip->details.bank[x].probed)
  3058. continue;
  3059. r = sam3_auto_probe(pChip->details.bank[x].pBank);
  3060. if (r != ERROR_OK)
  3061. return r;
  3062. }
  3063. r = sam3_GetInfo(pChip);
  3064. if (r != ERROR_OK) {
  3065. LOG_DEBUG("Sam3Info, Failed %d", r);
  3066. return r;
  3067. }
  3068. return ERROR_OK;
  3069. }
  3070. COMMAND_HANDLER(sam3_handle_gpnvm_command)
  3071. {
  3072. unsigned x, v;
  3073. int r, who;
  3074. struct sam3_chip *pChip;
  3075. pChip = get_current_sam3(CMD_CTX);
  3076. if (!pChip)
  3077. return ERROR_OK;
  3078. if (pChip->target->state != TARGET_HALTED) {
  3079. LOG_ERROR("sam3 - target not halted");
  3080. return ERROR_TARGET_NOT_HALTED;
  3081. }
  3082. if (pChip->details.bank[0].pBank == NULL) {
  3083. command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
  3084. at91sam3_flash.name);
  3085. return ERROR_FAIL;
  3086. }
  3087. if (!pChip->details.bank[0].probed) {
  3088. r = sam3_auto_probe(pChip->details.bank[0].pBank);
  3089. if (r != ERROR_OK)
  3090. return r;
  3091. }
  3092. switch (CMD_ARGC) {
  3093. default:
  3094. return ERROR_COMMAND_SYNTAX_ERROR;
  3095. break;
  3096. case 0:
  3097. goto showall;
  3098. break;
  3099. case 1:
  3100. who = -1;
  3101. break;
  3102. case 2:
  3103. if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
  3104. who = -1;
  3105. else {
  3106. uint32_t v32;
  3107. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
  3108. who = v32;
  3109. }
  3110. break;
  3111. }
  3112. if (0 == strcmp("show", CMD_ARGV[0])) {
  3113. if (who == -1) {
  3114. showall:
  3115. r = ERROR_OK;
  3116. for (x = 0; x < pChip->details.n_gpnvms; x++) {
  3117. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
  3118. if (r != ERROR_OK)
  3119. break;
  3120. command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
  3121. }
  3122. return r;
  3123. }
  3124. if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
  3125. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
  3126. command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
  3127. return r;
  3128. } else {
  3129. command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
  3130. return ERROR_COMMAND_SYNTAX_ERROR;
  3131. }
  3132. }
  3133. if (who == -1) {
  3134. command_print(CMD_CTX, "Missing GPNVM number");
  3135. return ERROR_COMMAND_SYNTAX_ERROR;
  3136. }
  3137. if (0 == strcmp("set", CMD_ARGV[0]))
  3138. r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
  3139. else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
  3140. (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
  3141. r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
  3142. else {
  3143. command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
  3144. r = ERROR_COMMAND_SYNTAX_ERROR;
  3145. }
  3146. return r;
  3147. }
  3148. COMMAND_HANDLER(sam3_handle_slowclk_command)
  3149. {
  3150. struct sam3_chip *pChip;
  3151. pChip = get_current_sam3(CMD_CTX);
  3152. if (!pChip)
  3153. return ERROR_OK;
  3154. switch (CMD_ARGC) {
  3155. case 0:
  3156. /* show */
  3157. break;
  3158. case 1:
  3159. {
  3160. /* set */
  3161. uint32_t v;
  3162. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
  3163. if (v > 200000) {
  3164. /* absurd slow clock of 200Khz? */
  3165. command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
  3166. return ERROR_COMMAND_SYNTAX_ERROR;
  3167. }
  3168. pChip->cfg.slow_freq = v;
  3169. break;
  3170. }
  3171. default:
  3172. /* error */
  3173. command_print(CMD_CTX, "Too many parameters");
  3174. return ERROR_COMMAND_SYNTAX_ERROR;
  3175. break;
  3176. }
  3177. command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
  3178. (int)(pChip->cfg.slow_freq / 1000),
  3179. (int)(pChip->cfg.slow_freq % 1000));
  3180. return ERROR_OK;
  3181. }
  3182. static const struct command_registration at91sam3_exec_command_handlers[] = {
  3183. {
  3184. .name = "gpnvm",
  3185. .handler = sam3_handle_gpnvm_command,
  3186. .mode = COMMAND_EXEC,
  3187. .usage = "[('clr'|'set'|'show') bitnum]",
  3188. .help = "Without arguments, shows all bits in the gpnvm "
  3189. "register. Otherwise, clears, sets, or shows one "
  3190. "General Purpose Non-Volatile Memory (gpnvm) bit.",
  3191. },
  3192. {
  3193. .name = "info",
  3194. .handler = sam3_handle_info_command,
  3195. .mode = COMMAND_EXEC,
  3196. .help = "Print information about the current at91sam3 chip"
  3197. "and its flash configuration.",
  3198. },
  3199. {
  3200. .name = "slowclk",
  3201. .handler = sam3_handle_slowclk_command,
  3202. .mode = COMMAND_EXEC,
  3203. .usage = "[clock_hz]",
  3204. .help = "Display or set the slowclock frequency "
  3205. "(default 32768 Hz).",
  3206. },
  3207. COMMAND_REGISTRATION_DONE
  3208. };
  3209. static const struct command_registration at91sam3_command_handlers[] = {
  3210. {
  3211. .name = "at91sam3",
  3212. .mode = COMMAND_ANY,
  3213. .help = "at91sam3 flash command group",
  3214. .usage = "",
  3215. .chain = at91sam3_exec_command_handlers,
  3216. },
  3217. COMMAND_REGISTRATION_DONE
  3218. };
  3219. struct flash_driver at91sam3_flash = {
  3220. .name = "at91sam3",
  3221. .commands = at91sam3_command_handlers,
  3222. .flash_bank_command = sam3_flash_bank_command,
  3223. .erase = sam3_erase,
  3224. .protect = sam3_protect,
  3225. .write = sam3_write,
  3226. .read = default_flash_read,
  3227. .probe = sam3_probe,
  3228. .auto_probe = sam3_auto_probe,
  3229. .erase_check = sam3_erase_check,
  3230. .protect_check = sam3_protect_check,
  3231. .info = sam3_info,
  3232. };