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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Duane Ellis *
  3. * openocd@duaneellis.com *
  4. * *
  5. * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
  6. * olaf@uni-paderborn.de *
  7. * *
  8. * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
  9. * (at91sam3x* & at91sam4 support)* *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
  19. * GNU General public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ****************************************************************************/
  26. /* Some of the the lower level code was based on code supplied by
  27. * ATMEL under this copyright. */
  28. /* BEGIN ATMEL COPYRIGHT */
  29. /* ----------------------------------------------------------------------------
  30. * ATMEL Microcontroller Software Support
  31. * ----------------------------------------------------------------------------
  32. * Copyright (c) 2009, Atmel Corporation
  33. *
  34. * All rights reserved.
  35. *
  36. * Redistribution and use in source and binary forms, with or without
  37. * modification, are permitted provided that the following conditions are met:
  38. *
  39. * - Redistributions of source code must retain the above copyright notice,
  40. * this list of conditions and the disclaimer below.
  41. *
  42. * Atmel's name may not be used to endorse or promote products derived from
  43. * this software without specific prior written permission.
  44. *
  45. * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  46. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  47. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  48. * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  49. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  51. * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  52. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  53. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  54. * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55. * ----------------------------------------------------------------------------
  56. */
  57. /* END ATMEL COPYRIGHT */
  58. #ifdef HAVE_CONFIG_H
  59. #include "config.h"
  60. #endif
  61. #include "imp.h"
  62. #include <helper/time_support.h>
  63. #define REG_NAME_WIDTH (12)
  64. /* at91sam4s series (has always one flash bank)*/
  65. #define FLASH_BANK_BASE_S 0x00400000
  66. /* at91sam4sd series (two one flash banks), first bank address */
  67. #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
  68. /* at91sam4sd16x, second bank address */
  69. #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
  70. /* at91sam4sd32x, second bank address */
  71. #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
  72. #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
  73. #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
  74. #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
  75. #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
  76. #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
  77. #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
  78. /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
  79. /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
  80. #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
  81. #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
  82. #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
  83. #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
  84. #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
  85. #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
  86. #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
  87. #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
  88. #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
  89. #define offset_EFC_FMR 0
  90. #define offset_EFC_FCR 4
  91. #define offset_EFC_FSR 8
  92. #define offset_EFC_FRR 12
  93. extern struct flash_driver at91sam4_flash;
  94. static float _tomhz(uint32_t freq_hz)
  95. {
  96. float f;
  97. f = ((float)(freq_hz)) / 1000000.0;
  98. return f;
  99. }
  100. /* How the chip is configured. */
  101. struct sam4_cfg {
  102. uint32_t unique_id[4];
  103. uint32_t slow_freq;
  104. uint32_t rc_freq;
  105. uint32_t mainosc_freq;
  106. uint32_t plla_freq;
  107. uint32_t mclk_freq;
  108. uint32_t cpu_freq;
  109. uint32_t fclk_freq;
  110. uint32_t pclk0_freq;
  111. uint32_t pclk1_freq;
  112. uint32_t pclk2_freq;
  113. #define SAM4_CHIPID_CIDR (0x400E0740)
  114. uint32_t CHIPID_CIDR;
  115. #define SAM4_CHIPID_EXID (0x400E0744)
  116. uint32_t CHIPID_EXID;
  117. #define SAM4_PMC_BASE (0x400E0400)
  118. #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
  119. uint32_t PMC_SCSR;
  120. #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
  121. uint32_t PMC_PCSR;
  122. #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
  123. uint32_t CKGR_UCKR;
  124. #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
  125. uint32_t CKGR_MOR;
  126. #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
  127. uint32_t CKGR_MCFR;
  128. #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
  129. uint32_t CKGR_PLLAR;
  130. #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
  131. uint32_t PMC_MCKR;
  132. #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
  133. uint32_t PMC_PCK0;
  134. #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
  135. uint32_t PMC_PCK1;
  136. #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
  137. uint32_t PMC_PCK2;
  138. #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
  139. uint32_t PMC_SR;
  140. #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
  141. uint32_t PMC_IMR;
  142. #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
  143. uint32_t PMC_FSMR;
  144. #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
  145. uint32_t PMC_FSPR;
  146. };
  147. struct sam4_bank_private {
  148. int probed;
  149. /* DANGER: THERE ARE DRAGONS HERE.. */
  150. /* NOTE: If you add more 'ghost' pointers */
  151. /* be aware that you must *manually* update */
  152. /* these pointers in the function sam4_GetDetails() */
  153. /* See the comment "Here there be dragons" */
  154. /* so we can find the chip we belong to */
  155. struct sam4_chip *pChip;
  156. /* so we can find the original bank pointer */
  157. struct flash_bank *pBank;
  158. unsigned bank_number;
  159. uint32_t controller_address;
  160. uint32_t base_address;
  161. uint32_t flash_wait_states;
  162. bool present;
  163. unsigned size_bytes;
  164. unsigned nsectors;
  165. unsigned sector_size;
  166. unsigned page_size;
  167. };
  168. struct sam4_chip_details {
  169. /* THERE ARE DRAGONS HERE.. */
  170. /* note: If you add pointers here */
  171. /* be careful about them as they */
  172. /* may need to be updated inside */
  173. /* the function: "sam4_GetDetails() */
  174. /* which copy/overwrites the */
  175. /* 'runtime' copy of this structure */
  176. uint32_t chipid_cidr;
  177. const char *name;
  178. unsigned n_gpnvms;
  179. #define SAM4_N_NVM_BITS 3
  180. unsigned gpnvm[SAM4_N_NVM_BITS];
  181. unsigned total_flash_size;
  182. unsigned total_sram_size;
  183. unsigned n_banks;
  184. #define SAM4_MAX_FLASH_BANKS 2
  185. /* these are "initialized" from the global const data */
  186. struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
  187. };
  188. struct sam4_chip {
  189. struct sam4_chip *next;
  190. int probed;
  191. /* this is "initialized" from the global const structure */
  192. struct sam4_chip_details details;
  193. struct target *target;
  194. struct sam4_cfg cfg;
  195. };
  196. struct sam4_reg_list {
  197. uint32_t address; size_t struct_offset; const char *name;
  198. void (*explain_func)(struct sam4_chip *pInfo);
  199. };
  200. static struct sam4_chip *all_sam4_chips;
  201. static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
  202. {
  203. struct target *t;
  204. static struct sam4_chip *p;
  205. t = get_current_target(cmd_ctx);
  206. if (!t) {
  207. command_print(cmd_ctx, "No current target?");
  208. return NULL;
  209. }
  210. p = all_sam4_chips;
  211. if (!p) {
  212. /* this should not happen */
  213. /* the command is not registered until the chip is created? */
  214. command_print(cmd_ctx, "No SAM4 chips exist?");
  215. return NULL;
  216. }
  217. while (p) {
  218. if (p->target == t)
  219. return p;
  220. p = p->next;
  221. }
  222. command_print(cmd_ctx, "Cannot find SAM4 chip?");
  223. return NULL;
  224. }
  225. /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
  226. /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
  227. /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
  228. /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
  229. /* these are used to *initialize* the "pChip->details" structure. */
  230. static const struct sam4_chip_details all_sam4_details[] = {
  231. /* Start at91sam4s* series */
  232. /*atsam4s16c - LQFP100/BGA100*/
  233. {
  234. .chipid_cidr = 0x28AC0CE0,
  235. .name = "at91sam4s16c",
  236. .total_flash_size = 1024 * 1024,
  237. .total_sram_size = 128 * 1024,
  238. .n_gpnvms = 2,
  239. .n_banks = 1,
  240. {
  241. /* .bank[0] = {*/
  242. {
  243. .probed = 0,
  244. .pChip = NULL,
  245. .pBank = NULL,
  246. .bank_number = 0,
  247. .base_address = FLASH_BANK_BASE_S,
  248. .controller_address = 0x400e0a00,
  249. .flash_wait_states = 6, /* workaround silicon bug */
  250. .present = 1,
  251. .size_bytes = 1024 * 1024,
  252. .nsectors = 128,
  253. .sector_size = 8192,
  254. .page_size = 512,
  255. },
  256. /* .bank[1] = {*/
  257. {
  258. .present = 0,
  259. .probed = 0,
  260. .bank_number = 1,
  261. },
  262. },
  263. },
  264. /*atsam4s16b - LQFP64/QFN64*/
  265. {
  266. .chipid_cidr = 0x289C0CE0,
  267. .name = "at91sam4s16b",
  268. .total_flash_size = 1024 * 1024,
  269. .total_sram_size = 128 * 1024,
  270. .n_gpnvms = 2,
  271. .n_banks = 1,
  272. {
  273. /* .bank[0] = {*/
  274. {
  275. .probed = 0,
  276. .pChip = NULL,
  277. .pBank = NULL,
  278. .bank_number = 0,
  279. .base_address = FLASH_BANK_BASE_S,
  280. .controller_address = 0x400e0a00,
  281. .flash_wait_states = 6, /* workaround silicon bug */
  282. .present = 1,
  283. .size_bytes = 1024 * 1024,
  284. .nsectors = 128,
  285. .sector_size = 8192,
  286. .page_size = 512,
  287. },
  288. /* .bank[1] = {*/
  289. {
  290. .present = 0,
  291. .probed = 0,
  292. .bank_number = 1,
  293. },
  294. },
  295. },
  296. /*atsam4s16a - LQFP48/QFN48*/
  297. {
  298. .chipid_cidr = 0x288C0CE0,
  299. .name = "at91sam4s16a",
  300. .total_flash_size = 1024 * 1024,
  301. .total_sram_size = 128 * 1024,
  302. .n_gpnvms = 2,
  303. .n_banks = 1,
  304. {
  305. /* .bank[0] = {*/
  306. {
  307. .probed = 0,
  308. .pChip = NULL,
  309. .pBank = NULL,
  310. .bank_number = 0,
  311. .base_address = FLASH_BANK_BASE_S,
  312. .controller_address = 0x400e0a00,
  313. .flash_wait_states = 6, /* workaround silicon bug */
  314. .present = 1,
  315. .size_bytes = 1024 * 1024,
  316. .nsectors = 128,
  317. .sector_size = 8192,
  318. .page_size = 512,
  319. },
  320. /* .bank[1] = {*/
  321. {
  322. .present = 0,
  323. .probed = 0,
  324. .bank_number = 1,
  325. },
  326. },
  327. },
  328. /*atsam4s8c - LQFP100/BGA100*/
  329. {
  330. .chipid_cidr = 0x28AC0AE0,
  331. .name = "at91sam4s8c",
  332. .total_flash_size = 512 * 1024,
  333. .total_sram_size = 128 * 1024,
  334. .n_gpnvms = 2,
  335. .n_banks = 1,
  336. {
  337. /* .bank[0] = {*/
  338. {
  339. .probed = 0,
  340. .pChip = NULL,
  341. .pBank = NULL,
  342. .bank_number = 0,
  343. .base_address = FLASH_BANK_BASE_S,
  344. .controller_address = 0x400e0a00,
  345. .flash_wait_states = 6, /* workaround silicon bug */
  346. .present = 1,
  347. .size_bytes = 512 * 1024,
  348. .nsectors = 64,
  349. .sector_size = 8192,
  350. .page_size = 512,
  351. },
  352. /* .bank[1] = {*/
  353. {
  354. .present = 0,
  355. .probed = 0,
  356. .bank_number = 1,
  357. },
  358. },
  359. },
  360. /*atsam4s8b - LQFP64/BGA64*/
  361. {
  362. .chipid_cidr = 0x289C0AE0,
  363. .name = "at91sam4s8b",
  364. .total_flash_size = 512 * 1024,
  365. .total_sram_size = 128 * 1024,
  366. .n_gpnvms = 2,
  367. .n_banks = 1,
  368. {
  369. /* .bank[0] = {*/
  370. {
  371. .probed = 0,
  372. .pChip = NULL,
  373. .pBank = NULL,
  374. .bank_number = 0,
  375. .base_address = FLASH_BANK_BASE_S,
  376. .controller_address = 0x400e0a00,
  377. .flash_wait_states = 6, /* workaround silicon bug */
  378. .present = 1,
  379. .size_bytes = 512 * 1024,
  380. .nsectors = 64,
  381. .sector_size = 8192,
  382. .page_size = 512,
  383. },
  384. /* .bank[1] = {*/
  385. {
  386. .present = 0,
  387. .probed = 0,
  388. .bank_number = 1,
  389. },
  390. },
  391. },
  392. /*atsam4s8a - LQFP48/BGA48*/
  393. {
  394. .chipid_cidr = 0x288C0AE0,
  395. .name = "at91sam4s8a",
  396. .total_flash_size = 512 * 1024,
  397. .total_sram_size = 128 * 1024,
  398. .n_gpnvms = 2,
  399. .n_banks = 1,
  400. {
  401. /* .bank[0] = {*/
  402. {
  403. .probed = 0,
  404. .pChip = NULL,
  405. .pBank = NULL,
  406. .bank_number = 0,
  407. .base_address = FLASH_BANK_BASE_S,
  408. .controller_address = 0x400e0a00,
  409. .flash_wait_states = 6, /* workaround silicon bug */
  410. .present = 1,
  411. .size_bytes = 512 * 1024,
  412. .nsectors = 64,
  413. .sector_size = 8192,
  414. .page_size = 512,
  415. },
  416. /* .bank[1] = {*/
  417. {
  418. .present = 0,
  419. .probed = 0,
  420. .bank_number = 1,
  421. },
  422. },
  423. },
  424. /*at91sam4sd32c*/
  425. {
  426. .chipid_cidr = 0x29a70ee0,
  427. .name = "at91sam4sd32c",
  428. .total_flash_size = 2048 * 1024,
  429. .total_sram_size = 160 * 1024,
  430. .n_gpnvms = 3,
  431. .n_banks = 2,
  432. /* .bank[0] = { */
  433. {
  434. {
  435. .probed = 0,
  436. .pChip = NULL,
  437. .pBank = NULL,
  438. .bank_number = 0,
  439. .base_address = FLASH_BANK0_BASE_SD,
  440. .controller_address = 0x400e0a00,
  441. .flash_wait_states = 6, /* workaround silicon bug */
  442. .present = 1,
  443. .size_bytes = 1024 * 1024,
  444. .nsectors = 128,
  445. .sector_size = 8192,
  446. .page_size = 512,
  447. },
  448. /* .bank[1] = { */
  449. {
  450. .probed = 0,
  451. .pChip = NULL,
  452. .pBank = NULL,
  453. .bank_number = 1,
  454. .base_address = FLASH_BANK1_BASE_2048K_SD,
  455. .controller_address = 0x400e0c00,
  456. .flash_wait_states = 6, /* workaround silicon bug */
  457. .present = 1,
  458. .size_bytes = 1024 * 1024,
  459. .nsectors = 128,
  460. .sector_size = 8192,
  461. .page_size = 512,
  462. },
  463. },
  464. },
  465. /* terminate */
  466. {
  467. .chipid_cidr = 0,
  468. .name = NULL,
  469. }
  470. };
  471. /* Globals above */
  472. /***********************************************************************
  473. **********************************************************************
  474. **********************************************************************
  475. **********************************************************************
  476. **********************************************************************
  477. **********************************************************************/
  478. /* *ATMEL* style code - from the SAM4 driver code */
  479. /**
  480. * Get the current status of the EEFC and
  481. * the value of some status bits (LOCKE, PROGE).
  482. * @param pPrivate - info about the bank
  483. * @param v - result goes here
  484. */
  485. static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
  486. {
  487. int r;
  488. r = target_read_u32(pPrivate->pChip->target,
  489. pPrivate->controller_address + offset_EFC_FSR,
  490. v);
  491. LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
  492. (unsigned int)(*v),
  493. ((unsigned int)((*v >> 2) & 1)),
  494. ((unsigned int)((*v >> 1) & 1)),
  495. ((unsigned int)((*v >> 0) & 1)));
  496. return r;
  497. }
  498. /**
  499. * Get the result of the last executed command.
  500. * @param pPrivate - info about the bank
  501. * @param v - result goes here
  502. */
  503. static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
  504. {
  505. int r;
  506. uint32_t rv;
  507. r = target_read_u32(pPrivate->pChip->target,
  508. pPrivate->controller_address + offset_EFC_FRR,
  509. &rv);
  510. if (v)
  511. *v = rv;
  512. LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
  513. return r;
  514. }
  515. static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
  516. unsigned command, unsigned argument)
  517. {
  518. uint32_t n, v;
  519. int r;
  520. int retry;
  521. retry = 0;
  522. do_retry:
  523. /* Check command & argument */
  524. switch (command) {
  525. case AT91C_EFC_FCMD_WP:
  526. case AT91C_EFC_FCMD_WPL:
  527. case AT91C_EFC_FCMD_EWP:
  528. case AT91C_EFC_FCMD_EWPL:
  529. /* case AT91C_EFC_FCMD_EPL: */
  530. case AT91C_EFC_FCMD_EPA:
  531. case AT91C_EFC_FCMD_SLB:
  532. case AT91C_EFC_FCMD_CLB:
  533. n = (pPrivate->size_bytes / pPrivate->page_size);
  534. if (argument >= n)
  535. LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
  536. break;
  537. case AT91C_EFC_FCMD_SFB:
  538. case AT91C_EFC_FCMD_CFB:
  539. if (argument >= pPrivate->pChip->details.n_gpnvms) {
  540. LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
  541. pPrivate->pChip->details.n_gpnvms);
  542. }
  543. break;
  544. case AT91C_EFC_FCMD_GETD:
  545. case AT91C_EFC_FCMD_EA:
  546. case AT91C_EFC_FCMD_GLB:
  547. case AT91C_EFC_FCMD_GFB:
  548. case AT91C_EFC_FCMD_STUI:
  549. case AT91C_EFC_FCMD_SPUI:
  550. if (argument != 0)
  551. LOG_ERROR("Argument is meaningless for cmd: %d", command);
  552. break;
  553. default:
  554. LOG_ERROR("Unknown command %d", command);
  555. break;
  556. }
  557. if (command == AT91C_EFC_FCMD_SPUI) {
  558. /* this is a very special situation. */
  559. /* Situation (1) - error/retry - see below */
  560. /* And we are being called recursively */
  561. /* Situation (2) - normal, finished reading unique id */
  562. } else {
  563. /* it should be "ready" */
  564. EFC_GetStatus(pPrivate, &v);
  565. if (v & 1) {
  566. /* then it is ready */
  567. /* we go on */
  568. } else {
  569. if (retry) {
  570. /* we have done this before */
  571. /* the controller is not responding. */
  572. LOG_ERROR("flash controller(%d) is not ready! Error",
  573. pPrivate->bank_number);
  574. return ERROR_FAIL;
  575. } else {
  576. retry++;
  577. LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
  578. pPrivate->bank_number);
  579. /* we do that by issuing the *STOP* command */
  580. EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
  581. /* above is recursive, and further recursion is blocked by */
  582. /* if (command == AT91C_EFC_FCMD_SPUI) above */
  583. goto do_retry;
  584. }
  585. }
  586. }
  587. v = (0x5A << 24) | (argument << 8) | command;
  588. LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
  589. r = target_write_u32(pPrivate->pBank->target,
  590. pPrivate->controller_address + offset_EFC_FCR, v);
  591. if (r != ERROR_OK)
  592. LOG_DEBUG("Error Write failed");
  593. return r;
  594. }
  595. /**
  596. * Performs the given command and wait until its completion (or an error).
  597. * @param pPrivate - info about the bank
  598. * @param command - Command to perform.
  599. * @param argument - Optional command argument.
  600. * @param status - put command status bits here
  601. */
  602. static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
  603. unsigned command,
  604. unsigned argument,
  605. uint32_t *status)
  606. {
  607. int r;
  608. uint32_t v;
  609. long long ms_now, ms_end;
  610. /* default */
  611. if (status)
  612. *status = 0;
  613. r = EFC_StartCommand(pPrivate, command, argument);
  614. if (r != ERROR_OK)
  615. return r;
  616. ms_end = 10000 + timeval_ms();
  617. do {
  618. r = EFC_GetStatus(pPrivate, &v);
  619. if (r != ERROR_OK)
  620. return r;
  621. ms_now = timeval_ms();
  622. if (ms_now > ms_end) {
  623. /* error */
  624. LOG_ERROR("Command timeout");
  625. return ERROR_FAIL;
  626. }
  627. } while ((v & 1) == 0);
  628. /* error bits.. */
  629. if (status)
  630. *status = (v & 0x6);
  631. return ERROR_OK;
  632. }
  633. /**
  634. * Read the unique ID.
  635. * @param pPrivate - info about the bank
  636. * The unique ID is stored in the 'pPrivate' structure.
  637. */
  638. static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
  639. {
  640. int r;
  641. uint32_t v;
  642. int x;
  643. /* assume 0 */
  644. pPrivate->pChip->cfg.unique_id[0] = 0;
  645. pPrivate->pChip->cfg.unique_id[1] = 0;
  646. pPrivate->pChip->cfg.unique_id[2] = 0;
  647. pPrivate->pChip->cfg.unique_id[3] = 0;
  648. LOG_DEBUG("Begin");
  649. r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
  650. if (r < 0)
  651. return r;
  652. for (x = 0; x < 4; x++) {
  653. r = target_read_u32(pPrivate->pChip->target,
  654. pPrivate->pBank->base + (x * 4),
  655. &v);
  656. if (r < 0)
  657. return r;
  658. pPrivate->pChip->cfg.unique_id[x] = v;
  659. }
  660. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
  661. LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
  662. r,
  663. (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
  664. (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
  665. (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
  666. (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
  667. return r;
  668. }
  669. /**
  670. * Erases the entire flash.
  671. * @param pPrivate - the info about the bank.
  672. */
  673. static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
  674. {
  675. LOG_DEBUG("Here");
  676. return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
  677. }
  678. /**
  679. * Erases the entire flash.
  680. * @param pPrivate - the info about the bank.
  681. */
  682. static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
  683. int firstPage,
  684. int numPages,
  685. uint32_t *status)
  686. {
  687. LOG_DEBUG("Here");
  688. uint8_t erasePages;
  689. switch (numPages) {
  690. case 4:
  691. erasePages = 0x00;
  692. break;
  693. case 8:
  694. erasePages = 0x01;
  695. break;
  696. case 16:
  697. erasePages = 0x02;
  698. break;
  699. case 32:
  700. erasePages = 0x03;
  701. break;
  702. default:
  703. erasePages = 0x00;
  704. break;
  705. }
  706. /* AT91C_EFC_FCMD_EPA
  707. * According to the datasheet FARG[15:2] defines the page from which
  708. * the erase will start.This page must be modulo 4, 8, 16 or 32
  709. * according to the number of pages to erase. FARG[1:0] defines the
  710. * number of pages to be erased. Previously (firstpage << 2) was used
  711. * to conform to this, seems it should not be shifted...
  712. */
  713. return EFC_PerformCommand(pPrivate,
  714. /* send Erase Page */
  715. AT91C_EFC_FCMD_EPA,
  716. (firstPage) | erasePages,
  717. status);
  718. }
  719. /**
  720. * Gets current GPNVM state.
  721. * @param pPrivate - info about the bank.
  722. * @param gpnvm - GPNVM bit index.
  723. * @param puthere - result stored here.
  724. */
  725. /* ------------------------------------------------------------------------------ */
  726. static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
  727. {
  728. uint32_t v;
  729. int r;
  730. LOG_DEBUG("Here");
  731. if (pPrivate->bank_number != 0) {
  732. LOG_ERROR("GPNVM only works with Bank0");
  733. return ERROR_FAIL;
  734. }
  735. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  736. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  737. gpnvm, pPrivate->pChip->details.n_gpnvms);
  738. return ERROR_FAIL;
  739. }
  740. /* Get GPNVMs status */
  741. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
  742. if (r != ERROR_OK) {
  743. LOG_ERROR("Failed");
  744. return r;
  745. }
  746. r = EFC_GetResult(pPrivate, &v);
  747. if (puthere) {
  748. /* Check if GPNVM is set */
  749. /* get the bit and make it a 0/1 */
  750. *puthere = (v >> gpnvm) & 1;
  751. }
  752. return r;
  753. }
  754. /**
  755. * Clears the selected GPNVM bit.
  756. * @param pPrivate info about the bank
  757. * @param gpnvm GPNVM index.
  758. * @returns 0 if successful; otherwise returns an error code.
  759. */
  760. static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  761. {
  762. int r;
  763. unsigned v;
  764. LOG_DEBUG("Here");
  765. if (pPrivate->bank_number != 0) {
  766. LOG_ERROR("GPNVM only works with Bank0");
  767. return ERROR_FAIL;
  768. }
  769. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  770. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  771. gpnvm, pPrivate->pChip->details.n_gpnvms);
  772. return ERROR_FAIL;
  773. }
  774. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  775. if (r != ERROR_OK) {
  776. LOG_DEBUG("Failed: %d", r);
  777. return r;
  778. }
  779. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
  780. LOG_DEBUG("End: %d", r);
  781. return r;
  782. }
  783. /**
  784. * Sets the selected GPNVM bit.
  785. * @param pPrivate info about the bank
  786. * @param gpnvm GPNVM index.
  787. */
  788. static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  789. {
  790. int r;
  791. unsigned v;
  792. if (pPrivate->bank_number != 0) {
  793. LOG_ERROR("GPNVM only works with Bank0");
  794. return ERROR_FAIL;
  795. }
  796. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  797. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  798. gpnvm, pPrivate->pChip->details.n_gpnvms);
  799. return ERROR_FAIL;
  800. }
  801. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  802. if (r != ERROR_OK)
  803. return r;
  804. if (v) {
  805. /* already set */
  806. r = ERROR_OK;
  807. } else {
  808. /* set it */
  809. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
  810. }
  811. return r;
  812. }
  813. /**
  814. * Returns a bit field (at most 64) of locked regions within a page.
  815. * @param pPrivate info about the bank
  816. * @param v where to store locked bits
  817. */
  818. static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
  819. {
  820. int r;
  821. LOG_DEBUG("Here");
  822. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
  823. if (r == ERROR_OK) {
  824. EFC_GetResult(pPrivate, v);
  825. EFC_GetResult(pPrivate, v);
  826. EFC_GetResult(pPrivate, v);
  827. r = EFC_GetResult(pPrivate, v);
  828. }
  829. LOG_DEBUG("End: %d", r);
  830. return r;
  831. }
  832. /**
  833. * Unlocks all the regions in the given address range.
  834. * @param pPrivate info about the bank
  835. * @param start_sector first sector to unlock
  836. * @param end_sector last (inclusive) to unlock
  837. */
  838. static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
  839. unsigned start_sector,
  840. unsigned end_sector)
  841. {
  842. int r;
  843. uint32_t status;
  844. uint32_t pg;
  845. uint32_t pages_per_sector;
  846. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  847. /* Unlock all pages */
  848. while (start_sector <= end_sector) {
  849. pg = start_sector * pages_per_sector;
  850. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
  851. if (r != ERROR_OK)
  852. return r;
  853. start_sector++;
  854. }
  855. return ERROR_OK;
  856. }
  857. /**
  858. * Locks regions
  859. * @param pPrivate - info about the bank
  860. * @param start_sector - first sector to lock
  861. * @param end_sector - last sector (inclusive) to lock
  862. */
  863. static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
  864. unsigned start_sector,
  865. unsigned end_sector)
  866. {
  867. uint32_t status;
  868. uint32_t pg;
  869. uint32_t pages_per_sector;
  870. int r;
  871. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  872. /* Lock all pages */
  873. while (start_sector <= end_sector) {
  874. pg = start_sector * pages_per_sector;
  875. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
  876. if (r != ERROR_OK)
  877. return r;
  878. start_sector++;
  879. }
  880. return ERROR_OK;
  881. }
  882. /****** END SAM4 CODE ********/
  883. /* begin helpful debug code */
  884. /* print the fieldname, the field value, in dec & hex, and return field value */
  885. static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
  886. const char *regname,
  887. uint32_t value,
  888. unsigned shift,
  889. unsigned width)
  890. {
  891. uint32_t v;
  892. int hwidth, dwidth;
  893. /* extract the field */
  894. v = value >> shift;
  895. v = v & ((1 << width)-1);
  896. if (width <= 16) {
  897. hwidth = 4;
  898. dwidth = 5;
  899. } else {
  900. hwidth = 8;
  901. dwidth = 12;
  902. }
  903. /* show the basics */
  904. LOG_USER_N("\t%*s: %*d [0x%0*x] ",
  905. REG_NAME_WIDTH, regname,
  906. dwidth, v,
  907. hwidth, v);
  908. return v;
  909. }
  910. static const char _unknown[] = "unknown";
  911. static const char *const eproc_names[] = {
  912. _unknown, /* 0 */
  913. "arm946es", /* 1 */
  914. "arm7tdmi", /* 2 */
  915. "cortex-m3", /* 3 */
  916. "arm920t", /* 4 */
  917. "arm926ejs", /* 5 */
  918. "cortex-a5", /* 6 */
  919. "cortex-m4", /* 7 */
  920. _unknown, /* 8 */
  921. _unknown, /* 9 */
  922. _unknown, /* 10 */
  923. _unknown, /* 11 */
  924. _unknown, /* 12 */
  925. _unknown, /* 13 */
  926. _unknown, /* 14 */
  927. _unknown, /* 15 */
  928. };
  929. #define nvpsize2 nvpsize /* these two tables are identical */
  930. static const char *const nvpsize[] = {
  931. "none", /* 0 */
  932. "8K bytes", /* 1 */
  933. "16K bytes", /* 2 */
  934. "32K bytes", /* 3 */
  935. _unknown, /* 4 */
  936. "64K bytes", /* 5 */
  937. _unknown, /* 6 */
  938. "128K bytes", /* 7 */
  939. _unknown, /* 8 */
  940. "256K bytes", /* 9 */
  941. "512K bytes", /* 10 */
  942. _unknown, /* 11 */
  943. "1024K bytes", /* 12 */
  944. _unknown, /* 13 */
  945. "2048K bytes", /* 14 */
  946. _unknown, /* 15 */
  947. };
  948. static const char *const sramsize[] = {
  949. "48K Bytes", /* 0 */
  950. "1K Bytes", /* 1 */
  951. "2K Bytes", /* 2 */
  952. "6K Bytes", /* 3 */
  953. "112K Bytes", /* 4 */
  954. "4K Bytes", /* 5 */
  955. "80K Bytes", /* 6 */
  956. "160K Bytes", /* 7 */
  957. "8K Bytes", /* 8 */
  958. "16K Bytes", /* 9 */
  959. "32K Bytes", /* 10 */
  960. "64K Bytes", /* 11 */
  961. "128K Bytes", /* 12 */
  962. "256K Bytes", /* 13 */
  963. "96K Bytes", /* 14 */
  964. "512K Bytes", /* 15 */
  965. };
  966. static const struct archnames { unsigned value; const char *name; } archnames[] = {
  967. { 0x19, "AT91SAM9xx Series" },
  968. { 0x29, "AT91SAM9XExx Series" },
  969. { 0x34, "AT91x34 Series" },
  970. { 0x37, "CAP7 Series" },
  971. { 0x39, "CAP9 Series" },
  972. { 0x3B, "CAP11 Series" },
  973. { 0x40, "AT91x40 Series" },
  974. { 0x42, "AT91x42 Series" },
  975. { 0x55, "AT91x55 Series" },
  976. { 0x60, "AT91SAM7Axx Series" },
  977. { 0x61, "AT91SAM7AQxx Series" },
  978. { 0x63, "AT91x63 Series" },
  979. { 0x70, "AT91SAM7Sxx Series" },
  980. { 0x71, "AT91SAM7XCxx Series" },
  981. { 0x72, "AT91SAM7SExx Series" },
  982. { 0x73, "AT91SAM7Lxx Series" },
  983. { 0x75, "AT91SAM7Xxx Series" },
  984. { 0x76, "AT91SAM7SLxx Series" },
  985. { 0x80, "ATSAM3UxC Series (100-pin version)" },
  986. { 0x81, "ATSAM3UxE Series (144-pin version)" },
  987. { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
  988. { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
  989. { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
  990. { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
  991. { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
  992. { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
  993. { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
  994. { 0x92, "AT91x92 Series" },
  995. { 0x93, "ATSAM3NxA Series (48-pin version)" },
  996. { 0x94, "ATSAM3NxB Series (64-pin version)" },
  997. { 0x95, "ATSAM3NxC Series (100-pin version)" },
  998. { 0x98, "ATSAM3SDxA Series (48-pin version)" },
  999. { 0x99, "ATSAM3SDxB Series (64-pin version)" },
  1000. { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
  1001. { 0xA5, "ATSAM5A" },
  1002. { 0xF0, "AT75Cxx Series" },
  1003. { -1, NULL },
  1004. };
  1005. static const char *const nvptype[] = {
  1006. "rom", /* 0 */
  1007. "romless or onchip flash", /* 1 */
  1008. "embedded flash memory",/* 2 */
  1009. "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
  1010. "sram emulating flash", /* 4 */
  1011. _unknown, /* 5 */
  1012. _unknown, /* 6 */
  1013. _unknown, /* 7 */
  1014. };
  1015. static const char *_yes_or_no(uint32_t v)
  1016. {
  1017. if (v)
  1018. return "YES";
  1019. else
  1020. return "NO";
  1021. }
  1022. static const char *const _rc_freq[] = {
  1023. "4 MHz", "8 MHz", "12 MHz", "reserved"
  1024. };
  1025. static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
  1026. {
  1027. uint32_t v;
  1028. uint32_t rcen;
  1029. v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
  1030. LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
  1031. v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
  1032. LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
  1033. rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
  1034. LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
  1035. v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
  1036. LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
  1037. pChip->cfg.rc_freq = 0;
  1038. if (rcen) {
  1039. switch (v) {
  1040. default:
  1041. pChip->cfg.rc_freq = 0;
  1042. break;
  1043. case 0:
  1044. pChip->cfg.rc_freq = 4 * 1000 * 1000;
  1045. break;
  1046. case 1:
  1047. pChip->cfg.rc_freq = 8 * 1000 * 1000;
  1048. break;
  1049. case 2:
  1050. pChip->cfg.rc_freq = 12 * 1000 * 1000;
  1051. break;
  1052. }
  1053. }
  1054. v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
  1055. LOG_USER("(startup clks, time= %f uSecs)",
  1056. ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
  1057. v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
  1058. LOG_USER("(mainosc source: %s)",
  1059. v ? "external xtal" : "internal RC");
  1060. v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
  1061. LOG_USER("(clock failure enabled: %s)",
  1062. _yes_or_no(v));
  1063. }
  1064. static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
  1065. {
  1066. int x;
  1067. uint32_t v;
  1068. const char *cp;
  1069. sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
  1070. LOG_USER_N("\n");
  1071. v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
  1072. LOG_USER("%s", eproc_names[v]);
  1073. v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
  1074. LOG_USER("%s", nvpsize[v]);
  1075. v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
  1076. LOG_USER("%s", nvpsize2[v]);
  1077. v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
  1078. LOG_USER("%s", sramsize[v]);
  1079. v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
  1080. cp = _unknown;
  1081. for (x = 0; archnames[x].name; x++) {
  1082. if (v == archnames[x].value) {
  1083. cp = archnames[x].name;
  1084. break;
  1085. }
  1086. }
  1087. LOG_USER("%s", cp);
  1088. v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
  1089. LOG_USER("%s", nvptype[v]);
  1090. v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
  1091. LOG_USER("(exists: %s)", _yes_or_no(v));
  1092. }
  1093. static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
  1094. {
  1095. uint32_t v;
  1096. v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
  1097. LOG_USER("(main ready: %s)", _yes_or_no(v));
  1098. v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
  1099. v = (v * pChip->cfg.slow_freq) / 16;
  1100. pChip->cfg.mainosc_freq = v;
  1101. LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
  1102. _tomhz(v),
  1103. pChip->cfg.slow_freq / 1000,
  1104. pChip->cfg.slow_freq % 1000);
  1105. }
  1106. static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
  1107. {
  1108. uint32_t mula, diva;
  1109. diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
  1110. LOG_USER_N("\n");
  1111. mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
  1112. LOG_USER_N("\n");
  1113. pChip->cfg.plla_freq = 0;
  1114. if (mula == 0)
  1115. LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
  1116. else if (diva == 0)
  1117. LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
  1118. else if (diva == 1) {
  1119. pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
  1120. LOG_USER("\tPLLA Freq: %3.03f MHz",
  1121. _tomhz(pChip->cfg.plla_freq));
  1122. }
  1123. }
  1124. static void sam4_explain_mckr(struct sam4_chip *pChip)
  1125. {
  1126. uint32_t css, pres, fin = 0;
  1127. int pdiv = 0;
  1128. const char *cp = NULL;
  1129. css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
  1130. switch (css & 3) {
  1131. case 0:
  1132. fin = pChip->cfg.slow_freq;
  1133. cp = "slowclk";
  1134. break;
  1135. case 1:
  1136. fin = pChip->cfg.mainosc_freq;
  1137. cp = "mainosc";
  1138. break;
  1139. case 2:
  1140. fin = pChip->cfg.plla_freq;
  1141. cp = "plla";
  1142. break;
  1143. case 3:
  1144. if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
  1145. fin = 480 * 1000 * 1000;
  1146. cp = "upll";
  1147. } else {
  1148. fin = 0;
  1149. cp = "upll (*ERROR* UPLL is disabled)";
  1150. }
  1151. break;
  1152. default:
  1153. assert(0);
  1154. break;
  1155. }
  1156. LOG_USER("%s (%3.03f Mhz)",
  1157. cp,
  1158. _tomhz(fin));
  1159. pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
  1160. switch (pres & 0x07) {
  1161. case 0:
  1162. pdiv = 1;
  1163. cp = "selected clock";
  1164. break;
  1165. case 1:
  1166. pdiv = 2;
  1167. cp = "clock/2";
  1168. break;
  1169. case 2:
  1170. pdiv = 4;
  1171. cp = "clock/4";
  1172. break;
  1173. case 3:
  1174. pdiv = 8;
  1175. cp = "clock/8";
  1176. break;
  1177. case 4:
  1178. pdiv = 16;
  1179. cp = "clock/16";
  1180. break;
  1181. case 5:
  1182. pdiv = 32;
  1183. cp = "clock/32";
  1184. break;
  1185. case 6:
  1186. pdiv = 64;
  1187. cp = "clock/64";
  1188. break;
  1189. case 7:
  1190. pdiv = 6;
  1191. cp = "clock/6";
  1192. break;
  1193. default:
  1194. assert(0);
  1195. break;
  1196. }
  1197. LOG_USER("(%s)", cp);
  1198. fin = fin / pdiv;
  1199. /* sam4 has a *SINGLE* clock - */
  1200. /* other at91 series parts have divisors for these. */
  1201. pChip->cfg.cpu_freq = fin;
  1202. pChip->cfg.mclk_freq = fin;
  1203. pChip->cfg.fclk_freq = fin;
  1204. LOG_USER("\t\tResult CPU Freq: %3.03f",
  1205. _tomhz(fin));
  1206. }
  1207. #if 0
  1208. static struct sam4_chip *target2sam4(struct target *pTarget)
  1209. {
  1210. struct sam4_chip *pChip;
  1211. if (pTarget == NULL)
  1212. return NULL;
  1213. pChip = all_sam4_chips;
  1214. while (pChip) {
  1215. if (pChip->target == pTarget)
  1216. break; /* return below */
  1217. else
  1218. pChip = pChip->next;
  1219. }
  1220. return pChip;
  1221. }
  1222. #endif
  1223. static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
  1224. {
  1225. /* this function exists to help */
  1226. /* keep funky offsetof() errors */
  1227. /* and casting from causing bugs */
  1228. /* By using prototypes - we can detect what would */
  1229. /* be casting errors. */
  1230. return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
  1231. }
  1232. #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
  1233. struct sam4_cfg, \
  1234. NAME), # NAME, FUNC }
  1235. static const struct sam4_reg_list sam4_all_regs[] = {
  1236. SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
  1237. SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
  1238. SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
  1239. SAM4_ENTRY(CKGR_UCKR, NULL),
  1240. SAM4_ENTRY(PMC_FSMR, NULL),
  1241. SAM4_ENTRY(PMC_FSPR, NULL),
  1242. SAM4_ENTRY(PMC_IMR, NULL),
  1243. SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
  1244. SAM4_ENTRY(PMC_PCK0, NULL),
  1245. SAM4_ENTRY(PMC_PCK1, NULL),
  1246. SAM4_ENTRY(PMC_PCK2, NULL),
  1247. SAM4_ENTRY(PMC_PCSR, NULL),
  1248. SAM4_ENTRY(PMC_SCSR, NULL),
  1249. SAM4_ENTRY(PMC_SR, NULL),
  1250. SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
  1251. SAM4_ENTRY(CHIPID_EXID, NULL),
  1252. /* TERMINATE THE LIST */
  1253. { .name = NULL }
  1254. };
  1255. #undef SAM4_ENTRY
  1256. static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
  1257. {
  1258. return (struct sam4_bank_private *)(bank->driver_priv);
  1259. }
  1260. /**
  1261. * Given a pointer to where it goes in the structure,
  1262. * determine the register name, address from the all registers table.
  1263. */
  1264. static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1265. {
  1266. const struct sam4_reg_list *pReg;
  1267. pReg = &(sam4_all_regs[0]);
  1268. while (pReg->name) {
  1269. uint32_t *pPossible;
  1270. /* calculate where this one go.. */
  1271. /* it is "possibly" this register. */
  1272. pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
  1273. /* well? Is it this register */
  1274. if (pPossible == goes_here) {
  1275. /* Jump for joy! */
  1276. return pReg;
  1277. }
  1278. /* next... */
  1279. pReg++;
  1280. }
  1281. /* This is *TOTAL*PANIC* - we are totally screwed. */
  1282. LOG_ERROR("INVALID SAM4 REGISTER");
  1283. return NULL;
  1284. }
  1285. static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1286. {
  1287. const struct sam4_reg_list *pReg;
  1288. int r;
  1289. pReg = sam4_GetReg(pChip, goes_here);
  1290. if (!pReg)
  1291. return ERROR_FAIL;
  1292. r = target_read_u32(pChip->target, pReg->address, goes_here);
  1293. if (r != ERROR_OK) {
  1294. LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
  1295. pReg->name, (unsigned)(pReg->address), r);
  1296. }
  1297. return r;
  1298. }
  1299. static int sam4_ReadAllRegs(struct sam4_chip *pChip)
  1300. {
  1301. int r;
  1302. const struct sam4_reg_list *pReg;
  1303. pReg = &(sam4_all_regs[0]);
  1304. while (pReg->name) {
  1305. r = sam4_ReadThisReg(pChip,
  1306. sam4_get_reg_ptr(&(pChip->cfg), pReg));
  1307. if (r != ERROR_OK) {
  1308. LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
  1309. pReg->name, ((unsigned)(pReg->address)), r);
  1310. return r;
  1311. }
  1312. pReg++;
  1313. }
  1314. return ERROR_OK;
  1315. }
  1316. static int sam4_GetInfo(struct sam4_chip *pChip)
  1317. {
  1318. const struct sam4_reg_list *pReg;
  1319. uint32_t regval;
  1320. pReg = &(sam4_all_regs[0]);
  1321. while (pReg->name) {
  1322. /* display all regs */
  1323. LOG_DEBUG("Start: %s", pReg->name);
  1324. regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
  1325. LOG_USER("%*s: [0x%08x] -> 0x%08x",
  1326. REG_NAME_WIDTH,
  1327. pReg->name,
  1328. pReg->address,
  1329. regval);
  1330. if (pReg->explain_func)
  1331. (*(pReg->explain_func))(pChip);
  1332. LOG_DEBUG("End: %s", pReg->name);
  1333. pReg++;
  1334. }
  1335. LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
  1336. LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
  1337. LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
  1338. LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
  1339. LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
  1340. LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
  1341. pChip->cfg.unique_id[0],
  1342. pChip->cfg.unique_id[1],
  1343. pChip->cfg.unique_id[2],
  1344. pChip->cfg.unique_id[3]);
  1345. return ERROR_OK;
  1346. }
  1347. static int sam4_protect_check(struct flash_bank *bank)
  1348. {
  1349. int r;
  1350. uint32_t v[4] = {0};
  1351. unsigned x;
  1352. struct sam4_bank_private *pPrivate;
  1353. LOG_DEBUG("Begin");
  1354. if (bank->target->state != TARGET_HALTED) {
  1355. LOG_ERROR("Target not halted");
  1356. return ERROR_TARGET_NOT_HALTED;
  1357. }
  1358. pPrivate = get_sam4_bank_private(bank);
  1359. if (!pPrivate) {
  1360. LOG_ERROR("no private for this bank?");
  1361. return ERROR_FAIL;
  1362. }
  1363. if (!(pPrivate->probed))
  1364. return ERROR_FLASH_BANK_NOT_PROBED;
  1365. r = FLASHD_GetLockBits(pPrivate, v);
  1366. if (r != ERROR_OK) {
  1367. LOG_DEBUG("Failed: %d", r);
  1368. return r;
  1369. }
  1370. for (x = 0; x < pPrivate->nsectors; x++)
  1371. bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
  1372. LOG_DEBUG("Done");
  1373. return ERROR_OK;
  1374. }
  1375. FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
  1376. {
  1377. struct sam4_chip *pChip;
  1378. pChip = all_sam4_chips;
  1379. /* is this an existing chip? */
  1380. while (pChip) {
  1381. if (pChip->target == bank->target)
  1382. break;
  1383. pChip = pChip->next;
  1384. }
  1385. if (!pChip) {
  1386. /* this is a *NEW* chip */
  1387. pChip = calloc(1, sizeof(struct sam4_chip));
  1388. if (!pChip) {
  1389. LOG_ERROR("NO RAM!");
  1390. return ERROR_FAIL;
  1391. }
  1392. pChip->target = bank->target;
  1393. /* insert at head */
  1394. pChip->next = all_sam4_chips;
  1395. all_sam4_chips = pChip;
  1396. pChip->target = bank->target;
  1397. /* assumption is this runs at 32khz */
  1398. pChip->cfg.slow_freq = 32768;
  1399. pChip->probed = 0;
  1400. }
  1401. switch (bank->base) {
  1402. default:
  1403. LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
  1404. "[at91sam4s series] )",
  1405. ((unsigned int)(bank->base)),
  1406. ((unsigned int)(FLASH_BANK_BASE_S)));
  1407. return ERROR_FAIL;
  1408. break;
  1409. /* at91sam4s series only has bank 0*/
  1410. /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
  1411. case FLASH_BANK_BASE_S:
  1412. bank->driver_priv = &(pChip->details.bank[0]);
  1413. bank->bank_number = 0;
  1414. pChip->details.bank[0].pChip = pChip;
  1415. pChip->details.bank[0].pBank = bank;
  1416. break;
  1417. /* Bank 1 of at91sam4sd series */
  1418. case FLASH_BANK1_BASE_1024K_SD:
  1419. case FLASH_BANK1_BASE_2048K_SD:
  1420. bank->driver_priv = &(pChip->details.bank[1]);
  1421. bank->bank_number = 1;
  1422. pChip->details.bank[1].pChip = pChip;
  1423. pChip->details.bank[1].pBank = bank;
  1424. break;
  1425. }
  1426. /* we initialize after probing. */
  1427. return ERROR_OK;
  1428. }
  1429. static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
  1430. {
  1431. const struct sam4_chip_details *pDetails;
  1432. struct sam4_chip *pChip;
  1433. struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
  1434. unsigned x;
  1435. LOG_DEBUG("Begin");
  1436. pDetails = all_sam4_details;
  1437. while (pDetails->name) {
  1438. /* Compare cidr without version bits */
  1439. if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
  1440. break;
  1441. else
  1442. pDetails++;
  1443. }
  1444. if (pDetails->name == NULL) {
  1445. LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
  1446. (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
  1447. /* Help the victim, print details about the chip */
  1448. LOG_INFO("SAM4 CHIPID_CIDR: 0x%08x decodes as follows",
  1449. pPrivate->pChip->cfg.CHIPID_CIDR);
  1450. sam4_explain_chipid_cidr(pPrivate->pChip);
  1451. return ERROR_FAIL;
  1452. }
  1453. /* DANGER: THERE ARE DRAGONS HERE */
  1454. /* get our pChip - it is going */
  1455. /* to be over-written shortly */
  1456. pChip = pPrivate->pChip;
  1457. /* Note that, in reality: */
  1458. /* */
  1459. /* pPrivate = &(pChip->details.bank[0]) */
  1460. /* or pPrivate = &(pChip->details.bank[1]) */
  1461. /* */
  1462. /* save the "bank" pointers */
  1463. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
  1464. saved_banks[x] = pChip->details.bank[x].pBank;
  1465. /* Overwrite the "details" structure. */
  1466. memcpy(&(pPrivate->pChip->details),
  1467. pDetails,
  1468. sizeof(pPrivate->pChip->details));
  1469. /* now fix the ghosted pointers */
  1470. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1471. pChip->details.bank[x].pChip = pChip;
  1472. pChip->details.bank[x].pBank = saved_banks[x];
  1473. }
  1474. /* update the *BANK*SIZE* */
  1475. LOG_DEBUG("End");
  1476. return ERROR_OK;
  1477. }
  1478. static int _sam4_probe(struct flash_bank *bank, int noise)
  1479. {
  1480. unsigned x;
  1481. int r;
  1482. struct sam4_bank_private *pPrivate;
  1483. LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
  1484. if (bank->target->state != TARGET_HALTED) {
  1485. LOG_ERROR("Target not halted");
  1486. return ERROR_TARGET_NOT_HALTED;
  1487. }
  1488. pPrivate = get_sam4_bank_private(bank);
  1489. if (!pPrivate) {
  1490. LOG_ERROR("Invalid/unknown bank number");
  1491. return ERROR_FAIL;
  1492. }
  1493. r = sam4_ReadAllRegs(pPrivate->pChip);
  1494. if (r != ERROR_OK)
  1495. return r;
  1496. LOG_DEBUG("Here");
  1497. if (pPrivate->pChip->probed)
  1498. r = sam4_GetInfo(pPrivate->pChip);
  1499. else
  1500. r = sam4_GetDetails(pPrivate);
  1501. if (r != ERROR_OK)
  1502. return r;
  1503. /* update the flash bank size */
  1504. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1505. if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
  1506. bank->size = pPrivate->pChip->details.bank[x].size_bytes;
  1507. break;
  1508. }
  1509. }
  1510. if (bank->sectors == NULL) {
  1511. bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
  1512. if (bank->sectors == NULL) {
  1513. LOG_ERROR("No memory!");
  1514. return ERROR_FAIL;
  1515. }
  1516. bank->num_sectors = pPrivate->nsectors;
  1517. for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
  1518. bank->sectors[x].size = pPrivate->sector_size;
  1519. bank->sectors[x].offset = x * (pPrivate->sector_size);
  1520. /* mark as unknown */
  1521. bank->sectors[x].is_erased = -1;
  1522. bank->sectors[x].is_protected = -1;
  1523. }
  1524. }
  1525. pPrivate->probed = 1;
  1526. r = sam4_protect_check(bank);
  1527. if (r != ERROR_OK)
  1528. return r;
  1529. LOG_DEBUG("Bank = %d, nbanks = %d",
  1530. pPrivate->bank_number, pPrivate->pChip->details.n_banks);
  1531. if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
  1532. /* read unique id, */
  1533. /* it appears to be associated with the *last* flash bank. */
  1534. FLASHD_ReadUniqueID(pPrivate);
  1535. }
  1536. return r;
  1537. }
  1538. static int sam4_probe(struct flash_bank *bank)
  1539. {
  1540. return _sam4_probe(bank, 1);
  1541. }
  1542. static int sam4_auto_probe(struct flash_bank *bank)
  1543. {
  1544. return _sam4_probe(bank, 0);
  1545. }
  1546. static int sam4_erase(struct flash_bank *bank, int first, int last)
  1547. {
  1548. struct sam4_bank_private *pPrivate;
  1549. int r;
  1550. int i;
  1551. int pageCount;
  1552. /*16 pages equals 8KB - Same size as a lock region*/
  1553. pageCount = 16;
  1554. uint32_t status;
  1555. LOG_DEBUG("Here");
  1556. if (bank->target->state != TARGET_HALTED) {
  1557. LOG_ERROR("Target not halted");
  1558. return ERROR_TARGET_NOT_HALTED;
  1559. }
  1560. r = sam4_auto_probe(bank);
  1561. if (r != ERROR_OK) {
  1562. LOG_DEBUG("Here,r=%d", r);
  1563. return r;
  1564. }
  1565. pPrivate = get_sam4_bank_private(bank);
  1566. if (!(pPrivate->probed))
  1567. return ERROR_FLASH_BANK_NOT_PROBED;
  1568. if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
  1569. /* whole chip */
  1570. LOG_DEBUG("Here");
  1571. return FLASHD_EraseEntireBank(pPrivate);
  1572. }
  1573. LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
  1574. LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
  1575. for (i = first; i <= last; i++) {
  1576. /*16 pages equals 8KB - Same size as a lock region*/
  1577. r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
  1578. LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
  1579. if (r != ERROR_OK)
  1580. LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
  1581. (unsigned int)(i));
  1582. if (status & (1 << 2)) {
  1583. LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
  1584. return ERROR_FAIL;
  1585. }
  1586. if (status & (1 << 1)) {
  1587. LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
  1588. return ERROR_FAIL;
  1589. }
  1590. }
  1591. return ERROR_OK;
  1592. }
  1593. static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
  1594. {
  1595. struct sam4_bank_private *pPrivate;
  1596. int r;
  1597. LOG_DEBUG("Here");
  1598. if (bank->target->state != TARGET_HALTED) {
  1599. LOG_ERROR("Target not halted");
  1600. return ERROR_TARGET_NOT_HALTED;
  1601. }
  1602. pPrivate = get_sam4_bank_private(bank);
  1603. if (!(pPrivate->probed))
  1604. return ERROR_FLASH_BANK_NOT_PROBED;
  1605. if (set)
  1606. r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
  1607. else
  1608. r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
  1609. LOG_DEBUG("End: r=%d", r);
  1610. return r;
  1611. }
  1612. static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
  1613. {
  1614. if (bank->target->state != TARGET_HALTED) {
  1615. LOG_ERROR("Target not halted");
  1616. return ERROR_TARGET_NOT_HALTED;
  1617. }
  1618. buf[0] = 0;
  1619. return ERROR_OK;
  1620. }
  1621. static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  1622. {
  1623. uint32_t adr;
  1624. int r;
  1625. adr = pagenum * pPrivate->page_size;
  1626. adr = adr + pPrivate->base_address;
  1627. r = target_read_memory(pPrivate->pChip->target,
  1628. adr,
  1629. 4, /* THIS*MUST*BE* in 32bit values */
  1630. pPrivate->page_size / 4,
  1631. buf);
  1632. if (r != ERROR_OK)
  1633. LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
  1634. (unsigned int)(adr));
  1635. return r;
  1636. }
  1637. /* The code below is basically this: */
  1638. /* compiled with */
  1639. /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
  1640. /* */
  1641. /* Only the *CPU* can write to the flash buffer. */
  1642. /* the DAP cannot... so - we download this 28byte thing */
  1643. /* Run the algorithm - (below) */
  1644. /* to program the device */
  1645. /* */
  1646. /* ======================================== */
  1647. /* #include <stdint.h> */
  1648. /* */
  1649. /* struct foo { */
  1650. /* uint32_t *dst; */
  1651. /* const uint32_t *src; */
  1652. /* int n; */
  1653. /* volatile uint32_t *base; */
  1654. /* uint32_t cmd; */
  1655. /* }; */
  1656. /* */
  1657. /* */
  1658. /* uint32_t sam4_function(struct foo *p) */
  1659. /* { */
  1660. /* volatile uint32_t *v; */
  1661. /* uint32_t *d; */
  1662. /* const uint32_t *s; */
  1663. /* int n; */
  1664. /* uint32_t r; */
  1665. /* */
  1666. /* d = p->dst; */
  1667. /* s = p->src; */
  1668. /* n = p->n; */
  1669. /* */
  1670. /* do { */
  1671. /* *d++ = *s++; */
  1672. /* } while (--n) */
  1673. /* ; */
  1674. /* */
  1675. /* v = p->base; */
  1676. /* */
  1677. /* v[ 1 ] = p->cmd; */
  1678. /* do { */
  1679. /* r = v[8/4]; */
  1680. /* } while (!(r&1)) */
  1681. /* ; */
  1682. /* return r; */
  1683. /* } */
  1684. /* ======================================== */
  1685. static const uint8_t
  1686. sam4_page_write_opcodes[] = {
  1687. /* 24 0000 0446 mov r4, r0 */
  1688. 0x04, 0x46,
  1689. /* 25 0002 6168 ldr r1, [r4, #4] */
  1690. 0x61, 0x68,
  1691. /* 26 0004 0068 ldr r0, [r0, #0] */
  1692. 0x00, 0x68,
  1693. /* 27 0006 A268 ldr r2, [r4, #8] */
  1694. 0xa2, 0x68,
  1695. /* 28 @ lr needed for prologue */
  1696. /* 29 .L2: */
  1697. /* 30 0008 51F8043B ldr r3, [r1], #4 */
  1698. 0x51, 0xf8, 0x04, 0x3b,
  1699. /* 31 000c 12F1FF32 adds r2, r2, #-1 */
  1700. 0x12, 0xf1, 0xff, 0x32,
  1701. /* 32 0010 40F8043B str r3, [r0], #4 */
  1702. 0x40, 0xf8, 0x04, 0x3b,
  1703. /* 33 0014 F8D1 bne .L2 */
  1704. 0xf8, 0xd1,
  1705. /* 34 0016 E268 ldr r2, [r4, #12] */
  1706. 0xe2, 0x68,
  1707. /* 35 0018 2369 ldr r3, [r4, #16] */
  1708. 0x23, 0x69,
  1709. /* 36 001a 5360 str r3, [r2, #4] */
  1710. 0x53, 0x60,
  1711. /* 37 001c 0832 adds r2, r2, #8 */
  1712. 0x08, 0x32,
  1713. /* 38 .L4: */
  1714. /* 39 001e 1068 ldr r0, [r2, #0] */
  1715. 0x10, 0x68,
  1716. /* 40 0020 10F0010F tst r0, #1 */
  1717. 0x10, 0xf0, 0x01, 0x0f,
  1718. /* 41 0024 FBD0 beq .L4 */
  1719. 0xfb, 0xd0,
  1720. 0x00, 0xBE /* bkpt #0 */
  1721. };
  1722. static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  1723. {
  1724. uint32_t adr;
  1725. uint32_t status;
  1726. uint32_t fmr; /* EEFC Flash Mode Register */
  1727. int r;
  1728. adr = pagenum * pPrivate->page_size;
  1729. adr = (adr + pPrivate->base_address);
  1730. /* Get flash mode register value */
  1731. r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
  1732. if (r != ERROR_OK)
  1733. LOG_DEBUG("Error Read failed: read flash mode register");
  1734. /* Clear flash wait state field */
  1735. fmr &= 0xfffff0ff;
  1736. /* set FWS (flash wait states) field in the FMR (flash mode register) */
  1737. fmr |= (pPrivate->flash_wait_states << 8);
  1738. LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
  1739. r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
  1740. if (r != ERROR_OK)
  1741. LOG_DEBUG("Error Write failed: set flash mode register");
  1742. /* 1st sector 8kBytes - page 0 - 15*/
  1743. /* 2nd sector 8kBytes - page 16 - 30*/
  1744. /* 3rd sector 48kBytes - page 31 - 127*/
  1745. LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
  1746. r = target_write_memory(pPrivate->pChip->target,
  1747. adr,
  1748. 4, /* THIS*MUST*BE* in 32bit values */
  1749. pPrivate->page_size / 4,
  1750. buf);
  1751. if (r != ERROR_OK) {
  1752. LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
  1753. (unsigned int)(adr));
  1754. return r;
  1755. }
  1756. r = EFC_PerformCommand(pPrivate,
  1757. /* send Erase & Write Page */
  1758. AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
  1759. pagenum,
  1760. &status);
  1761. if (r != ERROR_OK)
  1762. LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
  1763. (unsigned int)(adr));
  1764. if (status & (1 << 2)) {
  1765. LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
  1766. return ERROR_FAIL;
  1767. }
  1768. if (status & (1 << 1)) {
  1769. LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
  1770. return ERROR_FAIL;
  1771. }
  1772. return ERROR_OK;
  1773. }
  1774. static int sam4_write(struct flash_bank *bank,
  1775. uint8_t *buffer,
  1776. uint32_t offset,
  1777. uint32_t count)
  1778. {
  1779. int n;
  1780. unsigned page_cur;
  1781. unsigned page_end;
  1782. int r;
  1783. unsigned page_offset;
  1784. struct sam4_bank_private *pPrivate;
  1785. uint8_t *pagebuffer;
  1786. /* incase we bail further below, set this to null */
  1787. pagebuffer = NULL;
  1788. /* ignore dumb requests */
  1789. if (count == 0) {
  1790. r = ERROR_OK;
  1791. goto done;
  1792. }
  1793. if (bank->target->state != TARGET_HALTED) {
  1794. LOG_ERROR("Target not halted");
  1795. r = ERROR_TARGET_NOT_HALTED;
  1796. goto done;
  1797. }
  1798. pPrivate = get_sam4_bank_private(bank);
  1799. if (!(pPrivate->probed)) {
  1800. r = ERROR_FLASH_BANK_NOT_PROBED;
  1801. goto done;
  1802. }
  1803. if ((offset + count) > pPrivate->size_bytes) {
  1804. LOG_ERROR("Flash write error - past end of bank");
  1805. LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
  1806. (unsigned int)(offset),
  1807. (unsigned int)(count),
  1808. (unsigned int)(pPrivate->size_bytes));
  1809. r = ERROR_FAIL;
  1810. goto done;
  1811. }
  1812. pagebuffer = malloc(pPrivate->page_size);
  1813. if (!pagebuffer) {
  1814. LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
  1815. r = ERROR_FAIL;
  1816. goto done;
  1817. }
  1818. /* what page do we start & end in? */
  1819. page_cur = offset / pPrivate->page_size;
  1820. page_end = (offset + count - 1) / pPrivate->page_size;
  1821. LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
  1822. LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
  1823. /* Special case: all one page */
  1824. /* */
  1825. /* Otherwise: */
  1826. /* (1) non-aligned start */
  1827. /* (2) body pages */
  1828. /* (3) non-aligned end. */
  1829. /* Handle special case - all one page. */
  1830. if (page_cur == page_end) {
  1831. LOG_DEBUG("Special case, all in one page");
  1832. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1833. if (r != ERROR_OK)
  1834. goto done;
  1835. page_offset = (offset & (pPrivate->page_size-1));
  1836. memcpy(pagebuffer + page_offset,
  1837. buffer,
  1838. count);
  1839. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1840. if (r != ERROR_OK)
  1841. goto done;
  1842. r = ERROR_OK;
  1843. goto done;
  1844. }
  1845. /* non-aligned start */
  1846. page_offset = offset & (pPrivate->page_size - 1);
  1847. if (page_offset) {
  1848. LOG_DEBUG("Not-Aligned start");
  1849. /* read the partial */
  1850. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1851. if (r != ERROR_OK)
  1852. goto done;
  1853. /* over-write with new data */
  1854. n = (pPrivate->page_size - page_offset);
  1855. memcpy(pagebuffer + page_offset,
  1856. buffer,
  1857. n);
  1858. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1859. if (r != ERROR_OK)
  1860. goto done;
  1861. count -= n;
  1862. offset += n;
  1863. buffer += n;
  1864. page_cur++;
  1865. }
  1866. /* By checking that offset is correct here, we also
  1867. fix a clang warning */
  1868. assert(offset % pPrivate->page_size == 0);
  1869. /* intermediate large pages */
  1870. /* also - the final *terminal* */
  1871. /* if that terminal page is a full page */
  1872. LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
  1873. (int)page_cur, (int)page_end, (unsigned int)(count));
  1874. while ((page_cur < page_end) &&
  1875. (count >= pPrivate->page_size)) {
  1876. r = sam4_page_write(pPrivate, page_cur, buffer);
  1877. if (r != ERROR_OK)
  1878. goto done;
  1879. count -= pPrivate->page_size;
  1880. buffer += pPrivate->page_size;
  1881. page_cur += 1;
  1882. }
  1883. /* terminal partial page? */
  1884. if (count) {
  1885. LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
  1886. /* we have a partial page */
  1887. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1888. if (r != ERROR_OK)
  1889. goto done;
  1890. /* data goes at start */
  1891. memcpy(pagebuffer, buffer, count);
  1892. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1893. if (r != ERROR_OK)
  1894. goto done;
  1895. }
  1896. LOG_DEBUG("Done!");
  1897. r = ERROR_OK;
  1898. done:
  1899. if (pagebuffer)
  1900. free(pagebuffer);
  1901. return r;
  1902. }
  1903. COMMAND_HANDLER(sam4_handle_info_command)
  1904. {
  1905. struct sam4_chip *pChip;
  1906. pChip = get_current_sam4(CMD_CTX);
  1907. if (!pChip)
  1908. return ERROR_OK;
  1909. unsigned x;
  1910. int r;
  1911. /* bank0 must exist before we can do anything */
  1912. if (pChip->details.bank[0].pBank == NULL) {
  1913. x = 0;
  1914. need_define:
  1915. command_print(CMD_CTX,
  1916. "Please define bank %d via command: flash bank %s ... ",
  1917. x,
  1918. at91sam4_flash.name);
  1919. return ERROR_FAIL;
  1920. }
  1921. /* if bank 0 is not probed, then probe it */
  1922. if (!(pChip->details.bank[0].probed)) {
  1923. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  1924. if (r != ERROR_OK)
  1925. return ERROR_FAIL;
  1926. }
  1927. /* above guarantees the "chip details" structure is valid */
  1928. /* and thus, bank private areas are valid */
  1929. /* and we have a SAM4 chip, what a concept! */
  1930. /* auto-probe other banks, 0 done above */
  1931. for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
  1932. /* skip banks not present */
  1933. if (!(pChip->details.bank[x].present))
  1934. continue;
  1935. if (pChip->details.bank[x].pBank == NULL)
  1936. goto need_define;
  1937. if (pChip->details.bank[x].probed)
  1938. continue;
  1939. r = sam4_auto_probe(pChip->details.bank[x].pBank);
  1940. if (r != ERROR_OK)
  1941. return r;
  1942. }
  1943. r = sam4_GetInfo(pChip);
  1944. if (r != ERROR_OK) {
  1945. LOG_DEBUG("Sam4Info, Failed %d", r);
  1946. return r;
  1947. }
  1948. return ERROR_OK;
  1949. }
  1950. COMMAND_HANDLER(sam4_handle_gpnvm_command)
  1951. {
  1952. unsigned x, v;
  1953. int r, who;
  1954. struct sam4_chip *pChip;
  1955. pChip = get_current_sam4(CMD_CTX);
  1956. if (!pChip)
  1957. return ERROR_OK;
  1958. if (pChip->target->state != TARGET_HALTED) {
  1959. LOG_ERROR("sam4 - target not halted");
  1960. return ERROR_TARGET_NOT_HALTED;
  1961. }
  1962. if (pChip->details.bank[0].pBank == NULL) {
  1963. command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
  1964. at91sam4_flash.name);
  1965. return ERROR_FAIL;
  1966. }
  1967. if (!pChip->details.bank[0].probed) {
  1968. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  1969. if (r != ERROR_OK)
  1970. return r;
  1971. }
  1972. switch (CMD_ARGC) {
  1973. default:
  1974. return ERROR_COMMAND_SYNTAX_ERROR;
  1975. break;
  1976. case 0:
  1977. goto showall;
  1978. break;
  1979. case 1:
  1980. who = -1;
  1981. break;
  1982. case 2:
  1983. if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
  1984. who = -1;
  1985. else {
  1986. uint32_t v32;
  1987. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
  1988. who = v32;
  1989. }
  1990. break;
  1991. }
  1992. if (0 == strcmp("show", CMD_ARGV[0])) {
  1993. if (who == -1) {
  1994. showall:
  1995. r = ERROR_OK;
  1996. for (x = 0; x < pChip->details.n_gpnvms; x++) {
  1997. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
  1998. if (r != ERROR_OK)
  1999. break;
  2000. command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
  2001. }
  2002. return r;
  2003. }
  2004. if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
  2005. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
  2006. command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
  2007. return r;
  2008. } else {
  2009. command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
  2010. return ERROR_COMMAND_SYNTAX_ERROR;
  2011. }
  2012. }
  2013. if (who == -1) {
  2014. command_print(CMD_CTX, "Missing GPNVM number");
  2015. return ERROR_COMMAND_SYNTAX_ERROR;
  2016. }
  2017. if (0 == strcmp("set", CMD_ARGV[0]))
  2018. r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
  2019. else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
  2020. (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
  2021. r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
  2022. else {
  2023. command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
  2024. r = ERROR_COMMAND_SYNTAX_ERROR;
  2025. }
  2026. return r;
  2027. }
  2028. COMMAND_HANDLER(sam4_handle_slowclk_command)
  2029. {
  2030. struct sam4_chip *pChip;
  2031. pChip = get_current_sam4(CMD_CTX);
  2032. if (!pChip)
  2033. return ERROR_OK;
  2034. switch (CMD_ARGC) {
  2035. case 0:
  2036. /* show */
  2037. break;
  2038. case 1:
  2039. {
  2040. /* set */
  2041. uint32_t v;
  2042. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
  2043. if (v > 200000) {
  2044. /* absurd slow clock of 200Khz? */
  2045. command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
  2046. return ERROR_COMMAND_SYNTAX_ERROR;
  2047. }
  2048. pChip->cfg.slow_freq = v;
  2049. break;
  2050. }
  2051. default:
  2052. /* error */
  2053. command_print(CMD_CTX, "Too many parameters");
  2054. return ERROR_COMMAND_SYNTAX_ERROR;
  2055. break;
  2056. }
  2057. command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
  2058. (int)(pChip->cfg.slow_freq / 1000),
  2059. (int)(pChip->cfg.slow_freq % 1000));
  2060. return ERROR_OK;
  2061. }
  2062. static const struct command_registration at91sam4_exec_command_handlers[] = {
  2063. {
  2064. .name = "gpnvm",
  2065. .handler = sam4_handle_gpnvm_command,
  2066. .mode = COMMAND_EXEC,
  2067. .usage = "[('clr'|'set'|'show') bitnum]",
  2068. .help = "Without arguments, shows all bits in the gpnvm "
  2069. "register. Otherwise, clears, sets, or shows one "
  2070. "General Purpose Non-Volatile Memory (gpnvm) bit.",
  2071. },
  2072. {
  2073. .name = "info",
  2074. .handler = sam4_handle_info_command,
  2075. .mode = COMMAND_EXEC,
  2076. .help = "Print information about the current at91sam4 chip"
  2077. "and its flash configuration.",
  2078. },
  2079. {
  2080. .name = "slowclk",
  2081. .handler = sam4_handle_slowclk_command,
  2082. .mode = COMMAND_EXEC,
  2083. .usage = "[clock_hz]",
  2084. .help = "Display or set the slowclock frequency "
  2085. "(default 32768 Hz).",
  2086. },
  2087. COMMAND_REGISTRATION_DONE
  2088. };
  2089. static const struct command_registration at91sam4_command_handlers[] = {
  2090. {
  2091. .name = "at91sam4",
  2092. .mode = COMMAND_ANY,
  2093. .help = "at91sam4 flash command group",
  2094. .usage = "",
  2095. .chain = at91sam4_exec_command_handlers,
  2096. },
  2097. COMMAND_REGISTRATION_DONE
  2098. };
  2099. struct flash_driver at91sam4_flash = {
  2100. .name = "at91sam4",
  2101. .commands = at91sam4_command_handlers,
  2102. .flash_bank_command = sam4_flash_bank_command,
  2103. .erase = sam4_erase,
  2104. .protect = sam4_protect,
  2105. .write = sam4_write,
  2106. .read = default_flash_read,
  2107. .probe = sam4_probe,
  2108. .auto_probe = sam4_auto_probe,
  2109. .erase_check = default_flash_blank_check,
  2110. .protect_check = sam4_protect_check,
  2111. .info = sam4_info,
  2112. };