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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Gheorghe Guran (atlas) *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
  15. * GNU General public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ****************************************************************************/
  22. /***************************************************************************
  23. *
  24. * New flash setup command:
  25. *
  26. * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
  27. * [<chip_type> <banks>
  28. * <sectors_per_bank> <pages_per_sector>
  29. * <page_size> <num_nvmbits>
  30. * <ext_freq_khz>]
  31. *
  32. * <ext_freq_khz> - MUST be used if clock is from external source,
  33. * CAN be used if main oscillator frequency is known (recommended)
  34. * Examples:
  35. * ==== RECOMMENDED (covers clock speed) ============
  36. * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
  37. * (if auto-detect fails; provides clock spec)
  38. * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
  39. * (auto-detect everything except the clock)
  40. * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
  41. * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
  42. * (if auto-detect fails)
  43. * flash bank at91sam7 0 0 0 0 $_TARGETNAME
  44. * (old style, auto-detect everything)
  45. ****************************************************************************/
  46. #ifdef HAVE_CONFIG_H
  47. #include "config.h"
  48. #endif
  49. #include "imp.h"
  50. #include <helper/binarybuffer.h>
  51. /* AT91SAM7 control registers */
  52. #define DBGU_CIDR 0xFFFFF240
  53. #define CKGR_MCFR 0xFFFFFC24
  54. #define CKGR_MOR 0xFFFFFC20
  55. #define CKGR_MCFR_MAINRDY 0x10000
  56. #define CKGR_PLLR 0xFFFFFC2c
  57. #define CKGR_PLLR_DIV 0xff
  58. #define CKGR_PLLR_MUL 0x07ff0000
  59. #define PMC_MCKR 0xFFFFFC30
  60. #define PMC_MCKR_CSS 0x03
  61. #define PMC_MCKR_PRES 0x1c
  62. /* Flash Controller Commands */
  63. #define WP 0x01
  64. #define SLB 0x02
  65. #define WPL 0x03
  66. #define CLB 0x04
  67. #define EA 0x08
  68. #define SGPB 0x0B
  69. #define CGPB 0x0D
  70. #define SSB 0x0F
  71. /* MC_FSR bit definitions */
  72. #define MC_FSR_FRDY 1
  73. #define MC_FSR_EOL 2
  74. /* AT91SAM7 constants */
  75. #define RC_FREQ 32000
  76. /* Flash timing modes */
  77. #define FMR_TIMING_NONE 0
  78. #define FMR_TIMING_NVBITS 1
  79. #define FMR_TIMING_FLASH 2
  80. /* Flash size constants */
  81. #define FLASH_SIZE_8KB 1
  82. #define FLASH_SIZE_16KB 2
  83. #define FLASH_SIZE_32KB 3
  84. #define FLASH_SIZE_64KB 5
  85. #define FLASH_SIZE_128KB 7
  86. #define FLASH_SIZE_256KB 9
  87. #define FLASH_SIZE_512KB 10
  88. #define FLASH_SIZE_1024KB 12
  89. #define FLASH_SIZE_2048KB 14
  90. static int at91sam7_protect_check(struct flash_bank *bank);
  91. static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset,
  92. uint32_t count);
  93. static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
  94. static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
  95. static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
  96. static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
  97. static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
  98. static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
  99. static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
  100. static char *EPROC[8] = {
  101. "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
  102. };
  103. struct at91sam7_flash_bank {
  104. /* chip id register */
  105. uint32_t cidr;
  106. uint16_t cidr_ext;
  107. uint16_t cidr_nvptyp;
  108. uint16_t cidr_arch;
  109. uint16_t cidr_sramsiz;
  110. uint16_t cidr_nvpsiz;
  111. uint16_t cidr_nvpsiz2;
  112. uint16_t cidr_eproc;
  113. uint16_t cidr_version;
  114. const char *target_name;
  115. /* flash auto-detection */
  116. uint8_t flash_autodetection;
  117. /* flash geometry */
  118. uint16_t pages_per_sector;
  119. uint16_t pagesize;
  120. uint16_t pages_in_lockregion;
  121. /* nv memory bits */
  122. uint16_t num_lockbits_on;
  123. uint16_t lockbits;
  124. uint16_t num_nvmbits;
  125. uint16_t num_nvmbits_on;
  126. uint16_t nvmbits;
  127. uint8_t securitybit;
  128. /* 0: not init
  129. * 1: fmcn for nvbits (1uS)
  130. * 2: fmcn for flash (1.5uS) */
  131. uint8_t flashmode;
  132. /* main clock status */
  133. uint8_t mck_valid;
  134. uint32_t mck_freq;
  135. /* external clock frequency */
  136. uint32_t ext_freq;
  137. };
  138. #if 0
  139. static long SRAMSIZ[16] = {
  140. -1,
  141. 0x0400, /* 1K */
  142. 0x0800, /* 2K */
  143. -1,
  144. 0x1c000, /* 112K */
  145. 0x1000, /* 4K */
  146. 0x14000, /* 80K */
  147. 0x28000, /* 160K */
  148. 0x2000, /* 8K */
  149. 0x4000, /* 16K */
  150. 0x8000, /* 32K */
  151. 0x10000, /* 64K */
  152. 0x20000, /* 128K */
  153. 0x40000, /* 256K */
  154. 0x18000, /* 96K */
  155. 0x80000, /* 512K */
  156. };
  157. #endif
  158. static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
  159. {
  160. uint32_t fsr;
  161. target_read_u32(target, MC_FSR[bank_number], &fsr);
  162. return fsr;
  163. }
  164. /* Read clock configuration and set at91sam7_info->mck_freq */
  165. static void at91sam7_read_clock_info(struct flash_bank *bank)
  166. {
  167. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  168. struct target *target = bank->target;
  169. uint32_t mckr, mcfr, pllr, mor;
  170. unsigned long tmp = 0, mainfreq;
  171. /* Read Clock Generator Main Oscillator Register */
  172. target_read_u32(target, CKGR_MOR, &mor);
  173. /* Read Clock Generator Main Clock Frequency Register */
  174. target_read_u32(target, CKGR_MCFR, &mcfr);
  175. /* Read Master Clock Register*/
  176. target_read_u32(target, PMC_MCKR, &mckr);
  177. /* Read Clock Generator PLL Register */
  178. target_read_u32(target, CKGR_PLLR, &pllr);
  179. at91sam7_info->mck_valid = 0;
  180. at91sam7_info->mck_freq = 0;
  181. switch (mckr & PMC_MCKR_CSS) {
  182. case 0: /* Slow Clock */
  183. at91sam7_info->mck_valid = 1;
  184. tmp = RC_FREQ;
  185. break;
  186. case 1: /* Main Clock */
  187. if ((mcfr & CKGR_MCFR_MAINRDY) &&
  188. (at91sam7_info->ext_freq == 0)) {
  189. at91sam7_info->mck_valid = 1;
  190. tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
  191. } else if (at91sam7_info->ext_freq != 0) {
  192. at91sam7_info->mck_valid = 1;
  193. tmp = at91sam7_info->ext_freq;
  194. }
  195. break;
  196. case 2: /* Reserved */
  197. break;
  198. case 3: /* PLL Clock */
  199. if ((mcfr & CKGR_MCFR_MAINRDY) &&
  200. (at91sam7_info->ext_freq == 0)) {
  201. target_read_u32(target, CKGR_PLLR, &pllr);
  202. if (!(pllr & CKGR_PLLR_DIV))
  203. break; /* 0 Hz */
  204. at91sam7_info->mck_valid = 1;
  205. mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
  206. /* Integer arithmetic should have sufficient precision
  207. * as long as PLL is properly configured. */
  208. tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
  209. (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
  210. } else if ((at91sam7_info->ext_freq != 0) &&
  211. ((pllr&CKGR_PLLR_DIV) != 0)) {
  212. at91sam7_info->mck_valid = 1;
  213. tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
  214. (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
  215. }
  216. break;
  217. }
  218. /* Prescaler adjust */
  219. if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0)) {
  220. at91sam7_info->mck_valid = 0;
  221. at91sam7_info->mck_freq = 0;
  222. } else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
  223. at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
  224. else
  225. at91sam7_info->mck_freq = tmp;
  226. }
  227. /* Setup the timimg registers for nvbits or normal flash */
  228. static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
  229. {
  230. uint32_t fmr, fmcn = 0, fws = 0;
  231. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  232. struct target *target = bank->target;
  233. if (mode && (mode != at91sam7_info->flashmode)) {
  234. /* Always round up (ceil) */
  235. if (mode == FMR_TIMING_NVBITS) {
  236. if (at91sam7_info->cidr_arch == 0x60) {
  237. /* AT91SAM7A3 uses master clocks in 100 ns */
  238. fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
  239. } else {
  240. /* master clocks in 1uS for ARCH 0x7 types */
  241. fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
  242. }
  243. } else if (mode == FMR_TIMING_FLASH) {
  244. /* main clocks in 1.5uS */
  245. fmcn = (at91sam7_info->mck_freq/1000000ul)+
  246. (at91sam7_info->mck_freq/2000000ul) + 1;
  247. }
  248. /* hard overclocking */
  249. if (fmcn > 0xFF)
  250. fmcn = 0xFF;
  251. /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
  252. if (at91sam7_info->mck_freq <= 33333ul)
  253. fmcn = 0;
  254. /* Only allow fws = 0 if clock frequency is < 30 MHz. */
  255. if (at91sam7_info->mck_freq > 30000000ul)
  256. fws = 1;
  257. LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
  258. fmr = fmcn << 16 | fws << 8;
  259. target_write_u32(target, MC_FMR[bank->bank_number], fmr);
  260. }
  261. at91sam7_info->flashmode = mode;
  262. }
  263. static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
  264. {
  265. uint32_t status;
  266. while ((!((status = at91sam7_get_flash_status(bank->target,
  267. bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
  268. LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
  269. alive_sleep(1);
  270. }
  271. LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
  272. if (status & 0x0C) {
  273. LOG_ERROR("status register: 0x%" PRIx32 "", status);
  274. if (status & 0x4)
  275. LOG_ERROR("Lock Error Bit Detected, Operation Abort");
  276. if (status & 0x8)
  277. LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
  278. if (status & 0x10)
  279. LOG_ERROR("Security Bit Set, Operation Abort");
  280. }
  281. return status;
  282. }
  283. /* Send one command to the AT91SAM flash controller */
  284. static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen)
  285. {
  286. uint32_t fcr;
  287. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  288. struct target *target = bank->target;
  289. fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
  290. target_write_u32(target, MC_FCR[bank->bank_number], fcr);
  291. LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
  292. fcr,
  293. bank->bank_number + 1,
  294. pagen);
  295. if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB))) {
  296. /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
  297. if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
  298. return ERROR_FLASH_OPERATION_FAILED;
  299. return ERROR_OK;
  300. }
  301. if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
  302. return ERROR_FLASH_OPERATION_FAILED;
  303. return ERROR_OK;
  304. }
  305. /* Read device id register, main clock frequency register and fill in driver info structure */
  306. static int at91sam7_read_part_info(struct flash_bank *bank)
  307. {
  308. struct at91sam7_flash_bank *at91sam7_info;
  309. struct target *target = bank->target;
  310. uint16_t bnk, sec;
  311. uint16_t arch;
  312. uint32_t cidr;
  313. uint8_t banks_num = 0;
  314. uint16_t num_nvmbits = 0;
  315. uint16_t sectors_num = 0;
  316. uint16_t pages_per_sector = 0;
  317. uint16_t page_size = 0;
  318. uint32_t ext_freq;
  319. uint32_t bank_size;
  320. uint32_t base_address = 0;
  321. char *target_name_t = "Unknown";
  322. at91sam7_info = bank->driver_priv;
  323. if (at91sam7_info->cidr != 0) {
  324. /* flash already configured, update clock and check for protected sectors */
  325. struct flash_bank *fb = bank;
  326. struct flash_bank *t_bank = bank;
  327. while (t_bank) {
  328. /* re-calculate master clock frequency */
  329. at91sam7_read_clock_info(t_bank);
  330. /* no timming */
  331. at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
  332. /* check protect state */
  333. at91sam7_protect_check(t_bank);
  334. t_bank = fb->next;
  335. fb = t_bank;
  336. }
  337. return ERROR_OK;
  338. }
  339. /* Read and parse chip identification register */
  340. target_read_u32(target, DBGU_CIDR, &cidr);
  341. if (cidr == 0) {
  342. LOG_WARNING("Cannot identify target as an AT91SAM");
  343. return ERROR_FLASH_OPERATION_FAILED;
  344. }
  345. if (at91sam7_info->flash_autodetection == 0) {
  346. /* banks and sectors are already created, based on data from input file */
  347. struct flash_bank *fb = bank;
  348. struct flash_bank *t_bank = bank;
  349. while (t_bank) {
  350. at91sam7_info = t_bank->driver_priv;
  351. at91sam7_info->cidr = cidr;
  352. at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
  353. at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
  354. at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
  355. at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
  356. at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
  357. at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
  358. at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
  359. at91sam7_info->cidr_version = cidr&0x001F;
  360. /* calculate master clock frequency */
  361. at91sam7_read_clock_info(t_bank);
  362. /* no timming */
  363. at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
  364. /* check protect state */
  365. at91sam7_protect_check(t_bank);
  366. t_bank = fb->next;
  367. fb = t_bank;
  368. }
  369. return ERROR_OK;
  370. }
  371. arch = (cidr >> 20)&0x00FF;
  372. /* check flash size */
  373. switch ((cidr >> 8)&0x000F) {
  374. case FLASH_SIZE_8KB:
  375. break;
  376. case FLASH_SIZE_16KB:
  377. banks_num = 1;
  378. sectors_num = 8;
  379. pages_per_sector = 32;
  380. page_size = 64;
  381. base_address = 0x00100000;
  382. if (arch == 0x70) {
  383. num_nvmbits = 2;
  384. target_name_t = "AT91SAM7S161/16";
  385. }
  386. break;
  387. case FLASH_SIZE_32KB:
  388. banks_num = 1;
  389. sectors_num = 8;
  390. pages_per_sector = 32;
  391. page_size = 128;
  392. base_address = 0x00100000;
  393. if (arch == 0x70) {
  394. num_nvmbits = 2;
  395. target_name_t = "AT91SAM7S321/32";
  396. }
  397. if (arch == 0x72) {
  398. num_nvmbits = 3;
  399. target_name_t = "AT91SAM7SE32";
  400. }
  401. break;
  402. case FLASH_SIZE_64KB:
  403. banks_num = 1;
  404. sectors_num = 16;
  405. pages_per_sector = 32;
  406. page_size = 128;
  407. base_address = 0x00100000;
  408. if (arch == 0x70) {
  409. num_nvmbits = 2;
  410. target_name_t = "AT91SAM7S64";
  411. }
  412. break;
  413. case FLASH_SIZE_128KB:
  414. banks_num = 1;
  415. sectors_num = 8;
  416. pages_per_sector = 64;
  417. page_size = 256;
  418. base_address = 0x00100000;
  419. if (arch == 0x70) {
  420. num_nvmbits = 2;
  421. target_name_t = "AT91SAM7S128";
  422. }
  423. if (arch == 0x71) {
  424. num_nvmbits = 3;
  425. target_name_t = "AT91SAM7XC128";
  426. }
  427. if (arch == 0x72) {
  428. num_nvmbits = 3;
  429. target_name_t = "AT91SAM7SE128";
  430. }
  431. if (arch == 0x75) {
  432. num_nvmbits = 3;
  433. target_name_t = "AT91SAM7X128";
  434. }
  435. break;
  436. case FLASH_SIZE_256KB:
  437. banks_num = 1;
  438. sectors_num = 16;
  439. pages_per_sector = 64;
  440. page_size = 256;
  441. base_address = 0x00100000;
  442. if (arch == 0x60) {
  443. num_nvmbits = 3;
  444. target_name_t = "AT91SAM7A3";
  445. }
  446. if (arch == 0x70) {
  447. num_nvmbits = 2;
  448. target_name_t = "AT91SAM7S256";
  449. }
  450. if (arch == 0x71) {
  451. num_nvmbits = 3;
  452. target_name_t = "AT91SAM7XC256";
  453. }
  454. if (arch == 0x72) {
  455. num_nvmbits = 3;
  456. target_name_t = "AT91SAM7SE256";
  457. }
  458. if (arch == 0x75) {
  459. num_nvmbits = 3;
  460. target_name_t = "AT91SAM7X256";
  461. }
  462. break;
  463. case FLASH_SIZE_512KB:
  464. banks_num = 2;
  465. sectors_num = 16;
  466. pages_per_sector = 64;
  467. page_size = 256;
  468. base_address = 0x00100000;
  469. if (arch == 0x70) {
  470. num_nvmbits = 2;
  471. target_name_t = "AT91SAM7S512";
  472. }
  473. if (arch == 0x71) {
  474. num_nvmbits = 3;
  475. target_name_t = "AT91SAM7XC512";
  476. }
  477. if (arch == 0x72) {
  478. num_nvmbits = 3;
  479. target_name_t = "AT91SAM7SE512";
  480. }
  481. if (arch == 0x75) {
  482. num_nvmbits = 3;
  483. target_name_t = "AT91SAM7X512";
  484. }
  485. break;
  486. case FLASH_SIZE_1024KB:
  487. break;
  488. case FLASH_SIZE_2048KB:
  489. break;
  490. }
  491. if (strcmp(target_name_t, "Unknown") == 0) {
  492. LOG_ERROR(
  493. "Target autodetection failed! Please specify target parameters in configuration file");
  494. return ERROR_FLASH_OPERATION_FAILED;
  495. }
  496. ext_freq = at91sam7_info->ext_freq;
  497. /* calculate bank size */
  498. bank_size = sectors_num * pages_per_sector * page_size;
  499. for (bnk = 0; bnk < banks_num; bnk++) {
  500. struct flash_bank *t_bank = bank;
  501. if (bnk > 0) {
  502. if (!t_bank->next) {
  503. /* create a new flash bank element */
  504. struct flash_bank *fb = malloc(sizeof(struct flash_bank));
  505. fb->target = target;
  506. fb->driver = bank->driver;
  507. fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
  508. fb->name = "sam7_probed";
  509. fb->next = NULL;
  510. /* link created bank in 'flash_banks' list */
  511. t_bank->next = fb;
  512. }
  513. t_bank = t_bank->next;
  514. }
  515. t_bank->bank_number = bnk;
  516. t_bank->base = base_address + bnk * bank_size;
  517. t_bank->size = bank_size;
  518. t_bank->chip_width = 0;
  519. t_bank->bus_width = 4;
  520. t_bank->num_sectors = sectors_num;
  521. /* allocate sectors */
  522. t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
  523. for (sec = 0; sec < sectors_num; sec++) {
  524. t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
  525. t_bank->sectors[sec].size = pages_per_sector * page_size;
  526. t_bank->sectors[sec].is_erased = -1;
  527. t_bank->sectors[sec].is_protected = -1;
  528. }
  529. at91sam7_info = t_bank->driver_priv;
  530. at91sam7_info->cidr = cidr;
  531. at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
  532. at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
  533. at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
  534. at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
  535. at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
  536. at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
  537. at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
  538. at91sam7_info->cidr_version = cidr&0x001F;
  539. at91sam7_info->target_name = target_name_t;
  540. at91sam7_info->flashmode = 0;
  541. at91sam7_info->ext_freq = ext_freq;
  542. at91sam7_info->num_nvmbits = num_nvmbits;
  543. at91sam7_info->num_nvmbits_on = 0;
  544. at91sam7_info->pagesize = page_size;
  545. at91sam7_info->pages_per_sector = pages_per_sector;
  546. /* calculate master clock frequency */
  547. at91sam7_read_clock_info(t_bank);
  548. /* no timming */
  549. at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
  550. /* check protect state */
  551. at91sam7_protect_check(t_bank);
  552. }
  553. LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
  554. at91sam7_info->cidr_nvptyp,
  555. at91sam7_info->cidr_arch);
  556. return ERROR_OK;
  557. }
  558. static int at91sam7_erase_check(struct flash_bank *bank)
  559. {
  560. struct target *target = bank->target;
  561. uint16_t retval;
  562. uint32_t blank;
  563. uint16_t fast_check;
  564. uint8_t *buffer;
  565. uint16_t nSector;
  566. uint16_t nByte;
  567. if (bank->target->state != TARGET_HALTED) {
  568. LOG_ERROR("Target not halted");
  569. return ERROR_TARGET_NOT_HALTED;
  570. }
  571. /* Configure the flash controller timing */
  572. at91sam7_read_clock_info(bank);
  573. at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
  574. fast_check = 1;
  575. for (nSector = 0; nSector < bank->num_sectors; nSector++) {
  576. retval = target_blank_check_memory(target,
  577. bank->base + bank->sectors[nSector].offset,
  578. bank->sectors[nSector].size,
  579. &blank);
  580. if (retval != ERROR_OK) {
  581. fast_check = 0;
  582. break;
  583. }
  584. if (blank == 0xFF)
  585. bank->sectors[nSector].is_erased = 1;
  586. else
  587. bank->sectors[nSector].is_erased = 0;
  588. }
  589. if (fast_check)
  590. return ERROR_OK;
  591. LOG_USER("Running slow fallback erase check - add working memory");
  592. buffer = malloc(bank->sectors[0].size);
  593. for (nSector = 0; nSector < bank->num_sectors; nSector++) {
  594. bank->sectors[nSector].is_erased = 1;
  595. retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
  596. bank->sectors[nSector].size/4, buffer);
  597. if (retval != ERROR_OK)
  598. return retval;
  599. for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++) {
  600. if (buffer[nByte] != 0xFF) {
  601. bank->sectors[nSector].is_erased = 0;
  602. break;
  603. }
  604. }
  605. }
  606. free(buffer);
  607. return ERROR_OK;
  608. }
  609. static int at91sam7_protect_check(struct flash_bank *bank)
  610. {
  611. uint8_t lock_pos, gpnvm_pos;
  612. uint32_t status;
  613. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  614. if (at91sam7_info->cidr == 0)
  615. return ERROR_FLASH_BANK_NOT_PROBED;
  616. if (bank->target->state != TARGET_HALTED) {
  617. LOG_ERROR("Target not halted");
  618. return ERROR_TARGET_NOT_HALTED;
  619. }
  620. status = at91sam7_get_flash_status(bank->target, bank->bank_number);
  621. at91sam7_info->lockbits = (status >> 16);
  622. at91sam7_info->num_lockbits_on = 0;
  623. for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++) {
  624. if (((status >> (16 + lock_pos))&(0x0001)) == 1) {
  625. at91sam7_info->num_lockbits_on++;
  626. bank->sectors[lock_pos].is_protected = 1;
  627. } else
  628. bank->sectors[lock_pos].is_protected = 0;
  629. }
  630. /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
  631. status = at91sam7_get_flash_status(bank->target, 0);
  632. at91sam7_info->securitybit = (status >> 4)&0x01;
  633. at91sam7_info->nvmbits = (status >> 8)&0xFF;
  634. at91sam7_info->num_nvmbits_on = 0;
  635. for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++) {
  636. if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
  637. at91sam7_info->num_nvmbits_on++;
  638. }
  639. return ERROR_OK;
  640. }
  641. FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
  642. {
  643. struct flash_bank *t_bank = bank;
  644. struct at91sam7_flash_bank *at91sam7_info;
  645. struct target *target = t_bank->target;
  646. uint32_t base_address;
  647. uint32_t bank_size;
  648. uint32_t ext_freq = 0;
  649. int chip_width;
  650. int bus_width;
  651. int banks_num;
  652. int num_sectors;
  653. uint16_t pages_per_sector;
  654. uint16_t page_size;
  655. uint16_t num_nvmbits;
  656. char *target_name_t;
  657. int bnk, sec;
  658. at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
  659. t_bank->driver_priv = at91sam7_info;
  660. /* part wasn't probed for info yet */
  661. at91sam7_info->cidr = 0;
  662. at91sam7_info->flashmode = 0;
  663. at91sam7_info->ext_freq = 0;
  664. at91sam7_info->flash_autodetection = 0;
  665. if (CMD_ARGC < 13) {
  666. at91sam7_info->flash_autodetection = 1;
  667. return ERROR_OK;
  668. }
  669. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
  670. COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], chip_width);
  671. COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], bus_width);
  672. COMMAND_PARSE_NUMBER(int, CMD_ARGV[8], banks_num);
  673. COMMAND_PARSE_NUMBER(int, CMD_ARGV[9], num_sectors);
  674. COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
  675. COMMAND_PARSE_NUMBER(u16, CMD_ARGV[11], page_size);
  676. COMMAND_PARSE_NUMBER(u16, CMD_ARGV[12], num_nvmbits);
  677. if (CMD_ARGC == 14) {
  678. unsigned long freq;
  679. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[13], freq);
  680. ext_freq = freq * 1000;
  681. at91sam7_info->ext_freq = ext_freq;
  682. }
  683. if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) ||
  684. (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0)) {
  685. at91sam7_info->flash_autodetection = 1;
  686. return ERROR_OK;
  687. }
  688. target_name_t = calloc(strlen(CMD_ARGV[7]) + 1, sizeof(char));
  689. strcpy(target_name_t, CMD_ARGV[7]);
  690. /* calculate bank size */
  691. bank_size = num_sectors * pages_per_sector * page_size;
  692. for (bnk = 0; bnk < banks_num; bnk++) {
  693. if (bnk > 0) {
  694. if (!t_bank->next) {
  695. /* create a new bank element */
  696. struct flash_bank *fb = malloc(sizeof(struct flash_bank));
  697. fb->target = target;
  698. fb->driver = bank->driver;
  699. fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
  700. fb->name = "sam7_probed";
  701. fb->next = NULL;
  702. /* link created bank in 'flash_banks' list */
  703. t_bank->next = fb;
  704. }
  705. t_bank = t_bank->next;
  706. }
  707. t_bank->bank_number = bnk;
  708. t_bank->base = base_address + bnk * bank_size;
  709. t_bank->size = bank_size;
  710. t_bank->chip_width = chip_width;
  711. t_bank->bus_width = bus_width;
  712. t_bank->num_sectors = num_sectors;
  713. /* allocate sectors */
  714. t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
  715. for (sec = 0; sec < num_sectors; sec++) {
  716. t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
  717. t_bank->sectors[sec].size = pages_per_sector * page_size;
  718. t_bank->sectors[sec].is_erased = -1;
  719. t_bank->sectors[sec].is_protected = -1;
  720. }
  721. at91sam7_info = t_bank->driver_priv;
  722. at91sam7_info->target_name = target_name_t;
  723. at91sam7_info->flashmode = 0;
  724. at91sam7_info->ext_freq = ext_freq;
  725. at91sam7_info->num_nvmbits = num_nvmbits;
  726. at91sam7_info->num_nvmbits_on = 0;
  727. at91sam7_info->pagesize = page_size;
  728. at91sam7_info->pages_per_sector = pages_per_sector;
  729. }
  730. return ERROR_OK;
  731. }
  732. static int at91sam7_erase(struct flash_bank *bank, int first, int last)
  733. {
  734. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  735. int sec;
  736. uint32_t nbytes, pos;
  737. uint8_t *buffer;
  738. uint8_t erase_all;
  739. if (at91sam7_info->cidr == 0)
  740. return ERROR_FLASH_BANK_NOT_PROBED;
  741. if (bank->target->state != TARGET_HALTED) {
  742. LOG_ERROR("Target not halted");
  743. return ERROR_TARGET_NOT_HALTED;
  744. }
  745. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  746. return ERROR_FLASH_SECTOR_INVALID;
  747. erase_all = 0;
  748. if ((first == 0) && (last == (bank->num_sectors-1)))
  749. erase_all = 1;
  750. /* Configure the flash controller timing */
  751. at91sam7_read_clock_info(bank);
  752. at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
  753. if (erase_all) {
  754. if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
  755. return ERROR_FLASH_OPERATION_FAILED;
  756. } else {
  757. /* allocate and clean buffer */
  758. nbytes = (last - first + 1) * bank->sectors[first].size;
  759. buffer = malloc(nbytes * sizeof(uint8_t));
  760. for (pos = 0; pos < nbytes; pos++)
  761. buffer[pos] = 0xFF;
  762. if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK) {
  763. free(buffer);
  764. return ERROR_FLASH_OPERATION_FAILED;
  765. }
  766. free(buffer);
  767. }
  768. /* mark erased sectors */
  769. for (sec = first; sec <= last; sec++)
  770. bank->sectors[sec].is_erased = 1;
  771. return ERROR_OK;
  772. }
  773. static int at91sam7_protect(struct flash_bank *bank, int set, int first, int last)
  774. {
  775. uint32_t cmd;
  776. int sector;
  777. uint32_t pagen;
  778. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  779. if (at91sam7_info->cidr == 0)
  780. return ERROR_FLASH_BANK_NOT_PROBED;
  781. if (bank->target->state != TARGET_HALTED) {
  782. LOG_ERROR("Target not halted");
  783. return ERROR_TARGET_NOT_HALTED;
  784. }
  785. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  786. return ERROR_FLASH_SECTOR_INVALID;
  787. /* Configure the flash controller timing */
  788. at91sam7_read_clock_info(bank);
  789. at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
  790. for (sector = first; sector <= last; sector++) {
  791. if (set)
  792. cmd = SLB;
  793. else
  794. cmd = CLB;
  795. /* if we lock a page from one sector then entire sector will be locked, also,
  796. * if we unlock a page from a locked sector, entire sector will be unlocked */
  797. pagen = sector * at91sam7_info->pages_per_sector;
  798. if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
  799. return ERROR_FLASH_OPERATION_FAILED;
  800. }
  801. at91sam7_protect_check(bank);
  802. return ERROR_OK;
  803. }
  804. static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  805. {
  806. int retval;
  807. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  808. struct target *target = bank->target;
  809. uint32_t dst_min_alignment, wcount, bytes_remaining = count;
  810. uint32_t first_page, last_page, pagen, buffer_pos;
  811. if (at91sam7_info->cidr == 0)
  812. return ERROR_FLASH_BANK_NOT_PROBED;
  813. if (bank->target->state != TARGET_HALTED) {
  814. LOG_ERROR("Target not halted");
  815. return ERROR_TARGET_NOT_HALTED;
  816. }
  817. if (offset + count > bank->size)
  818. return ERROR_FLASH_DST_OUT_OF_BANK;
  819. dst_min_alignment = at91sam7_info->pagesize;
  820. if (offset % dst_min_alignment) {
  821. LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
  822. offset,
  823. dst_min_alignment);
  824. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  825. }
  826. if (at91sam7_info->cidr_arch == 0)
  827. return ERROR_FLASH_BANK_NOT_PROBED;
  828. first_page = offset/dst_min_alignment;
  829. last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
  830. LOG_DEBUG("first_page: %i, last_page: %i, count %i",
  831. (int)first_page,
  832. (int)last_page,
  833. (int)count);
  834. /* Configure the flash controller timing */
  835. at91sam7_read_clock_info(bank);
  836. at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
  837. for (pagen = first_page; pagen < last_page; pagen++) {
  838. if (bytes_remaining < dst_min_alignment)
  839. count = bytes_remaining;
  840. else
  841. count = dst_min_alignment;
  842. bytes_remaining -= count;
  843. /* Write one block to the PageWriteBuffer */
  844. buffer_pos = (pagen-first_page)*dst_min_alignment;
  845. wcount = DIV_ROUND_UP(count, 4);
  846. retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4,
  847. wcount, buffer + buffer_pos);
  848. if (retval != ERROR_OK)
  849. return retval;
  850. /* Send Write Page command to Flash Controller */
  851. if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
  852. return ERROR_FLASH_OPERATION_FAILED;
  853. LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
  854. }
  855. return ERROR_OK;
  856. }
  857. static int at91sam7_probe(struct flash_bank *bank)
  858. {
  859. /* we can't probe on an at91sam7
  860. * if this is an at91sam7, it has the configured flash */
  861. int retval;
  862. if (bank->target->state != TARGET_HALTED) {
  863. LOG_ERROR("Target not halted");
  864. return ERROR_TARGET_NOT_HALTED;
  865. }
  866. retval = at91sam7_read_part_info(bank);
  867. if (retval != ERROR_OK)
  868. return retval;
  869. return ERROR_OK;
  870. }
  871. static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
  872. {
  873. int printed;
  874. struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
  875. if (at91sam7_info->cidr == 0)
  876. return ERROR_FLASH_BANK_NOT_PROBED;
  877. printed = snprintf(buf, buf_size,
  878. "\n at91sam7 driver information: Chip is %s\n",
  879. at91sam7_info->target_name);
  880. buf += printed;
  881. buf_size -= printed;
  882. printed = snprintf(buf,
  883. buf_size,
  884. " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
  885. "Flashsize: 0x%8.8" PRIx32 "\n",
  886. at91sam7_info->cidr,
  887. at91sam7_info->cidr_arch,
  888. EPROC[at91sam7_info->cidr_eproc],
  889. at91sam7_info->cidr_version,
  890. bank->size);
  891. buf += printed;
  892. buf_size -= printed;
  893. printed = snprintf(buf, buf_size,
  894. " Master clock (estimated): %u KHz | External clock: %u KHz\n",
  895. (unsigned)(at91sam7_info->mck_freq / 1000),
  896. (unsigned)(at91sam7_info->ext_freq / 1000));
  897. buf += printed;
  898. buf_size -= printed;
  899. printed = snprintf(buf,
  900. buf_size,
  901. " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i\n",
  902. at91sam7_info->pagesize,
  903. bank->num_sectors,
  904. at91sam7_info->num_lockbits_on,
  905. at91sam7_info->lockbits,
  906. at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
  907. buf += printed;
  908. buf_size -= printed;
  909. snprintf(buf, buf_size,
  910. " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
  911. at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
  912. at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
  913. return ERROR_OK;
  914. }
  915. /*
  916. * On AT91SAM7S: When the gpnvm bits are set with
  917. * > at91sam7 gpnvm bitnr set
  918. * the changes are not visible in the flash controller status register MC_FSR
  919. * until the processor has been reset.
  920. * On the Olimex board this requires a power cycle.
  921. * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
  922. * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
  923. * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
  924. */
  925. COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
  926. {
  927. struct flash_bank *bank;
  928. int bit;
  929. uint8_t flashcmd;
  930. uint32_t status;
  931. struct at91sam7_flash_bank *at91sam7_info;
  932. int retval;
  933. if (CMD_ARGC != 2)
  934. return ERROR_COMMAND_SYNTAX_ERROR;
  935. bank = get_flash_bank_by_num_noprobe(0);
  936. if (bank == NULL)
  937. return ERROR_FLASH_BANK_INVALID;
  938. if (strcmp(bank->driver->name, "at91sam7")) {
  939. command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
  940. return ERROR_FLASH_BANK_INVALID;
  941. }
  942. if (bank->target->state != TARGET_HALTED) {
  943. LOG_ERROR("target has to be halted to perform flash operation");
  944. return ERROR_TARGET_NOT_HALTED;
  945. }
  946. if (strcmp(CMD_ARGV[1], "set") == 0)
  947. flashcmd = SGPB;
  948. else if (strcmp(CMD_ARGV[1], "clear") == 0)
  949. flashcmd = CGPB;
  950. else
  951. return ERROR_COMMAND_SYNTAX_ERROR;
  952. at91sam7_info = bank->driver_priv;
  953. if (at91sam7_info->cidr == 0) {
  954. retval = at91sam7_read_part_info(bank);
  955. if (retval != ERROR_OK)
  956. return retval;
  957. }
  958. COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], bit);
  959. if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits)) {
  960. command_print(CMD_CTX,
  961. "gpnvm bit '#%s' is out of bounds for target %s",
  962. CMD_ARGV[0],
  963. at91sam7_info->target_name);
  964. return ERROR_OK;
  965. }
  966. /* Configure the flash controller timing */
  967. at91sam7_read_clock_info(bank);
  968. at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
  969. if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
  970. return ERROR_FLASH_OPERATION_FAILED;
  971. /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
  972. status = at91sam7_get_flash_status(bank->target, 0);
  973. LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
  974. flashcmd,
  975. bit,
  976. status);
  977. /* check protect state */
  978. at91sam7_protect_check(bank);
  979. return ERROR_OK;
  980. }
  981. static const struct command_registration at91sam7_exec_command_handlers[] = {
  982. {
  983. .name = "gpnvm",
  984. .handler = at91sam7_handle_gpnvm_command,
  985. .mode = COMMAND_EXEC,
  986. .help = "set or clear one General Purpose Non-Volatile Memory "
  987. "(gpnvm) bit",
  988. .usage = "bitnum ('set'|'clear')",
  989. },
  990. COMMAND_REGISTRATION_DONE
  991. };
  992. static const struct command_registration at91sam7_command_handlers[] = {
  993. {
  994. .name = "at91sam7",
  995. .mode = COMMAND_ANY,
  996. .help = "at91sam7 flash command group",
  997. .usage = "",
  998. .chain = at91sam7_exec_command_handlers,
  999. },
  1000. COMMAND_REGISTRATION_DONE
  1001. };
  1002. struct flash_driver at91sam7_flash = {
  1003. .name = "at91sam7",
  1004. .usage = "gpnvm <bit> <set | clear>",
  1005. .commands = at91sam7_command_handlers,
  1006. .flash_bank_command = at91sam7_flash_bank_command,
  1007. .erase = at91sam7_erase,
  1008. .protect = at91sam7_protect,
  1009. .write = at91sam7_write,
  1010. .read = default_flash_read,
  1011. .probe = at91sam7_probe,
  1012. .auto_probe = at91sam7_probe,
  1013. .erase_check = at91sam7_erase_check,
  1014. .protect_check = at91sam7_protect_check,
  1015. .info = get_at91sam7_info,
  1016. };