You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

3053 lines
94KB

  1. /***************************************************************************
  2. * Copyright (C) 2005, 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * Copyright (C) 2009 Michael Schwingen *
  5. * michael@schwingen.org *
  6. * Copyright (C) 2010 √ėyvind Harboe <oyvind.harboe@zylin.com> *
  7. * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "imp.h"
  28. #include "cfi.h"
  29. #include "non_cfi.h"
  30. #include <target/arm.h>
  31. #include <target/arm7_9_common.h>
  32. #include <target/armv7m.h>
  33. #include <target/mips32.h>
  34. #include <helper/binarybuffer.h>
  35. #include <target/algorithm.h>
  36. #define CFI_MAX_BUS_WIDTH 4
  37. #define CFI_MAX_CHIP_WIDTH 4
  38. /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  39. #define CFI_MAX_INTEL_CODESIZE 256
  40. /* some id-types with specific handling */
  41. #define AT49BV6416 0x00d6
  42. #define AT49BV6416T 0x00d2
  43. static struct cfi_unlock_addresses cfi_unlock_addresses[] = {
  44. [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  45. [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  46. };
  47. /* CFI fixups forward declarations */
  48. static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param);
  49. static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param);
  50. static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param);
  51. static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param);
  52. /* fixup after reading cmdset 0002 primary query table */
  53. static const struct cfi_fixup cfi_0002_fixups[] = {
  54. {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses,
  55. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56. {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses,
  57. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58. {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses,
  59. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  60. {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses,
  61. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  62. {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses,
  63. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  64. {CFI_MFR_SST, 0x274b, cfi_fixup_0002_unlock_addresses,
  65. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  66. {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses,
  67. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  68. {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
  69. {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
  70. {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses,
  71. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  72. {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses,
  73. &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  74. {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses,
  75. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  76. {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses,
  77. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  78. {CFI_MFR_EON, 0x225b, cfi_fixup_0002_unlock_addresses,
  79. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  80. {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses,
  81. &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  82. {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  83. {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL},/* M29W128G */
  84. {0, 0, NULL, NULL}
  85. };
  86. /* fixup after reading cmdset 0001 primary query table */
  87. static const struct cfi_fixup cfi_0001_fixups[] = {
  88. {0, 0, NULL, NULL}
  89. };
  90. static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  91. {
  92. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  93. const struct cfi_fixup *f;
  94. for (f = fixups; f->fixup; f++) {
  95. if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  96. ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
  97. f->fixup(bank, f->param);
  98. }
  99. }
  100. static inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  101. {
  102. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  103. if (cfi_info->x16_as_x8)
  104. offset *= 2;
  105. /* while the sector list isn't built, only accesses to sector 0 work */
  106. if (sector == 0)
  107. return bank->base + offset * bank->bus_width;
  108. else {
  109. if (!bank->sectors) {
  110. LOG_ERROR("BUG: sector list not yet built");
  111. exit(-1);
  112. }
  113. return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
  114. }
  115. }
  116. static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
  117. {
  118. int i;
  119. /* clear whole buffer, to ensure bits that exceed the bus_width
  120. * are set to zero
  121. */
  122. for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
  123. cmd_buf[i] = 0;
  124. if (bank->target->endianness == TARGET_LITTLE_ENDIAN) {
  125. for (i = bank->bus_width; i > 0; i--)
  126. *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
  127. } else {
  128. for (i = 1; i <= bank->bus_width; i++)
  129. *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
  130. }
  131. }
  132. static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
  133. {
  134. uint8_t command[CFI_MAX_BUS_WIDTH];
  135. cfi_command(bank, cmd, command);
  136. return target_write_memory(bank->target, address, bank->bus_width, 1, command);
  137. }
  138. /* read unsigned 8-bit value from the bank
  139. * flash banks are expected to be made of similar chips
  140. * the query result should be the same for all
  141. */
  142. static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
  143. {
  144. struct target *target = bank->target;
  145. uint8_t data[CFI_MAX_BUS_WIDTH];
  146. int retval;
  147. retval = target_read_memory(target, flash_address(bank, sector, offset),
  148. bank->bus_width, 1, data);
  149. if (retval != ERROR_OK)
  150. return retval;
  151. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  152. *val = data[0];
  153. else
  154. *val = data[bank->bus_width - 1];
  155. return ERROR_OK;
  156. }
  157. /* read unsigned 8-bit value from the bank
  158. * in case of a bank made of multiple chips,
  159. * the individual values are ORed
  160. */
  161. static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
  162. {
  163. struct target *target = bank->target;
  164. uint8_t data[CFI_MAX_BUS_WIDTH];
  165. int i;
  166. int retval;
  167. retval = target_read_memory(target, flash_address(bank, sector, offset),
  168. bank->bus_width, 1, data);
  169. if (retval != ERROR_OK)
  170. return retval;
  171. if (bank->target->endianness == TARGET_LITTLE_ENDIAN) {
  172. for (i = 0; i < bank->bus_width / bank->chip_width; i++)
  173. data[0] |= data[i];
  174. *val = data[0];
  175. } else {
  176. uint8_t value = 0;
  177. for (i = 0; i < bank->bus_width / bank->chip_width; i++)
  178. value |= data[bank->bus_width - 1 - i];
  179. *val = value;
  180. }
  181. return ERROR_OK;
  182. }
  183. static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
  184. {
  185. struct target *target = bank->target;
  186. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  187. uint8_t data[CFI_MAX_BUS_WIDTH * 2];
  188. int retval;
  189. if (cfi_info->x16_as_x8) {
  190. uint8_t i;
  191. for (i = 0; i < 2; i++) {
  192. retval = target_read_memory(target, flash_address(bank, sector, offset + i),
  193. bank->bus_width, 1, &data[i * bank->bus_width]);
  194. if (retval != ERROR_OK)
  195. return retval;
  196. }
  197. } else {
  198. retval = target_read_memory(target, flash_address(bank, sector, offset),
  199. bank->bus_width, 2, data);
  200. if (retval != ERROR_OK)
  201. return retval;
  202. }
  203. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  204. *val = data[0] | data[bank->bus_width] << 8;
  205. else
  206. *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
  207. return ERROR_OK;
  208. }
  209. static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
  210. {
  211. struct target *target = bank->target;
  212. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  213. uint8_t data[CFI_MAX_BUS_WIDTH * 4];
  214. int retval;
  215. if (cfi_info->x16_as_x8) {
  216. uint8_t i;
  217. for (i = 0; i < 4; i++) {
  218. retval = target_read_memory(target, flash_address(bank, sector, offset + i),
  219. bank->bus_width, 1, &data[i * bank->bus_width]);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. }
  223. } else {
  224. retval = target_read_memory(target, flash_address(bank, sector, offset),
  225. bank->bus_width, 4, data);
  226. if (retval != ERROR_OK)
  227. return retval;
  228. }
  229. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  230. *val = data[0] | data[bank->bus_width] << 8 |
  231. data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
  232. else
  233. *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8 |
  234. data[(3 * bank->bus_width) - 1] << 16 |
  235. data[(4 * bank->bus_width) - 1] << 24;
  236. return ERROR_OK;
  237. }
  238. static int cfi_reset(struct flash_bank *bank)
  239. {
  240. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  241. int retval = ERROR_OK;
  242. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  243. if (retval != ERROR_OK)
  244. return retval;
  245. retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  246. if (retval != ERROR_OK)
  247. return retval;
  248. if (cfi_info->manufacturer == 0x20 &&
  249. (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E)) {
  250. /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
  251. * so we send an extra 0xF0 reset to fix the bug */
  252. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00));
  253. if (retval != ERROR_OK)
  254. return retval;
  255. }
  256. return retval;
  257. }
  258. static void cfi_intel_clear_status_register(struct flash_bank *bank)
  259. {
  260. cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
  261. }
  262. static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
  263. {
  264. uint8_t status;
  265. int retval = ERROR_OK;
  266. for (;; ) {
  267. if (timeout-- < 0) {
  268. LOG_ERROR("timeout while waiting for WSM to become ready");
  269. return ERROR_FAIL;
  270. }
  271. retval = cfi_get_u8(bank, 0, 0x0, &status);
  272. if (retval != ERROR_OK)
  273. return retval;
  274. if (status & 0x80)
  275. break;
  276. alive_sleep(1);
  277. }
  278. /* mask out bit 0 (reserved) */
  279. status = status & 0xfe;
  280. LOG_DEBUG("status: 0x%x", status);
  281. if (status != 0x80) {
  282. LOG_ERROR("status register: 0x%x", status);
  283. if (status & 0x2)
  284. LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
  285. if (status & 0x4)
  286. LOG_ERROR("Program suspended");
  287. if (status & 0x8)
  288. LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
  289. if (status & 0x10)
  290. LOG_ERROR("Program Error / Error in Setting Lock-Bit");
  291. if (status & 0x20)
  292. LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
  293. if (status & 0x40)
  294. LOG_ERROR("Block Erase Suspended");
  295. cfi_intel_clear_status_register(bank);
  296. retval = ERROR_FAIL;
  297. }
  298. *val = status;
  299. return retval;
  300. }
  301. static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
  302. {
  303. uint8_t status, oldstatus;
  304. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  305. int retval;
  306. retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
  307. if (retval != ERROR_OK)
  308. return retval;
  309. do {
  310. retval = cfi_get_u8(bank, 0, 0x0, &status);
  311. if (retval != ERROR_OK)
  312. return retval;
  313. if ((status ^ oldstatus) & 0x40) {
  314. if (status & cfi_info->status_poll_mask & 0x20) {
  315. retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
  316. if (retval != ERROR_OK)
  317. return retval;
  318. retval = cfi_get_u8(bank, 0, 0x0, &status);
  319. if (retval != ERROR_OK)
  320. return retval;
  321. if ((status ^ oldstatus) & 0x40) {
  322. LOG_ERROR("dq5 timeout, status: 0x%x", status);
  323. return ERROR_FLASH_OPERATION_FAILED;
  324. } else {
  325. LOG_DEBUG("status: 0x%x", status);
  326. return ERROR_OK;
  327. }
  328. }
  329. } else {/* no toggle: finished, OK */
  330. LOG_DEBUG("status: 0x%x", status);
  331. return ERROR_OK;
  332. }
  333. oldstatus = status;
  334. alive_sleep(1);
  335. } while (timeout-- > 0);
  336. LOG_ERROR("timeout, status: 0x%x", status);
  337. return ERROR_FLASH_BUSY;
  338. }
  339. static int cfi_read_intel_pri_ext(struct flash_bank *bank)
  340. {
  341. int retval;
  342. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  343. struct cfi_intel_pri_ext *pri_ext;
  344. if (cfi_info->pri_ext)
  345. free(cfi_info->pri_ext);
  346. pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
  347. if (pri_ext == NULL) {
  348. LOG_ERROR("Out of memory");
  349. return ERROR_FAIL;
  350. }
  351. cfi_info->pri_ext = pri_ext;
  352. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
  353. if (retval != ERROR_OK)
  354. return retval;
  355. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
  356. if (retval != ERROR_OK)
  357. return retval;
  358. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
  359. if (retval != ERROR_OK)
  360. return retval;
  361. if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
  362. retval = cfi_reset(bank);
  363. if (retval != ERROR_OK)
  364. return retval;
  365. LOG_ERROR("Could not read bank flash bank information");
  366. return ERROR_FLASH_BANK_INVALID;
  367. }
  368. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
  369. if (retval != ERROR_OK)
  370. return retval;
  371. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
  372. if (retval != ERROR_OK)
  373. return retval;
  374. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
  375. pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
  376. retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
  377. if (retval != ERROR_OK)
  378. return retval;
  379. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
  380. if (retval != ERROR_OK)
  381. return retval;
  382. retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
  383. if (retval != ERROR_OK)
  384. return retval;
  385. LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
  386. "0x%x, blk_status_reg_mask: 0x%x",
  387. pri_ext->feature_support,
  388. pri_ext->suspend_cmd_support,
  389. pri_ext->blk_status_reg_mask);
  390. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
  391. if (retval != ERROR_OK)
  392. return retval;
  393. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
  394. if (retval != ERROR_OK)
  395. return retval;
  396. LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
  397. (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
  398. (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
  399. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
  400. if (retval != ERROR_OK)
  401. return retval;
  402. if (pri_ext->num_protection_fields != 1) {
  403. LOG_WARNING("expected one protection register field, but found %i",
  404. pri_ext->num_protection_fields);
  405. }
  406. retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
  407. if (retval != ERROR_OK)
  408. return retval;
  409. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
  410. if (retval != ERROR_OK)
  411. return retval;
  412. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
  413. if (retval != ERROR_OK)
  414. return retval;
  415. LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
  416. "factory pre-programmed: %i, user programmable: %i",
  417. pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
  418. 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
  419. return ERROR_OK;
  420. }
  421. static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
  422. {
  423. int retval;
  424. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  425. struct cfi_spansion_pri_ext *pri_ext;
  426. if (cfi_info->pri_ext)
  427. free(cfi_info->pri_ext);
  428. pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
  429. if (pri_ext == NULL) {
  430. LOG_ERROR("Out of memory");
  431. return ERROR_FAIL;
  432. }
  433. cfi_info->pri_ext = pri_ext;
  434. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
  435. if (retval != ERROR_OK)
  436. return retval;
  437. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
  438. if (retval != ERROR_OK)
  439. return retval;
  440. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
  441. if (retval != ERROR_OK)
  442. return retval;
  443. if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
  444. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  445. if (retval != ERROR_OK)
  446. return retval;
  447. LOG_ERROR("Could not read spansion bank information");
  448. return ERROR_FLASH_BANK_INVALID;
  449. }
  450. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
  451. if (retval != ERROR_OK)
  452. return retval;
  453. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
  454. if (retval != ERROR_OK)
  455. return retval;
  456. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
  457. pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
  458. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
  459. if (retval != ERROR_OK)
  460. return retval;
  461. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
  462. if (retval != ERROR_OK)
  463. return retval;
  464. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
  465. if (retval != ERROR_OK)
  466. return retval;
  467. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
  468. if (retval != ERROR_OK)
  469. return retval;
  470. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
  471. if (retval != ERROR_OK)
  472. return retval;
  473. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
  474. if (retval != ERROR_OK)
  475. return retval;
  476. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
  477. if (retval != ERROR_OK)
  478. return retval;
  479. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
  480. if (retval != ERROR_OK)
  481. return retval;
  482. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
  483. if (retval != ERROR_OK)
  484. return retval;
  485. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
  486. if (retval != ERROR_OK)
  487. return retval;
  488. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
  489. if (retval != ERROR_OK)
  490. return retval;
  491. LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
  492. pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
  493. LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
  494. "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
  495. pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
  496. LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
  497. LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
  498. (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
  499. (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
  500. LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
  501. /* default values for implementation specific workarounds */
  502. pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
  503. pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
  504. pri_ext->_reversed_geometry = 0;
  505. return ERROR_OK;
  506. }
  507. static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
  508. {
  509. int retval;
  510. struct cfi_atmel_pri_ext atmel_pri_ext;
  511. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  512. struct cfi_spansion_pri_ext *pri_ext;
  513. if (cfi_info->pri_ext)
  514. free(cfi_info->pri_ext);
  515. pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
  516. if (pri_ext == NULL) {
  517. LOG_ERROR("Out of memory");
  518. return ERROR_FAIL;
  519. }
  520. /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
  521. * but a different primary extended query table.
  522. * We read the atmel table, and prepare a valid AMD/Spansion query table.
  523. */
  524. memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
  525. cfi_info->pri_ext = pri_ext;
  526. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
  527. if (retval != ERROR_OK)
  528. return retval;
  529. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
  530. if (retval != ERROR_OK)
  531. return retval;
  532. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
  533. if (retval != ERROR_OK)
  534. return retval;
  535. if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
  536. || (atmel_pri_ext.pri[2] != 'I')) {
  537. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  538. if (retval != ERROR_OK)
  539. return retval;
  540. LOG_ERROR("Could not read atmel bank information");
  541. return ERROR_FLASH_BANK_INVALID;
  542. }
  543. pri_ext->pri[0] = atmel_pri_ext.pri[0];
  544. pri_ext->pri[1] = atmel_pri_ext.pri[1];
  545. pri_ext->pri[2] = atmel_pri_ext.pri[2];
  546. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
  547. if (retval != ERROR_OK)
  548. return retval;
  549. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
  550. if (retval != ERROR_OK)
  551. return retval;
  552. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
  553. atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
  554. atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
  555. pri_ext->major_version = atmel_pri_ext.major_version;
  556. pri_ext->minor_version = atmel_pri_ext.minor_version;
  557. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
  558. if (retval != ERROR_OK)
  559. return retval;
  560. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
  561. if (retval != ERROR_OK)
  562. return retval;
  563. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
  564. if (retval != ERROR_OK)
  565. return retval;
  566. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
  567. if (retval != ERROR_OK)
  568. return retval;
  569. LOG_DEBUG(
  570. "features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
  571. atmel_pri_ext.features,
  572. atmel_pri_ext.bottom_boot,
  573. atmel_pri_ext.burst_mode,
  574. atmel_pri_ext.page_mode);
  575. if (atmel_pri_ext.features & 0x02)
  576. pri_ext->EraseSuspend = 2;
  577. /* some chips got it backwards... */
  578. if (cfi_info->device_id == AT49BV6416 ||
  579. cfi_info->device_id == AT49BV6416T) {
  580. if (atmel_pri_ext.bottom_boot)
  581. pri_ext->TopBottom = 3;
  582. else
  583. pri_ext->TopBottom = 2;
  584. } else {
  585. if (atmel_pri_ext.bottom_boot)
  586. pri_ext->TopBottom = 2;
  587. else
  588. pri_ext->TopBottom = 3;
  589. }
  590. pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
  591. pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
  592. return ERROR_OK;
  593. }
  594. static int cfi_read_0002_pri_ext(struct flash_bank *bank)
  595. {
  596. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  597. if (cfi_info->manufacturer == CFI_MFR_ATMEL)
  598. return cfi_read_atmel_pri_ext(bank);
  599. else
  600. return cfi_read_spansion_pri_ext(bank);
  601. }
  602. static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
  603. {
  604. int printed;
  605. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  606. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  607. printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
  608. buf += printed;
  609. buf_size -= printed;
  610. printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
  611. pri_ext->pri[1], pri_ext->pri[2],
  612. pri_ext->major_version, pri_ext->minor_version);
  613. buf += printed;
  614. buf_size -= printed;
  615. printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
  616. (pri_ext->SiliconRevision) >> 2,
  617. (pri_ext->SiliconRevision) & 0x03);
  618. buf += printed;
  619. buf_size -= printed;
  620. printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
  621. pri_ext->EraseSuspend,
  622. pri_ext->BlkProt);
  623. buf += printed;
  624. buf_size -= printed;
  625. snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
  626. (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
  627. (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
  628. return ERROR_OK;
  629. }
  630. static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
  631. {
  632. int printed;
  633. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  634. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  635. printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
  636. buf += printed;
  637. buf_size -= printed;
  638. printed = snprintf(buf,
  639. buf_size,
  640. "pri: '%c%c%c', version: %c.%c\n",
  641. pri_ext->pri[0],
  642. pri_ext->pri[1],
  643. pri_ext->pri[2],
  644. pri_ext->major_version,
  645. pri_ext->minor_version);
  646. buf += printed;
  647. buf_size -= printed;
  648. printed = snprintf(buf,
  649. buf_size,
  650. "feature_support: 0x%" PRIx32 ", "
  651. "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
  652. pri_ext->feature_support,
  653. pri_ext->suspend_cmd_support,
  654. pri_ext->blk_status_reg_mask);
  655. buf += printed;
  656. buf_size -= printed;
  657. printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
  658. (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
  659. (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
  660. buf += printed;
  661. buf_size -= printed;
  662. snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
  663. "factory pre-programmed: %i, user programmable: %i\n",
  664. pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
  665. 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
  666. return ERROR_OK;
  667. }
  668. /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
  669. */
  670. FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
  671. {
  672. struct cfi_flash_bank *cfi_info;
  673. if (CMD_ARGC < 6)
  674. return ERROR_COMMAND_SYNTAX_ERROR;
  675. /* both widths must:
  676. * - not exceed max value;
  677. * - not be null;
  678. * - be equal to a power of 2.
  679. * bus must be wide enough to hold one chip */
  680. if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
  681. || (bank->bus_width > CFI_MAX_BUS_WIDTH)
  682. || (bank->chip_width == 0)
  683. || (bank->bus_width == 0)
  684. || (bank->chip_width & (bank->chip_width - 1))
  685. || (bank->bus_width & (bank->bus_width - 1))
  686. || (bank->chip_width > bank->bus_width)) {
  687. LOG_ERROR("chip and bus width have to specified in bytes");
  688. return ERROR_FLASH_BANK_INVALID;
  689. }
  690. cfi_info = malloc(sizeof(struct cfi_flash_bank));
  691. cfi_info->probed = 0;
  692. cfi_info->erase_region_info = NULL;
  693. cfi_info->pri_ext = NULL;
  694. bank->driver_priv = cfi_info;
  695. cfi_info->x16_as_x8 = 0;
  696. cfi_info->jedec_probe = 0;
  697. cfi_info->not_cfi = 0;
  698. for (unsigned i = 6; i < CMD_ARGC; i++) {
  699. if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
  700. cfi_info->x16_as_x8 = 1;
  701. else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
  702. cfi_info->jedec_probe = 1;
  703. }
  704. /* bank wasn't probed yet */
  705. cfi_info->qry[0] = 0xff;
  706. return ERROR_OK;
  707. }
  708. static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
  709. {
  710. int retval;
  711. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  712. int i;
  713. cfi_intel_clear_status_register(bank);
  714. for (i = first; i <= last; i++) {
  715. retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0));
  716. if (retval != ERROR_OK)
  717. return retval;
  718. retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0));
  719. if (retval != ERROR_OK)
  720. return retval;
  721. uint8_t status;
  722. retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
  723. if (retval != ERROR_OK)
  724. return retval;
  725. if (status == 0x80)
  726. bank->sectors[i].is_erased = 1;
  727. else {
  728. retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  729. if (retval != ERROR_OK)
  730. return retval;
  731. LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
  732. PRIx32, i, bank->base);
  733. return ERROR_FLASH_OPERATION_FAILED;
  734. }
  735. }
  736. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  737. }
  738. static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
  739. {
  740. int retval;
  741. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  742. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  743. int i;
  744. for (i = first; i <= last; i++) {
  745. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
  746. if (retval != ERROR_OK)
  747. return retval;
  748. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
  749. if (retval != ERROR_OK)
  750. return retval;
  751. retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1));
  752. if (retval != ERROR_OK)
  753. return retval;
  754. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
  755. if (retval != ERROR_OK)
  756. return retval;
  757. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
  758. if (retval != ERROR_OK)
  759. return retval;
  760. retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0));
  761. if (retval != ERROR_OK)
  762. return retval;
  763. if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
  764. bank->sectors[i].is_erased = 1;
  765. else {
  766. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  767. if (retval != ERROR_OK)
  768. return retval;
  769. LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
  770. PRIx32, i, bank->base);
  771. return ERROR_FLASH_OPERATION_FAILED;
  772. }
  773. }
  774. return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  775. }
  776. static int cfi_erase(struct flash_bank *bank, int first, int last)
  777. {
  778. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  779. if (bank->target->state != TARGET_HALTED) {
  780. LOG_ERROR("Target not halted");
  781. return ERROR_TARGET_NOT_HALTED;
  782. }
  783. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  784. return ERROR_FLASH_SECTOR_INVALID;
  785. if (cfi_info->qry[0] != 'Q')
  786. return ERROR_FLASH_BANK_NOT_PROBED;
  787. switch (cfi_info->pri_id) {
  788. case 1:
  789. case 3:
  790. return cfi_intel_erase(bank, first, last);
  791. break;
  792. case 2:
  793. return cfi_spansion_erase(bank, first, last);
  794. break;
  795. default:
  796. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  797. break;
  798. }
  799. return ERROR_OK;
  800. }
  801. static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
  802. {
  803. int retval;
  804. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  805. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  806. int retry = 0;
  807. int i;
  808. /* if the device supports neither legacy lock/unlock (bit 3) nor
  809. * instant individual block locking (bit 5).
  810. */
  811. if (!(pri_ext->feature_support & 0x28)) {
  812. LOG_ERROR("lock/unlock not supported on flash");
  813. return ERROR_FLASH_OPERATION_FAILED;
  814. }
  815. cfi_intel_clear_status_register(bank);
  816. for (i = first; i <= last; i++) {
  817. retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0));
  818. if (retval != ERROR_OK)
  819. return retval;
  820. if (set) {
  821. retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0));
  822. if (retval != ERROR_OK)
  823. return retval;
  824. bank->sectors[i].is_protected = 1;
  825. } else {
  826. retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0));
  827. if (retval != ERROR_OK)
  828. return retval;
  829. bank->sectors[i].is_protected = 0;
  830. }
  831. /* instant individual block locking doesn't require reading of the status register
  832. **/
  833. if (!(pri_ext->feature_support & 0x20)) {
  834. /* Clear lock bits operation may take up to 1.4s */
  835. uint8_t status;
  836. retval = cfi_intel_wait_status_busy(bank, 1400, &status);
  837. if (retval != ERROR_OK)
  838. return retval;
  839. } else {
  840. uint8_t block_status;
  841. /* read block lock bit, to verify status */
  842. retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55));
  843. if (retval != ERROR_OK)
  844. return retval;
  845. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  846. if (retval != ERROR_OK)
  847. return retval;
  848. if ((block_status & 0x1) != set) {
  849. LOG_ERROR(
  850. "couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
  851. set, block_status);
  852. retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55));
  853. if (retval != ERROR_OK)
  854. return retval;
  855. uint8_t status;
  856. retval = cfi_intel_wait_status_busy(bank, 10, &status);
  857. if (retval != ERROR_OK)
  858. return retval;
  859. if (retry > 10)
  860. return ERROR_FLASH_OPERATION_FAILED;
  861. else {
  862. i--;
  863. retry++;
  864. }
  865. }
  866. }
  867. }
  868. /* if the device doesn't support individual block lock bits set/clear,
  869. * all blocks have been unlocked in parallel, so we set those that should be protected
  870. */
  871. if ((!set) && (!(pri_ext->feature_support & 0x20))) {
  872. /* FIX!!! this code path is broken!!!
  873. *
  874. * The correct approach is:
  875. *
  876. * 1. read out current protection status
  877. *
  878. * 2. override read out protection status w/unprotected.
  879. *
  880. * 3. re-protect what should be protected.
  881. *
  882. */
  883. for (i = 0; i < bank->num_sectors; i++) {
  884. if (bank->sectors[i].is_protected == 1) {
  885. cfi_intel_clear_status_register(bank);
  886. retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0));
  887. if (retval != ERROR_OK)
  888. return retval;
  889. retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0));
  890. if (retval != ERROR_OK)
  891. return retval;
  892. uint8_t status;
  893. retval = cfi_intel_wait_status_busy(bank, 100, &status);
  894. if (retval != ERROR_OK)
  895. return retval;
  896. }
  897. }
  898. }
  899. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  900. }
  901. static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
  902. {
  903. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  904. if (bank->target->state != TARGET_HALTED) {
  905. LOG_ERROR("Target not halted");
  906. return ERROR_TARGET_NOT_HALTED;
  907. }
  908. if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
  909. LOG_ERROR("Invalid sector range");
  910. return ERROR_FLASH_SECTOR_INVALID;
  911. }
  912. if (cfi_info->qry[0] != 'Q')
  913. return ERROR_FLASH_BANK_NOT_PROBED;
  914. switch (cfi_info->pri_id) {
  915. case 1:
  916. case 3:
  917. return cfi_intel_protect(bank, set, first, last);
  918. break;
  919. default:
  920. LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
  921. return ERROR_OK;
  922. }
  923. }
  924. /* Convert code image to target endian
  925. * FIXME create general block conversion fcts in target.c?) */
  926. static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
  927. const uint32_t *src, uint32_t count)
  928. {
  929. uint32_t i;
  930. for (i = 0; i < count; i++) {
  931. target_buffer_set_u32(target, dest, *src);
  932. dest += 4;
  933. src++;
  934. }
  935. }
  936. static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
  937. {
  938. struct target *target = bank->target;
  939. uint8_t buf[CFI_MAX_BUS_WIDTH];
  940. cfi_command(bank, cmd, buf);
  941. switch (bank->bus_width) {
  942. case 1:
  943. return buf[0];
  944. break;
  945. case 2:
  946. return target_buffer_get_u16(target, buf);
  947. break;
  948. case 4:
  949. return target_buffer_get_u32(target, buf);
  950. break;
  951. default:
  952. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
  953. bank->bus_width);
  954. return 0;
  955. }
  956. }
  957. static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
  958. uint32_t address, uint32_t count)
  959. {
  960. struct target *target = bank->target;
  961. struct reg_param reg_params[7];
  962. struct arm_algorithm arm_algo;
  963. struct working_area *write_algorithm;
  964. struct working_area *source = NULL;
  965. uint32_t buffer_size = 32768;
  966. uint32_t write_command_val, busy_pattern_val, error_pattern_val;
  967. /* algorithm register usage:
  968. * r0: source address (in RAM)
  969. * r1: target address (in Flash)
  970. * r2: count
  971. * r3: flash write command
  972. * r4: status byte (returned to host)
  973. * r5: busy test pattern
  974. * r6: error test pattern
  975. */
  976. /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
  977. static const uint32_t word_32_code[] = {
  978. 0xe4904004, /* loop: ldr r4, [r0], #4 */
  979. 0xe5813000, /* str r3, [r1] */
  980. 0xe5814000, /* str r4, [r1] */
  981. 0xe5914000, /* busy: ldr r4, [r1] */
  982. 0xe0047005, /* and r7, r4, r5 */
  983. 0xe1570005, /* cmp r7, r5 */
  984. 0x1afffffb, /* bne busy */
  985. 0xe1140006, /* tst r4, r6 */
  986. 0x1a000003, /* bne done */
  987. 0xe2522001, /* subs r2, r2, #1 */
  988. 0x0a000001, /* beq done */
  989. 0xe2811004, /* add r1, r1 #4 */
  990. 0xeafffff2, /* b loop */
  991. 0xeafffffe /* done: b -2 */
  992. };
  993. /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
  994. static const uint32_t word_16_code[] = {
  995. 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
  996. 0xe1c130b0, /* strh r3, [r1] */
  997. 0xe1c140b0, /* strh r4, [r1] */
  998. 0xe1d140b0, /* busy ldrh r4, [r1] */
  999. 0xe0047005, /* and r7, r4, r5 */
  1000. 0xe1570005, /* cmp r7, r5 */
  1001. 0x1afffffb, /* bne busy */
  1002. 0xe1140006, /* tst r4, r6 */
  1003. 0x1a000003, /* bne done */
  1004. 0xe2522001, /* subs r2, r2, #1 */
  1005. 0x0a000001, /* beq done */
  1006. 0xe2811002, /* add r1, r1 #2 */
  1007. 0xeafffff2, /* b loop */
  1008. 0xeafffffe /* done: b -2 */
  1009. };
  1010. /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
  1011. static const uint32_t word_8_code[] = {
  1012. 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
  1013. 0xe5c13000, /* strb r3, [r1] */
  1014. 0xe5c14000, /* strb r4, [r1] */
  1015. 0xe5d14000, /* busy ldrb r4, [r1] */
  1016. 0xe0047005, /* and r7, r4, r5 */
  1017. 0xe1570005, /* cmp r7, r5 */
  1018. 0x1afffffb, /* bne busy */
  1019. 0xe1140006, /* tst r4, r6 */
  1020. 0x1a000003, /* bne done */
  1021. 0xe2522001, /* subs r2, r2, #1 */
  1022. 0x0a000001, /* beq done */
  1023. 0xe2811001, /* add r1, r1 #1 */
  1024. 0xeafffff2, /* b loop */
  1025. 0xeafffffe /* done: b -2 */
  1026. };
  1027. uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
  1028. const uint32_t *target_code_src;
  1029. uint32_t target_code_size;
  1030. int retval = ERROR_OK;
  1031. /* check we have a supported arch */
  1032. if (is_arm(target_to_arm(target))) {
  1033. /* All other ARM CPUs have 32 bit instructions */
  1034. arm_algo.common_magic = ARM_COMMON_MAGIC;
  1035. arm_algo.core_mode = ARM_MODE_SVC;
  1036. arm_algo.core_state = ARM_STATE_ARM;
  1037. } else {
  1038. LOG_ERROR("Unknown architecture");
  1039. return ERROR_FAIL;
  1040. }
  1041. cfi_intel_clear_status_register(bank);
  1042. /* If we are setting up the write_algorith, we need target_code_src
  1043. * if not we only need target_code_size. */
  1044. /* However, we don't want to create multiple code paths, so we
  1045. * do the unnecessary evaluation of target_code_src, which the
  1046. * compiler will probably nicely optimize away if not needed */
  1047. /* prepare algorithm code for target endian */
  1048. switch (bank->bus_width) {
  1049. case 1:
  1050. target_code_src = word_8_code;
  1051. target_code_size = sizeof(word_8_code);
  1052. break;
  1053. case 2:
  1054. target_code_src = word_16_code;
  1055. target_code_size = sizeof(word_16_code);
  1056. break;
  1057. case 4:
  1058. target_code_src = word_32_code;
  1059. target_code_size = sizeof(word_32_code);
  1060. break;
  1061. default:
  1062. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
  1063. bank->bus_width);
  1064. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1065. }
  1066. /* flash write code */
  1067. if (target_code_size > sizeof(target_code)) {
  1068. LOG_WARNING("Internal error - target code buffer to small. "
  1069. "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
  1070. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1071. }
  1072. cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
  1073. /* Get memory for block write handler */
  1074. retval = target_alloc_working_area(target,
  1075. target_code_size,
  1076. &write_algorithm);
  1077. if (retval != ERROR_OK) {
  1078. LOG_WARNING("No working area available, can't do block memory writes");
  1079. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1080. }
  1081. ;
  1082. /* write algorithm code to working area */
  1083. retval = target_write_buffer(target, write_algorithm->address,
  1084. target_code_size, target_code);
  1085. if (retval != ERROR_OK) {
  1086. LOG_ERROR("Unable to write block write code to target");
  1087. goto cleanup;
  1088. }
  1089. /* Get a workspace buffer for the data to flash starting with 32k size.
  1090. * Half size until buffer would be smaller 256 Bytes then fail back */
  1091. /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
  1092. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  1093. buffer_size /= 2;
  1094. if (buffer_size <= 256) {
  1095. LOG_WARNING(
  1096. "no large enough working area available, can't do block memory writes");
  1097. retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1098. goto cleanup;
  1099. }
  1100. }
  1101. ;
  1102. /* setup algo registers */
  1103. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  1104. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1105. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  1106. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  1107. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
  1108. init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
  1109. init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
  1110. /* prepare command and status register patterns */
  1111. write_command_val = cfi_command_val(bank, 0x40);
  1112. busy_pattern_val = cfi_command_val(bank, 0x80);
  1113. error_pattern_val = cfi_command_val(bank, 0x7e);
  1114. LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
  1115. source->address, buffer_size);
  1116. /* Programming main loop */
  1117. while (count > 0) {
  1118. uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
  1119. uint32_t wsm_error;
  1120. retval = target_write_buffer(target, source->address, thisrun_count, buffer);
  1121. if (retval != ERROR_OK)
  1122. goto cleanup;
  1123. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  1124. buf_set_u32(reg_params[1].value, 0, 32, address);
  1125. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
  1126. buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
  1127. buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
  1128. buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
  1129. LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32,
  1130. thisrun_count, address);
  1131. /* Execute algorithm, assume breakpoint for last instruction */
  1132. retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
  1133. write_algorithm->address,
  1134. write_algorithm->address + target_code_size -
  1135. sizeof(uint32_t),
  1136. 10000, /* 10s should be enough for max. 32k of data */
  1137. &arm_algo);
  1138. /* On failure try a fall back to direct word writes */
  1139. if (retval != ERROR_OK) {
  1140. cfi_intel_clear_status_register(bank);
  1141. LOG_ERROR(
  1142. "Execution of flash algorythm failed. Can't fall back. Please report.");
  1143. retval = ERROR_FLASH_OPERATION_FAILED;
  1144. /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
  1145. /* FIXME To allow fall back or recovery, we must save the actual status
  1146. * somewhere, so that a higher level code can start recovery. */
  1147. goto cleanup;
  1148. }
  1149. /* Check return value from algo code */
  1150. wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
  1151. if (wsm_error) {
  1152. /* read status register (outputs debug information) */
  1153. uint8_t status;
  1154. cfi_intel_wait_status_busy(bank, 100, &status);
  1155. cfi_intel_clear_status_register(bank);
  1156. retval = ERROR_FLASH_OPERATION_FAILED;
  1157. goto cleanup;
  1158. }
  1159. buffer += thisrun_count;
  1160. address += thisrun_count;
  1161. count -= thisrun_count;
  1162. keep_alive();
  1163. }
  1164. /* free up resources */
  1165. cleanup:
  1166. if (source)
  1167. target_free_working_area(target, source);
  1168. target_free_working_area(target, write_algorithm);
  1169. destroy_reg_param(&reg_params[0]);
  1170. destroy_reg_param(&reg_params[1]);
  1171. destroy_reg_param(&reg_params[2]);
  1172. destroy_reg_param(&reg_params[3]);
  1173. destroy_reg_param(&reg_params[4]);
  1174. destroy_reg_param(&reg_params[5]);
  1175. destroy_reg_param(&reg_params[6]);
  1176. return retval;
  1177. }
  1178. static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffer,
  1179. uint32_t address, uint32_t count)
  1180. {
  1181. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1182. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1183. struct target *target = bank->target;
  1184. struct reg_param reg_params[10];
  1185. struct mips32_algorithm mips32_info;
  1186. struct working_area *write_algorithm;
  1187. struct working_area *source;
  1188. uint32_t buffer_size = 32768;
  1189. uint32_t status;
  1190. int retval = ERROR_OK;
  1191. /* input parameters -
  1192. * 4 A0 = source address
  1193. * 5 A1 = destination address
  1194. * 6 A2 = number of writes
  1195. * 7 A3 = flash write command
  1196. * 8 T0 = constant to mask DQ7 bits (also used for Dq5 with shift)
  1197. * output parameters -
  1198. * 9 T1 = 0x80 ok 0x00 bad
  1199. * temp registers -
  1200. * 10 T2 = value read from flash to test status
  1201. * 11 T3 = holding register
  1202. * unlock registers -
  1203. * 12 T4 = unlock1_addr
  1204. * 13 T5 = unlock1_cmd
  1205. * 14 T6 = unlock2_addr
  1206. * 15 T7 = unlock2_cmd */
  1207. static const uint32_t mips_word_16_code[] = {
  1208. /* start: */
  1209. MIPS32_LHU(9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */
  1210. MIPS32_ADDI(4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */
  1211. MIPS32_SH(13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */
  1212. MIPS32_SH(15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */
  1213. MIPS32_SH(7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */
  1214. MIPS32_SH(9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */
  1215. MIPS32_NOP, /* nop */
  1216. /* busy: */
  1217. MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
  1218. MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
  1219. MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
  1220. MIPS32_BNE(11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
  1221. MIPS32_NOP, /* nop */
  1222. MIPS32_SRL(10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */
  1223. MIPS32_AND(11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */
  1224. MIPS32_BNE(11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */
  1225. MIPS32_NOP, /* nop */
  1226. MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
  1227. MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
  1228. MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
  1229. MIPS32_BNE(11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
  1230. MIPS32_NOP, /* nop */
  1231. MIPS32_XOR(9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */
  1232. MIPS32_BEQ(9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */
  1233. MIPS32_NOP, /* nop */
  1234. /* cont: */
  1235. MIPS32_ADDI(6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */
  1236. MIPS32_BNE(6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */
  1237. MIPS32_NOP, /* nop */
  1238. MIPS32_LUI(9, 0), /* lui $t1, 0 */
  1239. MIPS32_ORI(9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */
  1240. MIPS32_B(4), /* b done ; goto done */
  1241. MIPS32_NOP, /* nop */
  1242. /* cont2: */
  1243. MIPS32_ADDI(5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */
  1244. MIPS32_B(NEG16(33)), /* b start ; goto start */
  1245. MIPS32_NOP, /* nop */
  1246. /* done: */
  1247. MIPS32_SDBBP, /* sdbbp ; break(); */
  1248. };
  1249. mips32_info.common_magic = MIPS32_COMMON_MAGIC;
  1250. mips32_info.isa_mode = MIPS32_ISA_MIPS32;
  1251. int target_code_size = 0;
  1252. const uint32_t *target_code_src = NULL;
  1253. switch (bank->bus_width) {
  1254. case 2:
  1255. /* Check for DQ5 support */
  1256. if (cfi_info->status_poll_mask & (1 << 5)) {
  1257. target_code_src = mips_word_16_code;
  1258. target_code_size = sizeof(mips_word_16_code);
  1259. } else {
  1260. LOG_ERROR("Need DQ5 support");
  1261. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1262. /* target_code_src = mips_word_16_code_dq7only; */
  1263. /* target_code_size = sizeof(mips_word_16_code_dq7only); */
  1264. }
  1265. break;
  1266. default:
  1267. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
  1268. bank->bus_width);
  1269. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1270. }
  1271. /* flash write code */
  1272. uint8_t *target_code;
  1273. /* convert bus-width dependent algorithm code to correct endianness */
  1274. target_code = malloc(target_code_size);
  1275. if (target_code == NULL) {
  1276. LOG_ERROR("Out of memory");
  1277. return ERROR_FAIL;
  1278. }
  1279. cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
  1280. /* allocate working area */
  1281. retval = target_alloc_working_area(target, target_code_size,
  1282. &write_algorithm);
  1283. if (retval != ERROR_OK) {
  1284. free(target_code);
  1285. return retval;
  1286. }
  1287. /* write algorithm code to working area */
  1288. retval = target_write_buffer(target, write_algorithm->address,
  1289. target_code_size, target_code);
  1290. if (retval != ERROR_OK) {
  1291. free(target_code);
  1292. return retval;
  1293. }
  1294. free(target_code);
  1295. /* the following code still assumes target code is fixed 24*4 bytes */
  1296. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  1297. buffer_size /= 2;
  1298. if (buffer_size <= 256) {
  1299. /* we already allocated the writing code, but failed to get a
  1300. * buffer, free the algorithm */
  1301. target_free_working_area(target, write_algorithm);
  1302. LOG_WARNING(
  1303. "not enough working area available, can't do block memory writes");
  1304. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1305. }
  1306. }
  1307. ;
  1308. init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);
  1309. init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
  1310. init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT);
  1311. init_reg_param(&reg_params[3], "a3", 32, PARAM_OUT);
  1312. init_reg_param(&reg_params[4], "t0", 32, PARAM_OUT);
  1313. init_reg_param(&reg_params[5], "t1", 32, PARAM_IN);
  1314. init_reg_param(&reg_params[6], "t4", 32, PARAM_OUT);
  1315. init_reg_param(&reg_params[7], "t5", 32, PARAM_OUT);
  1316. init_reg_param(&reg_params[8], "t6", 32, PARAM_OUT);
  1317. init_reg_param(&reg_params[9], "t7", 32, PARAM_OUT);
  1318. while (count > 0) {
  1319. uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
  1320. retval = target_write_buffer(target, source->address, thisrun_count, buffer);
  1321. if (retval != ERROR_OK)
  1322. break;
  1323. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  1324. buf_set_u32(reg_params[1].value, 0, 32, address);
  1325. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
  1326. buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
  1327. buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
  1328. buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
  1329. buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
  1330. buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
  1331. buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
  1332. retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
  1333. write_algorithm->address,
  1334. write_algorithm->address + ((target_code_size) - 4),
  1335. 10000, &mips32_info);
  1336. if (retval != ERROR_OK)
  1337. break;
  1338. status = buf_get_u32(reg_params[5].value, 0, 32);
  1339. if (status != 0x80) {
  1340. LOG_ERROR("flash write block failed status: 0x%" PRIx32, status);
  1341. retval = ERROR_FLASH_OPERATION_FAILED;
  1342. break;
  1343. }
  1344. buffer += thisrun_count;
  1345. address += thisrun_count;
  1346. count -= thisrun_count;
  1347. }
  1348. target_free_all_working_areas(target);
  1349. destroy_reg_param(&reg_params[0]);
  1350. destroy_reg_param(&reg_params[1]);
  1351. destroy_reg_param(&reg_params[2]);
  1352. destroy_reg_param(&reg_params[3]);
  1353. destroy_reg_param(&reg_params[4]);
  1354. destroy_reg_param(&reg_params[5]);
  1355. destroy_reg_param(&reg_params[6]);
  1356. destroy_reg_param(&reg_params[7]);
  1357. destroy_reg_param(&reg_params[8]);
  1358. destroy_reg_param(&reg_params[9]);
  1359. return retval;
  1360. }
  1361. static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
  1362. uint32_t address, uint32_t count)
  1363. {
  1364. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1365. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1366. struct target *target = bank->target;
  1367. struct reg_param reg_params[10];
  1368. void *arm_algo;
  1369. struct arm_algorithm armv4_5_algo;
  1370. struct armv7m_algorithm armv7m_algo;
  1371. struct working_area *write_algorithm;
  1372. struct working_area *source;
  1373. uint32_t buffer_size = 32768;
  1374. uint32_t status;
  1375. int retval = ERROR_OK;
  1376. /* input parameters -
  1377. * R0 = source address
  1378. * R1 = destination address
  1379. * R2 = number of writes
  1380. * R3 = flash write command
  1381. * R4 = constant to mask DQ7 bits (also used for Dq5 with shift)
  1382. * output parameters -
  1383. * R5 = 0x80 ok 0x00 bad
  1384. * temp registers -
  1385. * R6 = value read from flash to test status
  1386. * R7 = holding register
  1387. * unlock registers -
  1388. * R8 = unlock1_addr
  1389. * R9 = unlock1_cmd
  1390. * R10 = unlock2_addr
  1391. * R11 = unlock2_cmd */
  1392. /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
  1393. static const uint32_t armv4_5_word_32_code[] = {
  1394. /* 00008100 <sp_32_code>: */
  1395. 0xe4905004, /* ldr r5, [r0], #4 */
  1396. 0xe5889000, /* str r9, [r8] */
  1397. 0xe58ab000, /* str r11, [r10] */
  1398. 0xe5883000, /* str r3, [r8] */
  1399. 0xe5815000, /* str r5, [r1] */
  1400. 0xe1a00000, /* nop */
  1401. /* 00008110 <sp_32_busy>: */
  1402. 0xe5916000, /* ldr r6, [r1] */
  1403. 0xe0257006, /* eor r7, r5, r6 */
  1404. 0xe0147007, /* ands r7, r4, r7 */
  1405. 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
  1406. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1407. 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
  1408. 0xe5916000, /* ldr r6, [r1] */
  1409. 0xe0257006, /* eor r7, r5, r6 */
  1410. 0xe0147007, /* ands r7, r4, r7 */
  1411. 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
  1412. 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
  1413. 0x1a000004, /* bne 8154 <sp_32_done> */
  1414. /* 00008140 <sp_32_cont>: */
  1415. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1416. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1417. 0x0a000001, /* beq 8154 <sp_32_done> */
  1418. 0xe2811004, /* add r1, r1, #4 ; 0x4 */
  1419. 0xeaffffe8, /* b 8100 <sp_32_code> */
  1420. /* 00008154 <sp_32_done>: */
  1421. 0xeafffffe /* b 8154 <sp_32_done> */
  1422. };
  1423. /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
  1424. static const uint32_t armv4_5_word_16_code[] = {
  1425. /* 00008158 <sp_16_code>: */
  1426. 0xe0d050b2, /* ldrh r5, [r0], #2 */
  1427. 0xe1c890b0, /* strh r9, [r8] */
  1428. 0xe1cab0b0, /* strh r11, [r10] */
  1429. 0xe1c830b0, /* strh r3, [r8] */
  1430. 0xe1c150b0, /* strh r5, [r1] */
  1431. 0xe1a00000, /* nop (mov r0,r0) */
  1432. /* 00008168 <sp_16_busy>: */
  1433. 0xe1d160b0, /* ldrh r6, [r1] */
  1434. 0xe0257006, /* eor r7, r5, r6 */
  1435. 0xe0147007, /* ands r7, r4, r7 */
  1436. 0x0a000007, /* beq 8198 <sp_16_cont> */
  1437. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1438. 0x0afffff9, /* beq 8168 <sp_16_busy> */
  1439. 0xe1d160b0, /* ldrh r6, [r1] */
  1440. 0xe0257006, /* eor r7, r5, r6 */
  1441. 0xe0147007, /* ands r7, r4, r7 */
  1442. 0x0a000001, /* beq 8198 <sp_16_cont> */
  1443. 0xe3a05000, /* mov r5, #0 ; 0x0 */
  1444. 0x1a000004, /* bne 81ac <sp_16_done> */
  1445. /* 00008198 <sp_16_cont>: */
  1446. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1447. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1448. 0x0a000001, /* beq 81ac <sp_16_done> */
  1449. 0xe2811002, /* add r1, r1, #2 ; 0x2 */
  1450. 0xeaffffe8, /* b 8158 <sp_16_code> */
  1451. /* 000081ac <sp_16_done>: */
  1452. 0xeafffffe /* b 81ac <sp_16_done> */
  1453. };
  1454. /* see contib/loaders/flash/armv7m_cfi_span_16.s for src */
  1455. static const uint32_t armv7m_word_16_code[] = {
  1456. 0x5B02F830,
  1457. 0x9000F8A8,
  1458. 0xB000F8AA,
  1459. 0x3000F8A8,
  1460. 0xBF00800D,
  1461. 0xEA85880E,
  1462. 0x40270706,
  1463. 0xEA16D00A,
  1464. 0xD0F70694,
  1465. 0xEA85880E,
  1466. 0x40270706,
  1467. 0xF04FD002,
  1468. 0xD1070500,
  1469. 0xD0023A01,
  1470. 0x0102F101,
  1471. 0xF04FE7E0,
  1472. 0xE7FF0580,
  1473. 0x0000BE00
  1474. };
  1475. /* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
  1476. static const uint32_t armv4_5_word_16_code_dq7only[] = {
  1477. /* <sp_16_code>: */
  1478. 0xe0d050b2, /* ldrh r5, [r0], #2 */
  1479. 0xe1c890b0, /* strh r9, [r8] */
  1480. 0xe1cab0b0, /* strh r11, [r10] */
  1481. 0xe1c830b0, /* strh r3, [r8] */
  1482. 0xe1c150b0, /* strh r5, [r1] */
  1483. 0xe1a00000, /* nop (mov r0,r0) */
  1484. /* <sp_16_busy>: */
  1485. 0xe1d160b0, /* ldrh r6, [r1] */
  1486. 0xe0257006, /* eor r7, r5, r6 */
  1487. 0xe2177080, /* ands r7, #0x80 */
  1488. 0x1afffffb, /* bne 8168 <sp_16_busy> */
  1489. /* */
  1490. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1491. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1492. 0x0a000001, /* beq 81ac <sp_16_done> */
  1493. 0xe2811002, /* add r1, r1, #2 ; 0x2 */
  1494. 0xeafffff0, /* b 8158 <sp_16_code> */
  1495. /* 000081ac <sp_16_done>: */
  1496. 0xeafffffe /* b 81ac <sp_16_done> */
  1497. };
  1498. /* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
  1499. static const uint32_t armv4_5_word_8_code[] = {
  1500. /* 000081b0 <sp_16_code_end>: */
  1501. 0xe4d05001, /* ldrb r5, [r0], #1 */
  1502. 0xe5c89000, /* strb r9, [r8] */
  1503. 0xe5cab000, /* strb r11, [r10] */
  1504. 0xe5c83000, /* strb r3, [r8] */
  1505. 0xe5c15000, /* strb r5, [r1] */
  1506. 0xe1a00000, /* nop (mov r0,r0) */
  1507. /* 000081c0 <sp_8_busy>: */
  1508. 0xe5d16000, /* ldrb r6, [r1] */
  1509. 0xe0257006, /* eor r7, r5, r6 */
  1510. 0xe0147007, /* ands r7, r4, r7 */
  1511. 0x0a000007, /* beq 81f0 <sp_8_cont> */
  1512. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1513. 0x0afffff9, /* beq 81c0 <sp_8_busy> */
  1514. 0xe5d16000, /* ldrb r6, [r1] */
  1515. 0xe0257006, /* eor r7, r5, r6 */
  1516. 0xe0147007, /* ands r7, r4, r7 */
  1517. 0x0a000001, /* beq 81f0 <sp_8_cont> */
  1518. 0xe3a05000, /* mov r5, #0 ; 0x0 */
  1519. 0x1a000004, /* bne 8204 <sp_8_done> */
  1520. /* 000081f0 <sp_8_cont>: */
  1521. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1522. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1523. 0x0a000001, /* beq 8204 <sp_8_done> */
  1524. 0xe2811001, /* add r1, r1, #1 ; 0x1 */
  1525. 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
  1526. /* 00008204 <sp_8_done>: */
  1527. 0xeafffffe /* b 8204 <sp_8_done> */
  1528. };
  1529. if (strncmp(target_type_name(target), "mips_m4k", 8) == 0)
  1530. return cfi_spansion_write_block_mips(bank, buffer, address, count);
  1531. if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */
  1532. armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
  1533. armv7m_algo.core_mode = ARM_MODE_THREAD;
  1534. arm_algo = &armv7m_algo;
  1535. } else if (is_arm(target_to_arm(target))) {
  1536. /* All other ARM CPUs have 32 bit instructions */
  1537. armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
  1538. armv4_5_algo.core_mode = ARM_MODE_SVC;
  1539. armv4_5_algo.core_state = ARM_STATE_ARM;
  1540. arm_algo = &armv4_5_algo;
  1541. } else {
  1542. LOG_ERROR("Unknown architecture");
  1543. return ERROR_FAIL;
  1544. }
  1545. int target_code_size = 0;
  1546. const uint32_t *target_code_src = NULL;
  1547. switch (bank->bus_width) {
  1548. case 1:
  1549. if (is_armv7m(target_to_armv7m(target))) {
  1550. LOG_ERROR("Unknown ARM architecture");
  1551. return ERROR_FAIL;
  1552. }
  1553. target_code_src = armv4_5_word_8_code;
  1554. target_code_size = sizeof(armv4_5_word_8_code);
  1555. break;
  1556. case 2:
  1557. /* Check for DQ5 support */
  1558. if (cfi_info->status_poll_mask & (1 << 5)) {
  1559. if (is_armv7m(target_to_armv7m(target))) {
  1560. /* armv7m target */
  1561. target_code_src = armv7m_word_16_code;
  1562. target_code_size = sizeof(armv7m_word_16_code);
  1563. } else { /* armv4_5 target */
  1564. target_code_src = armv4_5_word_16_code;
  1565. target_code_size = sizeof(armv4_5_word_16_code);
  1566. }
  1567. } else {
  1568. /* No DQ5 support. Use DQ7 DATA# polling only. */
  1569. if (is_armv7m(target_to_armv7m(target))) {
  1570. LOG_ERROR("Unknown ARM architecture");
  1571. return ERROR_FAIL;
  1572. }
  1573. target_code_src = armv4_5_word_16_code_dq7only;
  1574. target_code_size = sizeof(armv4_5_word_16_code_dq7only);
  1575. }
  1576. break;
  1577. case 4:
  1578. if (is_armv7m(target_to_armv7m(target))) {
  1579. LOG_ERROR("Unknown ARM architecture");
  1580. return ERROR_FAIL;
  1581. }
  1582. target_code_src = armv4_5_word_32_code;
  1583. target_code_size = sizeof(armv4_5_word_32_code);
  1584. break;
  1585. default:
  1586. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
  1587. bank->bus_width);
  1588. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1589. }
  1590. /* flash write code */
  1591. uint8_t *target_code;
  1592. /* convert bus-width dependent algorithm code to correct endianness */
  1593. target_code = malloc(target_code_size);
  1594. if (target_code == NULL) {
  1595. LOG_ERROR("Out of memory");
  1596. return ERROR_FAIL;
  1597. }
  1598. cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
  1599. /* allocate working area */
  1600. retval = target_alloc_working_area(target, target_code_size,
  1601. &write_algorithm);
  1602. if (retval != ERROR_OK) {
  1603. free(target_code);
  1604. return retval;
  1605. }
  1606. /* write algorithm code to working area */
  1607. retval = target_write_buffer(target, write_algorithm->address,
  1608. target_code_size, target_code);
  1609. if (retval != ERROR_OK) {
  1610. free(target_code);
  1611. return retval;
  1612. }
  1613. free(target_code);
  1614. /* the following code still assumes target code is fixed 24*4 bytes */
  1615. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  1616. buffer_size /= 2;
  1617. if (buffer_size <= 256) {
  1618. /* we already allocated the writing code, but failed to get a
  1619. * buffer, free the algorithm */
  1620. target_free_working_area(target, write_algorithm);
  1621. LOG_WARNING(
  1622. "not enough working area available, can't do block memory writes");
  1623. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1624. }
  1625. }
  1626. ;
  1627. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  1628. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1629. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  1630. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  1631. init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
  1632. init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
  1633. init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
  1634. init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
  1635. init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
  1636. init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
  1637. while (count > 0) {
  1638. uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
  1639. retval = target_write_buffer(target, source->address, thisrun_count, buffer);
  1640. if (retval != ERROR_OK)
  1641. break;
  1642. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  1643. buf_set_u32(reg_params[1].value, 0, 32, address);
  1644. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
  1645. buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
  1646. buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
  1647. buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
  1648. buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
  1649. buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
  1650. buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
  1651. retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
  1652. write_algorithm->address,
  1653. write_algorithm->address + ((target_code_size) - 4),
  1654. 10000, arm_algo);
  1655. if (retval != ERROR_OK)
  1656. break;
  1657. status = buf_get_u32(reg_params[5].value, 0, 32);
  1658. if (status != 0x80) {
  1659. LOG_ERROR("flash write block failed status: 0x%" PRIx32, status);
  1660. retval = ERROR_FLASH_OPERATION_FAILED;
  1661. break;
  1662. }
  1663. buffer += thisrun_count;
  1664. address += thisrun_count;
  1665. count -= thisrun_count;
  1666. }
  1667. target_free_all_working_areas(target);
  1668. destroy_reg_param(&reg_params[0]);
  1669. destroy_reg_param(&reg_params[1]);
  1670. destroy_reg_param(&reg_params[2]);
  1671. destroy_reg_param(&reg_params[3]);
  1672. destroy_reg_param(&reg_params[4]);
  1673. destroy_reg_param(&reg_params[5]);
  1674. destroy_reg_param(&reg_params[6]);
  1675. destroy_reg_param(&reg_params[7]);
  1676. destroy_reg_param(&reg_params[8]);
  1677. destroy_reg_param(&reg_params[9]);
  1678. return retval;
  1679. }
  1680. static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1681. {
  1682. int retval;
  1683. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1684. struct target *target = bank->target;
  1685. cfi_intel_clear_status_register(bank);
  1686. retval = cfi_send_command(bank, 0x40, address);
  1687. if (retval != ERROR_OK)
  1688. return retval;
  1689. retval = target_write_memory(target, address, bank->bus_width, 1, word);
  1690. if (retval != ERROR_OK)
  1691. return retval;
  1692. uint8_t status;
  1693. retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
  1694. if (retval != 0x80) {
  1695. retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  1696. if (retval != ERROR_OK)
  1697. return retval;
  1698. LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
  1699. bank->base, address);
  1700. return ERROR_FLASH_OPERATION_FAILED;
  1701. }
  1702. return ERROR_OK;
  1703. }
  1704. static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
  1705. uint32_t wordcount, uint32_t address)
  1706. {
  1707. int retval;
  1708. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1709. struct target *target = bank->target;
  1710. /* Calculate buffer size and boundary mask
  1711. * buffersize is (buffer size per chip) * (number of chips)
  1712. * bufferwsize is buffersize in words */
  1713. uint32_t buffersize =
  1714. (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
  1715. uint32_t buffermask = buffersize-1;
  1716. uint32_t bufferwsize = buffersize / bank->bus_width;
  1717. /* Check for valid range */
  1718. if (address & buffermask) {
  1719. LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
  1720. " not aligned to 2^%d boundary",
  1721. bank->base, address, cfi_info->max_buf_write_size);
  1722. return ERROR_FLASH_OPERATION_FAILED;
  1723. }
  1724. /* Check for valid size */
  1725. if (wordcount > bufferwsize) {
  1726. LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
  1727. wordcount, buffersize);
  1728. return ERROR_FLASH_OPERATION_FAILED;
  1729. }
  1730. /* Write to flash buffer */
  1731. cfi_intel_clear_status_register(bank);
  1732. /* Initiate buffer operation _*/
  1733. retval = cfi_send_command(bank, 0xe8, address);
  1734. if (retval != ERROR_OK)
  1735. return retval;
  1736. uint8_t status;
  1737. retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
  1738. if (retval != ERROR_OK)
  1739. return retval;
  1740. if (status != 0x80) {
  1741. retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  1742. if (retval != ERROR_OK)
  1743. return retval;
  1744. LOG_ERROR(
  1745. "couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
  1746. bank->base,
  1747. address);
  1748. return ERROR_FLASH_OPERATION_FAILED;
  1749. }
  1750. /* Write buffer wordcount-1 and data words */
  1751. retval = cfi_send_command(bank, bufferwsize-1, address);
  1752. if (retval != ERROR_OK)
  1753. return retval;
  1754. retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word);
  1755. if (retval != ERROR_OK)
  1756. return retval;
  1757. /* Commit write operation */
  1758. retval = cfi_send_command(bank, 0xd0, address);
  1759. if (retval != ERROR_OK)
  1760. return retval;
  1761. retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
  1762. if (retval != ERROR_OK)
  1763. return retval;
  1764. if (status != 0x80) {
  1765. retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  1766. if (retval != ERROR_OK)
  1767. return retval;
  1768. LOG_ERROR("Buffer write at base 0x%" PRIx32
  1769. ", address 0x%" PRIx32 " failed.", bank->base, address);
  1770. return ERROR_FLASH_OPERATION_FAILED;
  1771. }
  1772. return ERROR_OK;
  1773. }
  1774. static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1775. {
  1776. int retval;
  1777. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1778. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1779. struct target *target = bank->target;
  1780. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
  1781. if (retval != ERROR_OK)
  1782. return retval;
  1783. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
  1784. if (retval != ERROR_OK)
  1785. return retval;
  1786. retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1));
  1787. if (retval != ERROR_OK)
  1788. return retval;
  1789. retval = target_write_memory(target, address, bank->bus_width, 1, word);
  1790. if (retval != ERROR_OK)
  1791. return retval;
  1792. if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK) {
  1793. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  1794. if (retval != ERROR_OK)
  1795. return retval;
  1796. LOG_ERROR("couldn't write word at base 0x%" PRIx32
  1797. ", address 0x%" PRIx32, bank->base, address);
  1798. return ERROR_FLASH_OPERATION_FAILED;
  1799. }
  1800. return ERROR_OK;
  1801. }
  1802. static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
  1803. uint32_t wordcount, uint32_t address)
  1804. {
  1805. int retval;
  1806. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1807. struct target *target = bank->target;
  1808. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1809. /* Calculate buffer size and boundary mask
  1810. * buffersize is (buffer size per chip) * (number of chips)
  1811. * bufferwsize is buffersize in words */
  1812. uint32_t buffersize =
  1813. (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
  1814. uint32_t buffermask = buffersize-1;
  1815. uint32_t bufferwsize = buffersize / bank->bus_width;
  1816. /* Check for valid range */
  1817. if (address & buffermask) {
  1818. LOG_ERROR("Write address at base 0x%" PRIx32
  1819. ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
  1820. bank->base, address, cfi_info->max_buf_write_size);
  1821. return ERROR_FLASH_OPERATION_FAILED;
  1822. }
  1823. /* Check for valid size */
  1824. if (wordcount > bufferwsize) {
  1825. LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
  1826. PRId32, wordcount, buffersize);
  1827. return ERROR_FLASH_OPERATION_FAILED;
  1828. }
  1829. /* Unlock */
  1830. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
  1831. if (retval != ERROR_OK)
  1832. return retval;
  1833. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
  1834. if (retval != ERROR_OK)
  1835. return retval;
  1836. /* Buffer load command */
  1837. retval = cfi_send_command(bank, 0x25, address);
  1838. if (retval != ERROR_OK)
  1839. return retval;
  1840. /* Write buffer wordcount-1 and data words */
  1841. retval = cfi_send_command(bank, bufferwsize-1, address);
  1842. if (retval != ERROR_OK)
  1843. return retval;
  1844. retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word);
  1845. if (retval != ERROR_OK)
  1846. return retval;
  1847. /* Commit write operation */
  1848. retval = cfi_send_command(bank, 0x29, address);
  1849. if (retval != ERROR_OK)
  1850. return retval;
  1851. if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK) {
  1852. retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  1853. if (retval != ERROR_OK)
  1854. return retval;
  1855. LOG_ERROR("couldn't write block at base 0x%" PRIx32
  1856. ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
  1857. bufferwsize);
  1858. return ERROR_FLASH_OPERATION_FAILED;
  1859. }
  1860. return ERROR_OK;
  1861. }
  1862. static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1863. {
  1864. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1865. switch (cfi_info->pri_id) {
  1866. case 1:
  1867. case 3:
  1868. return cfi_intel_write_word(bank, word, address);
  1869. break;
  1870. case 2:
  1871. return cfi_spansion_write_word(bank, word, address);
  1872. break;
  1873. default:
  1874. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  1875. break;
  1876. }
  1877. return ERROR_FLASH_OPERATION_FAILED;
  1878. }
  1879. static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
  1880. uint32_t wordcount, uint32_t address)
  1881. {
  1882. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1883. if (cfi_info->buf_write_timeout_typ == 0) {
  1884. /* buffer writes are not supported */
  1885. LOG_DEBUG("Buffer Writes Not Supported");
  1886. return ERROR_FLASH_OPER_UNSUPPORTED;
  1887. }
  1888. switch (cfi_info->pri_id) {
  1889. case 1:
  1890. case 3:
  1891. return cfi_intel_write_words(bank, word, wordcount, address);
  1892. break;
  1893. case 2:
  1894. return cfi_spansion_write_words(bank, word, wordcount, address);
  1895. break;
  1896. default:
  1897. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  1898. break;
  1899. }
  1900. return ERROR_FLASH_OPERATION_FAILED;
  1901. }
  1902. static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  1903. {
  1904. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1905. struct target *target = bank->target;
  1906. uint32_t address = bank->base + offset;
  1907. uint32_t read_p;
  1908. int align; /* number of unaligned bytes */
  1909. uint8_t current_word[CFI_MAX_BUS_WIDTH];
  1910. int i;
  1911. int retval;
  1912. LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
  1913. (int)count, (unsigned)offset);
  1914. if (bank->target->state != TARGET_HALTED) {
  1915. LOG_ERROR("Target not halted");
  1916. return ERROR_TARGET_NOT_HALTED;
  1917. }
  1918. if (offset + count > bank->size)
  1919. return ERROR_FLASH_DST_OUT_OF_BANK;
  1920. if (cfi_info->qry[0] != 'Q')
  1921. return ERROR_FLASH_BANK_NOT_PROBED;
  1922. /* start at the first byte of the first word (bus_width size) */
  1923. read_p = address & ~(bank->bus_width - 1);
  1924. align = address - read_p;
  1925. if (align != 0) {
  1926. LOG_INFO("Fixup %d unaligned read head bytes", align);
  1927. /* read a complete word from flash */
  1928. retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word);
  1929. if (retval != ERROR_OK)
  1930. return retval;
  1931. /* take only bytes we need */
  1932. for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
  1933. *buffer++ = current_word[i];
  1934. read_p += bank->bus_width;
  1935. }
  1936. align = count / bank->bus_width;
  1937. if (align) {
  1938. retval = target_read_memory(target, read_p, bank->bus_width, align, buffer);
  1939. if (retval != ERROR_OK)
  1940. return retval;
  1941. read_p += align * bank->bus_width;
  1942. buffer += align * bank->bus_width;
  1943. count -= align * bank->bus_width;
  1944. }
  1945. if (count) {
  1946. LOG_INFO("Fixup %d unaligned read tail bytes", count);
  1947. /* read a complete word from flash */
  1948. retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word);
  1949. if (retval != ERROR_OK)
  1950. return retval;
  1951. /* take only bytes we need */
  1952. for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
  1953. *buffer++ = current_word[i];
  1954. }
  1955. return ERROR_OK;
  1956. }
  1957. static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  1958. {
  1959. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1960. struct target *target = bank->target;
  1961. uint32_t address = bank->base + offset; /* address of first byte to be programmed */
  1962. uint32_t write_p;
  1963. int align; /* number of unaligned bytes */
  1964. int blk_count; /* number of bus_width bytes for block copy */
  1965. uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being
  1966. *programmed */
  1967. int i;
  1968. int retval;
  1969. if (bank->target->state != TARGET_HALTED) {
  1970. LOG_ERROR("Target not halted");
  1971. return ERROR_TARGET_NOT_HALTED;
  1972. }
  1973. if (offset + count > bank->size)
  1974. return ERROR_FLASH_DST_OUT_OF_BANK;
  1975. if (cfi_info->qry[0] != 'Q')
  1976. return ERROR_FLASH_BANK_NOT_PROBED;
  1977. /* start at the first byte of the first word (bus_width size) */
  1978. write_p = address & ~(bank->bus_width - 1);
  1979. align = address - write_p;
  1980. if (align != 0) {
  1981. LOG_INFO("Fixup %d unaligned head bytes", align);
  1982. /* read a complete word from flash */
  1983. retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word);
  1984. if (retval != ERROR_OK)
  1985. return retval;
  1986. /* replace only bytes that must be written */
  1987. for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
  1988. current_word[i] = *buffer++;
  1989. retval = cfi_write_word(bank, current_word, write_p);
  1990. if (retval != ERROR_OK)
  1991. return retval;
  1992. write_p += bank->bus_width;
  1993. }
  1994. /* handle blocks of bus_size aligned bytes */
  1995. blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
  1996. switch (cfi_info->pri_id) {
  1997. /* try block writes (fails without working area) */
  1998. case 1:
  1999. case 3:
  2000. retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
  2001. break;
  2002. case 2:
  2003. retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
  2004. break;
  2005. default:
  2006. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2007. retval = ERROR_FLASH_OPERATION_FAILED;
  2008. break;
  2009. }
  2010. if (retval == ERROR_OK) {
  2011. /* Increment pointers and decrease count on succesful block write */
  2012. buffer += blk_count;
  2013. write_p += blk_count;
  2014. count -= blk_count;
  2015. } else {
  2016. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  2017. /* Calculate buffer size and boundary mask
  2018. * buffersize is (buffer size per chip) * (number of chips)
  2019. * bufferwsize is buffersize in words */
  2020. uint32_t buffersize =
  2021. (1UL <<
  2022. cfi_info->max_buf_write_size) *
  2023. (bank->bus_width / bank->chip_width);
  2024. uint32_t buffermask = buffersize-1;
  2025. uint32_t bufferwsize = buffersize / bank->bus_width;
  2026. /* fall back to memory writes */
  2027. while (count >= (uint32_t)bank->bus_width) {
  2028. int fallback;
  2029. if ((write_p & 0xff) == 0) {
  2030. LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
  2031. PRIx32 " bytes remaining", write_p, count);
  2032. }
  2033. fallback = 1;
  2034. if ((bufferwsize > 0) && (count >= buffersize) &&
  2035. !(write_p & buffermask)) {
  2036. retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
  2037. if (retval == ERROR_OK) {
  2038. buffer += buffersize;
  2039. write_p += buffersize;
  2040. count -= buffersize;
  2041. fallback = 0;
  2042. } else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
  2043. return retval;
  2044. }
  2045. /* try the slow way? */
  2046. if (fallback) {
  2047. for (i = 0; i < bank->bus_width; i++)
  2048. current_word[i] = *buffer++;
  2049. retval = cfi_write_word(bank, current_word, write_p);
  2050. if (retval != ERROR_OK)
  2051. return retval;
  2052. write_p += bank->bus_width;
  2053. count -= bank->bus_width;
  2054. }
  2055. }
  2056. } else
  2057. return retval;
  2058. }
  2059. /* return to read array mode, so we can read from flash again for padding */
  2060. retval = cfi_reset(bank);
  2061. if (retval != ERROR_OK)
  2062. return retval;
  2063. /* handle unaligned tail bytes */
  2064. if (count > 0) {
  2065. LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
  2066. /* read a complete word from flash */
  2067. retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word);
  2068. if (retval != ERROR_OK)
  2069. return retval;
  2070. /* replace only bytes that must be written */
  2071. for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
  2072. current_word[i] = *buffer++;
  2073. retval = cfi_write_word(bank, current_word, write_p);
  2074. if (retval != ERROR_OK)
  2075. return retval;
  2076. }
  2077. /* return to read array mode */
  2078. return cfi_reset(bank);
  2079. }
  2080. static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
  2081. {
  2082. (void) param;
  2083. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2084. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2085. pri_ext->_reversed_geometry = 1;
  2086. }
  2087. static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
  2088. {
  2089. int i;
  2090. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2091. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2092. (void) param;
  2093. if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3)) {
  2094. LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
  2095. for (i = 0; i < cfi_info->num_erase_regions / 2; i++) {
  2096. int j = (cfi_info->num_erase_regions - 1) - i;
  2097. uint32_t swap;
  2098. swap = cfi_info->erase_region_info[i];
  2099. cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
  2100. cfi_info->erase_region_info[j] = swap;
  2101. }
  2102. }
  2103. }
  2104. static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
  2105. {
  2106. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2107. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2108. struct cfi_unlock_addresses *unlock_addresses = param;
  2109. pri_ext->_unlock1 = unlock_addresses->unlock1;
  2110. pri_ext->_unlock2 = unlock_addresses->unlock2;
  2111. }
  2112. static int cfi_query_string(struct flash_bank *bank, int address)
  2113. {
  2114. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2115. int retval;
  2116. retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address));
  2117. if (retval != ERROR_OK)
  2118. return retval;
  2119. retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
  2120. if (retval != ERROR_OK)
  2121. return retval;
  2122. retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
  2123. if (retval != ERROR_OK)
  2124. return retval;
  2125. retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
  2126. if (retval != ERROR_OK)
  2127. return retval;
  2128. LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
  2129. cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
  2130. if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y')) {
  2131. retval = cfi_reset(bank);
  2132. if (retval != ERROR_OK)
  2133. return retval;
  2134. LOG_ERROR("Could not probe bank: no QRY");
  2135. return ERROR_FLASH_BANK_INVALID;
  2136. }
  2137. return ERROR_OK;
  2138. }
  2139. static int cfi_probe(struct flash_bank *bank)
  2140. {
  2141. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2142. struct target *target = bank->target;
  2143. int num_sectors = 0;
  2144. int i;
  2145. int sector = 0;
  2146. uint32_t unlock1 = 0x555;
  2147. uint32_t unlock2 = 0x2aa;
  2148. int retval;
  2149. uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
  2150. if (bank->target->state != TARGET_HALTED) {
  2151. LOG_ERROR("Target not halted");
  2152. return ERROR_TARGET_NOT_HALTED;
  2153. }
  2154. cfi_info->probed = 0;
  2155. cfi_info->num_erase_regions = 0;
  2156. if (bank->sectors) {
  2157. free(bank->sectors);
  2158. bank->sectors = NULL;
  2159. }
  2160. if (cfi_info->erase_region_info) {
  2161. free(cfi_info->erase_region_info);
  2162. cfi_info->erase_region_info = NULL;
  2163. }
  2164. /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
  2165. * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
  2166. */
  2167. if (cfi_info->jedec_probe) {
  2168. unlock1 = 0x5555;
  2169. unlock2 = 0x2aaa;
  2170. }
  2171. /* switch to read identifier codes mode ("AUTOSELECT") */
  2172. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1));
  2173. if (retval != ERROR_OK)
  2174. return retval;
  2175. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2));
  2176. if (retval != ERROR_OK)
  2177. return retval;
  2178. retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1));
  2179. if (retval != ERROR_OK)
  2180. return retval;
  2181. retval = target_read_memory(target, flash_address(bank, 0, 0x00),
  2182. bank->bus_width, 1, value_buf0);
  2183. if (retval != ERROR_OK)
  2184. return retval;
  2185. retval = target_read_memory(target, flash_address(bank, 0, 0x01),
  2186. bank->bus_width, 1, value_buf1);
  2187. if (retval != ERROR_OK)
  2188. return retval;
  2189. switch (bank->chip_width) {
  2190. case 1:
  2191. cfi_info->manufacturer = *value_buf0;
  2192. cfi_info->device_id = *value_buf1;
  2193. break;
  2194. case 2:
  2195. cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
  2196. cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
  2197. break;
  2198. case 4:
  2199. cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
  2200. cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
  2201. break;
  2202. default:
  2203. LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory",
  2204. bank->chip_width);
  2205. return ERROR_FLASH_OPERATION_FAILED;
  2206. }
  2207. LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
  2208. cfi_info->manufacturer, cfi_info->device_id);
  2209. /* switch back to read array mode */
  2210. retval = cfi_reset(bank);
  2211. if (retval != ERROR_OK)
  2212. return retval;
  2213. /* check device/manufacturer ID for known non-CFI flashes. */
  2214. cfi_fixup_non_cfi(bank);
  2215. /* query only if this is a CFI compatible flash,
  2216. * otherwise the relevant info has already been filled in
  2217. */
  2218. if (cfi_info->not_cfi == 0) {
  2219. /* enter CFI query mode
  2220. * according to JEDEC Standard No. 68.01,
  2221. * a single bus sequence with address = 0x55, data = 0x98 should put
  2222. * the device into CFI query mode.
  2223. *
  2224. * SST flashes clearly violate this, and we will consider them incompatible for now
  2225. */
  2226. retval = cfi_query_string(bank, 0x55);
  2227. if (retval != ERROR_OK) {
  2228. /*
  2229. * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
  2230. * be harmless enough:
  2231. *
  2232. * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
  2233. */
  2234. LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
  2235. retval = cfi_query_string(bank, 0x555);
  2236. }
  2237. if (retval != ERROR_OK)
  2238. return retval;
  2239. retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
  2240. if (retval != ERROR_OK)
  2241. return retval;
  2242. retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
  2243. if (retval != ERROR_OK)
  2244. return retval;
  2245. retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
  2246. if (retval != ERROR_OK)
  2247. return retval;
  2248. retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
  2249. if (retval != ERROR_OK)
  2250. return retval;
  2251. LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
  2252. "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
  2253. cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
  2254. cfi_info->alt_id, cfi_info->alt_addr);
  2255. retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
  2256. if (retval != ERROR_OK)
  2257. return retval;
  2258. retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
  2259. if (retval != ERROR_OK)
  2260. return retval;
  2261. retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
  2262. if (retval != ERROR_OK)
  2263. return retval;
  2264. retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
  2265. if (retval != ERROR_OK)
  2266. return retval;
  2267. retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
  2268. if (retval != ERROR_OK)
  2269. return retval;
  2270. retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
  2271. if (retval != ERROR_OK)
  2272. return retval;
  2273. retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
  2274. if (retval != ERROR_OK)
  2275. return retval;
  2276. retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
  2277. if (retval != ERROR_OK)
  2278. return retval;
  2279. retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
  2280. if (retval != ERROR_OK)
  2281. return retval;
  2282. retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
  2283. if (retval != ERROR_OK)
  2284. return retval;
  2285. retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
  2286. if (retval != ERROR_OK)
  2287. return retval;
  2288. retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
  2289. if (retval != ERROR_OK)
  2290. return retval;
  2291. uint8_t data;
  2292. retval = cfi_query_u8(bank, 0, 0x27, &data);
  2293. if (retval != ERROR_OK)
  2294. return retval;
  2295. cfi_info->dev_size = 1 << data;
  2296. retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
  2297. if (retval != ERROR_OK)
  2298. return retval;
  2299. retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
  2300. if (retval != ERROR_OK)
  2301. return retval;
  2302. retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
  2303. if (retval != ERROR_OK)
  2304. return retval;
  2305. LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
  2306. cfi_info->dev_size, cfi_info->interface_desc,
  2307. (1 << cfi_info->max_buf_write_size));
  2308. if (cfi_info->num_erase_regions) {
  2309. cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
  2310. * cfi_info->num_erase_regions);
  2311. for (i = 0; i < cfi_info->num_erase_regions; i++) {
  2312. retval = cfi_query_u32(bank,
  2313. 0,
  2314. 0x2d + (4 * i),
  2315. &cfi_info->erase_region_info[i]);
  2316. if (retval != ERROR_OK)
  2317. return retval;
  2318. LOG_DEBUG(
  2319. "erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
  2320. i,
  2321. (cfi_info->erase_region_info[i] & 0xffff) + 1,
  2322. (cfi_info->erase_region_info[i] >> 16) * 256);
  2323. }
  2324. } else
  2325. cfi_info->erase_region_info = NULL;
  2326. /* We need to read the primary algorithm extended query table before calculating
  2327. * the sector layout to be able to apply fixups
  2328. */
  2329. switch (cfi_info->pri_id) {
  2330. /* Intel command set (standard and extended) */
  2331. case 0x0001:
  2332. case 0x0003:
  2333. cfi_read_intel_pri_ext(bank);
  2334. break;
  2335. /* AMD/Spansion, Atmel, ... command set */
  2336. case 0x0002:
  2337. cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /*
  2338. *default
  2339. *for
  2340. *all
  2341. *CFI
  2342. *flashs
  2343. **/
  2344. cfi_read_0002_pri_ext(bank);
  2345. break;
  2346. default:
  2347. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2348. break;
  2349. }
  2350. /* return to read array mode
  2351. * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
  2352. */
  2353. retval = cfi_reset(bank);
  2354. if (retval != ERROR_OK)
  2355. return retval;
  2356. } /* end CFI case */
  2357. LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
  2358. (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
  2359. (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
  2360. (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
  2361. (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
  2362. LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
  2363. "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
  2364. 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
  2365. 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
  2366. LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
  2367. "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
  2368. (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
  2369. (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
  2370. (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
  2371. (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
  2372. /* convert timeouts to real values in ms */
  2373. cfi_info->word_write_timeout = DIV_ROUND_UP((1L << cfi_info->word_write_timeout_typ) *
  2374. (1L << cfi_info->word_write_timeout_max), 1000);
  2375. cfi_info->buf_write_timeout = DIV_ROUND_UP((1L << cfi_info->buf_write_timeout_typ) *
  2376. (1L << cfi_info->buf_write_timeout_max), 1000);
  2377. cfi_info->block_erase_timeout = (1L << cfi_info->block_erase_timeout_typ) *
  2378. (1L << cfi_info->block_erase_timeout_max);
  2379. cfi_info->chip_erase_timeout = (1L << cfi_info->chip_erase_timeout_typ) *
  2380. (1L << cfi_info->chip_erase_timeout_max);
  2381. LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
  2382. "block erase timeout: %u ms, chip erase timeout: %u ms",
  2383. cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
  2384. cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
  2385. /* apply fixups depending on the primary command set */
  2386. switch (cfi_info->pri_id) {
  2387. /* Intel command set (standard and extended) */
  2388. case 0x0001:
  2389. case 0x0003:
  2390. cfi_fixup(bank, cfi_0001_fixups);
  2391. break;
  2392. /* AMD/Spansion, Atmel, ... command set */
  2393. case 0x0002:
  2394. cfi_fixup(bank, cfi_0002_fixups);
  2395. break;
  2396. default:
  2397. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2398. break;
  2399. }
  2400. if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size) {
  2401. LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
  2402. " size flash was found", bank->size, cfi_info->dev_size);
  2403. }
  2404. if (cfi_info->num_erase_regions == 0) {
  2405. /* a device might have only one erase block, spanning the whole device */
  2406. bank->num_sectors = 1;
  2407. bank->sectors = malloc(sizeof(struct flash_sector));
  2408. bank->sectors[sector].offset = 0x0;
  2409. bank->sectors[sector].size = bank->size;
  2410. bank->sectors[sector].is_erased = -1;
  2411. bank->sectors[sector].is_protected = -1;
  2412. } else {
  2413. uint32_t offset = 0;
  2414. for (i = 0; i < cfi_info->num_erase_regions; i++)
  2415. num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
  2416. bank->num_sectors = num_sectors;
  2417. bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
  2418. for (i = 0; i < cfi_info->num_erase_regions; i++) {
  2419. uint32_t j;
  2420. for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++) {
  2421. bank->sectors[sector].offset = offset;
  2422. bank->sectors[sector].size =
  2423. ((cfi_info->erase_region_info[i] >> 16) * 256)
  2424. * bank->bus_width / bank->chip_width;
  2425. offset += bank->sectors[sector].size;
  2426. bank->sectors[sector].is_erased = -1;
  2427. bank->sectors[sector].is_protected = -1;
  2428. sector++;
  2429. }
  2430. }
  2431. if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) {
  2432. LOG_WARNING(
  2433. "CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
  2434. (cfi_info->dev_size * bank->bus_width / bank->chip_width),
  2435. offset);
  2436. }
  2437. }
  2438. cfi_info->probed = 1;
  2439. return ERROR_OK;
  2440. }
  2441. static int cfi_auto_probe(struct flash_bank *bank)
  2442. {
  2443. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2444. if (cfi_info->probed)
  2445. return ERROR_OK;
  2446. return cfi_probe(bank);
  2447. }
  2448. static int cfi_intel_protect_check(struct flash_bank *bank)
  2449. {
  2450. int retval;
  2451. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2452. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  2453. int i;
  2454. /* check if block lock bits are supported on this device */
  2455. if (!(pri_ext->blk_status_reg_mask & 0x1))
  2456. return ERROR_FLASH_OPERATION_FAILED;
  2457. retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55));
  2458. if (retval != ERROR_OK)
  2459. return retval;
  2460. for (i = 0; i < bank->num_sectors; i++) {
  2461. uint8_t block_status;
  2462. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  2463. if (retval != ERROR_OK)
  2464. return retval;
  2465. if (block_status & 1)
  2466. bank->sectors[i].is_protected = 1;
  2467. else
  2468. bank->sectors[i].is_protected = 0;
  2469. }
  2470. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  2471. }
  2472. static int cfi_spansion_protect_check(struct flash_bank *bank)
  2473. {
  2474. int retval;
  2475. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2476. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2477. int i;
  2478. retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
  2479. if (retval != ERROR_OK)
  2480. return retval;
  2481. retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
  2482. if (retval != ERROR_OK)
  2483. return retval;
  2484. retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1));
  2485. if (retval != ERROR_OK)
  2486. return retval;
  2487. for (i = 0; i < bank->num_sectors; i++) {
  2488. uint8_t block_status;
  2489. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  2490. if (retval != ERROR_OK)
  2491. return retval;
  2492. if (block_status & 1)
  2493. bank->sectors[i].is_protected = 1;
  2494. else
  2495. bank->sectors[i].is_protected = 0;
  2496. }
  2497. return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  2498. }
  2499. static int cfi_protect_check(struct flash_bank *bank)
  2500. {
  2501. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2502. if (bank->target->state != TARGET_HALTED) {
  2503. LOG_ERROR("Target not halted");
  2504. return ERROR_TARGET_NOT_HALTED;
  2505. }
  2506. if (cfi_info->qry[0] != 'Q')
  2507. return ERROR_FLASH_BANK_NOT_PROBED;
  2508. switch (cfi_info->pri_id) {
  2509. case 1:
  2510. case 3:
  2511. return cfi_intel_protect_check(bank);
  2512. break;
  2513. case 2:
  2514. return cfi_spansion_protect_check(bank);
  2515. break;
  2516. default:
  2517. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2518. break;
  2519. }
  2520. return ERROR_OK;
  2521. }
  2522. static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
  2523. {
  2524. int printed;
  2525. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2526. if (cfi_info->qry[0] == 0xff) {
  2527. snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
  2528. return ERROR_OK;
  2529. }
  2530. if (cfi_info->not_cfi == 0)
  2531. printed = snprintf(buf, buf_size, "\nCFI flash: ");
  2532. else
  2533. printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
  2534. buf += printed;
  2535. buf_size -= printed;
  2536. printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
  2537. cfi_info->manufacturer, cfi_info->device_id);
  2538. buf += printed;
  2539. buf_size -= printed;
  2540. printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
  2541. "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
  2542. cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
  2543. cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
  2544. buf += printed;
  2545. buf_size -= printed;
  2546. printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
  2547. "Vpp min: %u.%x, Vpp max: %u.%x\n",
  2548. (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
  2549. (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
  2550. (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
  2551. (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
  2552. buf += printed;
  2553. buf_size -= printed;
  2554. printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
  2555. "typ. buf write timeout: %u us, "
  2556. "typ. block erase timeout: %u ms, "
  2557. "typ. chip erase timeout: %u ms\n",
  2558. 1 << cfi_info->word_write_timeout_typ,
  2559. 1 << cfi_info->buf_write_timeout_typ,
  2560. 1 << cfi_info->block_erase_timeout_typ,
  2561. 1 << cfi_info->chip_erase_timeout_typ);
  2562. buf += printed;
  2563. buf_size -= printed;
  2564. printed = snprintf(buf,
  2565. buf_size,
  2566. "max. word write timeout: %u us, "
  2567. "max. buf write timeout: %u us, max. "
  2568. "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
  2569. (1 <<
  2570. cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
  2571. (1 <<
  2572. cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
  2573. (1 <<
  2574. cfi_info->block_erase_timeout_max) *
  2575. (1 << cfi_info->block_erase_timeout_typ),
  2576. (1 <<
  2577. cfi_info->chip_erase_timeout_max) *
  2578. (1 << cfi_info->chip_erase_timeout_typ));
  2579. buf += printed;
  2580. buf_size -= printed;
  2581. printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
  2582. "max buffer write size: 0x%x\n",
  2583. cfi_info->dev_size,
  2584. cfi_info->interface_desc,
  2585. 1 << cfi_info->max_buf_write_size);
  2586. buf += printed;
  2587. buf_size -= printed;
  2588. switch (cfi_info->pri_id) {
  2589. case 1:
  2590. case 3:
  2591. cfi_intel_info(bank, buf, buf_size);
  2592. break;
  2593. case 2:
  2594. cfi_spansion_info(bank, buf, buf_size);
  2595. break;
  2596. default:
  2597. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2598. break;
  2599. }
  2600. return ERROR_OK;
  2601. }
  2602. static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param)
  2603. {
  2604. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2605. /* disable write buffer for M29W128G */
  2606. cfi_info->buf_write_timeout_typ = 0;
  2607. }
  2608. struct flash_driver cfi_flash = {
  2609. .name = "cfi",
  2610. .flash_bank_command = cfi_flash_bank_command,
  2611. .erase = cfi_erase,
  2612. .protect = cfi_protect,
  2613. .write = cfi_write,
  2614. .read = cfi_read,
  2615. .probe = cfi_probe,
  2616. .auto_probe = cfi_auto_probe,
  2617. /* FIXME: access flash at bus_width size */
  2618. .erase_check = default_flash_blank_check,
  2619. .protect_check = cfi_protect_check,
  2620. .info = get_cfi_info,
  2621. };