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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Andreas Fritiofson *
  9. * andreas.fritiofson@gmail.com *
  10. * *
  11. * Copyright (C) 2013 by Roman Dmitrienko *
  12. * me@iamroman.org *
  13. *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  28. ***************************************************************************/
  29. #ifdef HAVE_CONFIG_H
  30. #include "config.h"
  31. #endif
  32. #include "imp.h"
  33. #include <helper/binarybuffer.h>
  34. #include <target/algorithm.h>
  35. #include <target/armv7m.h>
  36. #include <target/cortex_m.h>
  37. /* keep family IDs in decimal */
  38. #define EFM_FAMILY_ID_GECKO 71
  39. #define EFM_FAMILY_ID_GIANT_GECKO 72
  40. #define EFM_FAMILY_ID_TINY_GECKO 73
  41. #define EFM_FAMILY_ID_LEOPARD_GECKO 74
  42. #define EFM32_FLASH_ERASE_TMO 100
  43. #define EFM32_FLASH_WDATAREADY_TMO 100
  44. #define EFM32_FLASH_WRITE_TMO 100
  45. /* size in bytes, not words; must fit all Gecko devices */
  46. #define LOCKBITS_PAGE_SZ 512
  47. #define EFM32_MSC_INFO_BASE 0x0fe00000
  48. #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
  49. #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
  50. #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
  51. /* PAGE_SIZE is only present in Leopard and Giant Gecko MCUs */
  52. #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
  53. #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
  54. #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
  55. #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
  56. #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
  57. #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
  58. #define EFM32_MSC_REGBASE 0x400c0000
  59. #define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
  60. #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
  61. #define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
  62. #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  63. #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  64. #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  65. #define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
  66. #define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
  67. #define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
  68. #define EFM32_MSC_STATUS_BUSY_MASK 0x1
  69. #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
  70. #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
  71. #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  72. #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  73. #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  74. #define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
  75. #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
  76. struct efm32x_flash_bank {
  77. int probed;
  78. uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
  79. };
  80. struct efm32_info {
  81. uint16_t flash_sz_kib;
  82. uint16_t ram_sz_kib;
  83. uint16_t part_num;
  84. uint8_t part_family;
  85. uint8_t prod_rev;
  86. uint16_t page_size;
  87. };
  88. static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
  89. uint32_t offset, uint32_t count);
  90. static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
  91. {
  92. return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
  93. }
  94. static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
  95. {
  96. return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
  97. }
  98. static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
  99. {
  100. return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
  101. }
  102. static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
  103. {
  104. return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
  105. }
  106. static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
  107. {
  108. return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
  109. }
  110. static int efm32x_read_info(struct flash_bank *bank,
  111. struct efm32_info *efm32_info)
  112. {
  113. int ret;
  114. uint32_t cpuid = 0;
  115. memset(efm32_info, 0, sizeof(struct efm32_info));
  116. ret = target_read_u32(bank->target, CPUID, &cpuid);
  117. if (ERROR_OK != ret)
  118. return ret;
  119. if (((cpuid >> 4) & 0xfff) == 0xc23) {
  120. /* Cortex M3 device */
  121. } else {
  122. LOG_ERROR("Target is not CortexM3");
  123. return ERROR_FAIL;
  124. }
  125. ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
  126. if (ERROR_OK != ret)
  127. return ret;
  128. ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
  129. if (ERROR_OK != ret)
  130. return ret;
  131. ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
  132. if (ERROR_OK != ret)
  133. return ret;
  134. ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
  135. if (ERROR_OK != ret)
  136. return ret;
  137. ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
  138. if (ERROR_OK != ret)
  139. return ret;
  140. if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
  141. EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
  142. efm32_info->page_size = 512;
  143. else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
  144. EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
  145. if (efm32_info->prod_rev >= 18) {
  146. uint8_t pg_size = 0;
  147. ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
  148. &pg_size);
  149. if (ERROR_OK != ret)
  150. return ret;
  151. efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
  152. } else {
  153. /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
  154. for MCUs with PROD_REV < 18 */
  155. if (efm32_info->flash_sz_kib < 512)
  156. efm32_info->page_size = 2048;
  157. else
  158. efm32_info->page_size = 4096;
  159. }
  160. if ((2048 != efm32_info->page_size) &&
  161. (4096 != efm32_info->page_size)) {
  162. LOG_ERROR("Invalid page size %u", efm32_info->page_size);
  163. return ERROR_FAIL;
  164. }
  165. } else {
  166. LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
  167. return ERROR_FAIL;
  168. }
  169. return ERROR_OK;
  170. }
  171. /* flash bank efm32 <base> <size> 0 0 <target#>
  172. */
  173. FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
  174. {
  175. struct efm32x_flash_bank *efm32x_info;
  176. if (CMD_ARGC < 6)
  177. return ERROR_COMMAND_SYNTAX_ERROR;
  178. efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
  179. bank->driver_priv = efm32x_info;
  180. efm32x_info->probed = 0;
  181. memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
  182. return ERROR_OK;
  183. }
  184. /* set or reset given bits in a register */
  185. static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
  186. uint32_t bitmask, int set)
  187. {
  188. int ret = 0;
  189. uint32_t reg_val = 0;
  190. ret = target_read_u32(bank->target, reg, &reg_val);
  191. if (ERROR_OK != ret)
  192. return ret;
  193. if (set)
  194. reg_val |= bitmask;
  195. else
  196. reg_val &= ~bitmask;
  197. return target_write_u32(bank->target, reg, reg_val);
  198. }
  199. static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
  200. {
  201. return efm32x_set_reg_bits(bank, EFM32_MSC_WRITECTRL,
  202. EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
  203. }
  204. static int efm32x_msc_lock(struct flash_bank *bank, int lock)
  205. {
  206. return target_write_u32(bank->target, EFM32_MSC_LOCK,
  207. (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
  208. }
  209. static int efm32x_wait_status(struct flash_bank *bank, int timeout,
  210. uint32_t wait_mask, int wait_for_set)
  211. {
  212. int ret = 0;
  213. uint32_t status = 0;
  214. while (1) {
  215. ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
  216. if (ERROR_OK != ret)
  217. break;
  218. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  219. if (((status & wait_mask) == 0) && (0 == wait_for_set))
  220. break;
  221. else if (((status & wait_mask) != 0) && wait_for_set)
  222. break;
  223. if (timeout-- <= 0) {
  224. LOG_ERROR("timed out waiting for MSC status");
  225. return ERROR_FAIL;
  226. }
  227. alive_sleep(1);
  228. }
  229. if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
  230. LOG_WARNING("page erase was aborted");
  231. return ret;
  232. }
  233. static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
  234. {
  235. /* this function DOES NOT set WREN; must be set already */
  236. /* 1. write address to ADDRB
  237. 2. write LADDRIM
  238. 3. check status (INVADDR, LOCKED)
  239. 4. write ERASEPAGE
  240. 5. wait until !STATUS_BUSY
  241. */
  242. int ret = 0;
  243. uint32_t status = 0;
  244. LOG_DEBUG("erasing flash page at 0x%08x", addr);
  245. ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
  246. if (ERROR_OK != ret)
  247. return ret;
  248. ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
  249. EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
  250. if (ERROR_OK != ret)
  251. return ret;
  252. ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
  253. if (ERROR_OK != ret)
  254. return ret;
  255. LOG_DEBUG("status 0x%x", status);
  256. if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
  257. LOG_ERROR("Page is locked");
  258. return ERROR_FAIL;
  259. } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
  260. LOG_ERROR("Invalid address 0x%x", addr);
  261. return ERROR_FAIL;
  262. }
  263. ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
  264. EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
  265. if (ERROR_OK != ret)
  266. return ret;
  267. return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
  268. EFM32_MSC_STATUS_BUSY_MASK, 0);
  269. }
  270. static int efm32x_erase(struct flash_bank *bank, int first, int last)
  271. {
  272. struct target *target = bank->target;
  273. int i = 0;
  274. int ret = 0;
  275. if (TARGET_HALTED != target->state) {
  276. LOG_ERROR("Target not halted");
  277. return ERROR_TARGET_NOT_HALTED;
  278. }
  279. efm32x_msc_lock(bank, 0);
  280. ret = efm32x_set_wren(bank, 1);
  281. if (ERROR_OK != ret) {
  282. LOG_ERROR("Failed to enable MSC write");
  283. return ret;
  284. }
  285. for (i = first; i <= last; i++) {
  286. ret = efm32x_erase_page(bank, bank->sectors[i].offset);
  287. if (ERROR_OK != ret)
  288. LOG_ERROR("Failed to erase page %d", i);
  289. }
  290. ret = efm32x_set_wren(bank, 0);
  291. efm32x_msc_lock(bank, 1);
  292. return ret;
  293. }
  294. static int efm32x_read_lock_data(struct flash_bank *bank)
  295. {
  296. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  297. struct target *target = bank->target;
  298. int i = 0;
  299. int data_size = 0;
  300. uint32_t *ptr = NULL;
  301. int ret = 0;
  302. assert(!(bank->num_sectors & 0x1f));
  303. data_size = bank->num_sectors / 8; /* number of data bytes */
  304. data_size /= 4; /* ...and data dwords */
  305. ptr = efm32x_info->lb_page;
  306. for (i = 0; i < data_size; i++, ptr++) {
  307. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
  308. if (ERROR_OK != ret) {
  309. LOG_ERROR("Failed to read PLW %d", i);
  310. return ret;
  311. }
  312. }
  313. /* also, read ULW, DLW and MLW */
  314. /* ULW, word 126 */
  315. ptr = efm32x_info->lb_page + 126;
  316. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
  317. if (ERROR_OK != ret) {
  318. LOG_ERROR("Failed to read ULW");
  319. return ret;
  320. }
  321. /* DLW, word 127 */
  322. ptr = efm32x_info->lb_page + 127;
  323. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
  324. if (ERROR_OK != ret) {
  325. LOG_ERROR("Failed to read DLW");
  326. return ret;
  327. }
  328. /* MLW, word 125, present in GG and LG */
  329. ptr = efm32x_info->lb_page + 125;
  330. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
  331. if (ERROR_OK != ret) {
  332. LOG_ERROR("Failed to read MLW");
  333. return ret;
  334. }
  335. return ERROR_OK;
  336. }
  337. static int efm32x_write_lock_data(struct flash_bank *bank)
  338. {
  339. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  340. int ret = 0;
  341. ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
  342. if (ERROR_OK != ret) {
  343. LOG_ERROR("Failed to erase LB page");
  344. return ret;
  345. }
  346. return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
  347. LOCKBITS_PAGE_SZ);
  348. }
  349. static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
  350. {
  351. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  352. uint32_t dw = efm32x_info->lb_page[page >> 5];
  353. uint32_t mask = 0;
  354. mask = 1 << (page & 0x1f);
  355. return (dw & mask) ? 0 : 1;
  356. }
  357. static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
  358. {
  359. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  360. uint32_t *dw = &efm32x_info->lb_page[page >> 5];
  361. uint32_t mask = 0;
  362. mask = 1 << (page & 0x1f);
  363. if (!set)
  364. *dw |= mask;
  365. else
  366. *dw &= ~mask;
  367. return ERROR_OK;
  368. }
  369. static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
  370. {
  371. struct target *target = bank->target;
  372. int i = 0;
  373. int ret = 0;
  374. if (!set) {
  375. LOG_ERROR("Erase device data to reset page locks");
  376. return ERROR_FAIL;
  377. }
  378. if (target->state != TARGET_HALTED) {
  379. LOG_ERROR("Target not halted");
  380. return ERROR_TARGET_NOT_HALTED;
  381. }
  382. for (i = first; i <= last; i++) {
  383. ret = efm32x_set_page_lock(bank, i, set);
  384. if (ERROR_OK != ret) {
  385. LOG_ERROR("Failed to set lock on page %d", i);
  386. return ret;
  387. }
  388. }
  389. ret = efm32x_write_lock_data(bank);
  390. if (ERROR_OK != ret) {
  391. LOG_ERROR("Failed to write LB page");
  392. return ret;
  393. }
  394. return ERROR_OK;
  395. }
  396. static int efm32x_write_block(struct flash_bank *bank, uint8_t *buf,
  397. uint32_t offset, uint32_t count)
  398. {
  399. struct target *target = bank->target;
  400. uint32_t buffer_size = 16384;
  401. struct working_area *write_algorithm;
  402. struct working_area *source;
  403. uint32_t address = bank->base + offset;
  404. struct reg_param reg_params[5];
  405. struct armv7m_algorithm armv7m_info;
  406. int ret = ERROR_OK;
  407. /* see contrib/loaders/flash/efm32.S for src */
  408. static const uint8_t efm32x_flash_write_code[] = {
  409. /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
  410. /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
  411. /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
  412. /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
  413. /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
  414. /* #define EFM32_MSC_LOCK_OFFSET 0x03c */
  415. 0x15, 0x4e, /* ldr r6, =#0x1b71 */
  416. 0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
  417. 0x01, 0x26, /* movs r6, #1 */
  418. 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
  419. /* wait_fifo: */
  420. 0x16, 0x68, /* ldr r6, [r2, #0] */
  421. 0x00, 0x2e, /* cmp r6, #0 */
  422. 0x22, 0xd0, /* beq exit */
  423. 0x55, 0x68, /* ldr r5, [r2, #4] */
  424. 0xb5, 0x42, /* cmp r5, r6 */
  425. 0xf9, 0xd0, /* beq wait_fifo */
  426. 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
  427. 0x01, 0x26, /* movs r6, #1 */
  428. 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
  429. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  430. 0x06, 0x27, /* movs r7, #6 */
  431. 0x3e, 0x42, /* tst r6, r7 */
  432. 0x16, 0xd1, /* bne error */
  433. /* wait_wdataready: */
  434. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  435. 0x08, 0x27, /* movs r7, #8 */
  436. 0x3e, 0x42, /* tst r6, r7 */
  437. 0xfb, 0xd0, /* beq wait_wdataready */
  438. 0x2e, 0x68, /* ldr r6, [r5] */
  439. 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
  440. 0x08, 0x26, /* movs r6, #8 */
  441. 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
  442. 0x04, 0x35, /* adds r5, #4 */
  443. 0x04, 0x34, /* adds r4, #4 */
  444. /* busy: */
  445. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  446. 0x01, 0x27, /* movs r7, #1 */
  447. 0x3e, 0x42, /* tst r6, r7 */
  448. 0xfb, 0xd1, /* bne busy */
  449. 0x9d, 0x42, /* cmp r5, r3 */
  450. 0x01, 0xd3, /* bcc no_wrap */
  451. 0x15, 0x46, /* mov r5, r2 */
  452. 0x08, 0x35, /* adds r5, #8 */
  453. /* no_wrap: */
  454. 0x55, 0x60, /* str r5, [r2, #4] */
  455. 0x01, 0x39, /* subs r1, r1, #1 */
  456. 0x00, 0x29, /* cmp r1, #0 */
  457. 0x02, 0xd0, /* beq exit */
  458. 0xdb, 0xe7, /* b wait_fifo */
  459. /* error: */
  460. 0x00, 0x20, /* movs r0, #0 */
  461. 0x50, 0x60, /* str r0, [r2, #4] */
  462. /* exit: */
  463. 0x30, 0x46, /* mov r0, r6 */
  464. 0x00, 0xbe, /* bkpt #0 */
  465. /* LOCKKEY */
  466. 0x71, 0x1b, 0x00, 0x00
  467. };
  468. /* flash write code */
  469. if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
  470. &write_algorithm) != ERROR_OK) {
  471. LOG_WARNING("no working area available, can't do block memory writes");
  472. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  473. };
  474. ret = target_write_buffer(target, write_algorithm->address,
  475. sizeof(efm32x_flash_write_code),
  476. (uint8_t *)efm32x_flash_write_code);
  477. if (ret != ERROR_OK)
  478. return ret;
  479. /* memory buffer */
  480. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  481. buffer_size /= 2;
  482. buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
  483. if (buffer_size <= 256) {
  484. /* we already allocated the writing code, but failed to get a
  485. * buffer, free the algorithm */
  486. target_free_working_area(target, write_algorithm);
  487. LOG_WARNING("no large enough working area available, can't do block memory writes");
  488. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  489. }
  490. };
  491. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
  492. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
  493. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
  494. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
  495. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
  496. buf_set_u32(reg_params[0].value, 0, 32, EFM32_MSC_REGBASE);
  497. buf_set_u32(reg_params[1].value, 0, 32, count);
  498. buf_set_u32(reg_params[2].value, 0, 32, source->address);
  499. buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
  500. buf_set_u32(reg_params[4].value, 0, 32, address);
  501. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  502. armv7m_info.core_mode = ARM_MODE_THREAD;
  503. ret = target_run_flash_async_algorithm(target, buf, count, 4,
  504. 0, NULL,
  505. 5, reg_params,
  506. source->address, source->size,
  507. write_algorithm->address, 0,
  508. &armv7m_info);
  509. if (ret == ERROR_FLASH_OPERATION_FAILED) {
  510. LOG_ERROR("flash write failed at address 0x%"PRIx32,
  511. buf_get_u32(reg_params[4].value, 0, 32));
  512. if (buf_get_u32(reg_params[0].value, 0, 32) &
  513. EFM32_MSC_STATUS_LOCKED_MASK) {
  514. LOG_ERROR("flash memory write protected");
  515. }
  516. if (buf_get_u32(reg_params[0].value, 0, 32) &
  517. EFM32_MSC_STATUS_INVADDR_MASK) {
  518. LOG_ERROR("invalid flash memory write address");
  519. }
  520. }
  521. target_free_working_area(target, source);
  522. target_free_working_area(target, write_algorithm);
  523. destroy_reg_param(&reg_params[0]);
  524. destroy_reg_param(&reg_params[1]);
  525. destroy_reg_param(&reg_params[2]);
  526. destroy_reg_param(&reg_params[3]);
  527. destroy_reg_param(&reg_params[4]);
  528. return ret;
  529. }
  530. static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
  531. uint32_t val)
  532. {
  533. /* this function DOES NOT set WREN; must be set already */
  534. /* 1. write address to ADDRB
  535. 2. write LADDRIM
  536. 3. check status (INVADDR, LOCKED)
  537. 4. wait for WDATAREADY
  538. 5. write data to WDATA
  539. 6. write WRITECMD_WRITEONCE to WRITECMD
  540. 7. wait until !STATUS_BUSY
  541. */
  542. /* FIXME: EFM32G ref states (7.3.2) that writes should be
  543. * performed twice per dword */
  544. int ret = 0;
  545. uint32_t status = 0;
  546. /* if not called, GDB errors will be reported during large writes */
  547. keep_alive();
  548. ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
  549. if (ERROR_OK != ret)
  550. return ret;
  551. ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
  552. EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
  553. if (ERROR_OK != ret)
  554. return ret;
  555. ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
  556. if (ERROR_OK != ret)
  557. return ret;
  558. LOG_DEBUG("status 0x%x", status);
  559. if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
  560. LOG_ERROR("Page is locked");
  561. return ERROR_FAIL;
  562. } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
  563. LOG_ERROR("Invalid address 0x%x", addr);
  564. return ERROR_FAIL;
  565. }
  566. ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
  567. EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
  568. if (ERROR_OK != ret) {
  569. LOG_ERROR("Wait for WDATAREADY failed");
  570. return ret;
  571. }
  572. ret = target_write_u32(bank->target, EFM32_MSC_WDATA, val);
  573. if (ERROR_OK != ret) {
  574. LOG_ERROR("WDATA write failed");
  575. return ret;
  576. }
  577. ret = target_write_u32(bank->target, EFM32_MSC_WRITECMD,
  578. EFM32_MSC_WRITECMD_WRITEONCE_MASK);
  579. if (ERROR_OK != ret) {
  580. LOG_ERROR("WRITECMD write failed");
  581. return ret;
  582. }
  583. ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
  584. EFM32_MSC_STATUS_BUSY_MASK, 0);
  585. if (ERROR_OK != ret) {
  586. LOG_ERROR("Wait for BUSY failed");
  587. return ret;
  588. }
  589. return ERROR_OK;
  590. }
  591. static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
  592. uint32_t offset, uint32_t count)
  593. {
  594. struct target *target = bank->target;
  595. uint8_t *new_buffer = NULL;
  596. if (target->state != TARGET_HALTED) {
  597. LOG_ERROR("Target not halted");
  598. return ERROR_TARGET_NOT_HALTED;
  599. }
  600. if (offset & 0x3) {
  601. LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
  602. "alignment", offset);
  603. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  604. }
  605. if (count & 0x3) {
  606. uint32_t old_count = count;
  607. count = (old_count | 3) + 1;
  608. new_buffer = malloc(count);
  609. if (new_buffer == NULL) {
  610. LOG_ERROR("odd number of bytes to write and no memory "
  611. "for padding buffer");
  612. return ERROR_FAIL;
  613. }
  614. LOG_INFO("odd number of bytes to write (%d), extending to %d "
  615. "and padding with 0xff", old_count, count);
  616. memset(buffer, 0xff, count);
  617. buffer = memcpy(new_buffer, buffer, old_count);
  618. }
  619. uint32_t words_remaining = count / 4;
  620. int retval, retval2;
  621. /* unlock flash registers */
  622. efm32x_msc_lock(bank, 0);
  623. retval = efm32x_set_wren(bank, 1);
  624. if (retval != ERROR_OK)
  625. goto cleanup;
  626. /* try using a block write */
  627. retval = efm32x_write_block(bank, buffer, offset, words_remaining);
  628. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  629. /* if block write failed (no sufficient working area),
  630. * we use normal (slow) single word accesses */
  631. LOG_WARNING("couldn't use block writes, falling back to single "
  632. "memory accesses");
  633. while (words_remaining > 0) {
  634. uint32_t value;
  635. memcpy(&value, buffer, sizeof(uint32_t));
  636. retval = efm32x_write_word(bank, offset, value);
  637. if (retval != ERROR_OK)
  638. goto reset_pg_and_lock;
  639. words_remaining--;
  640. buffer += 4;
  641. offset += 4;
  642. }
  643. }
  644. reset_pg_and_lock:
  645. retval2 = efm32x_set_wren(bank, 0);
  646. efm32x_msc_lock(bank, 1);
  647. if (retval == ERROR_OK)
  648. retval = retval2;
  649. cleanup:
  650. if (new_buffer)
  651. free(new_buffer);
  652. return retval;
  653. }
  654. static int efm32x_probe(struct flash_bank *bank)
  655. {
  656. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  657. struct efm32_info efm32_mcu_info;
  658. int ret;
  659. int i;
  660. uint32_t base_address = 0x00000000;
  661. efm32x_info->probed = 0;
  662. memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
  663. ret = efm32x_read_info(bank, &efm32_mcu_info);
  664. if (ERROR_OK != ret)
  665. return ret;
  666. switch (efm32_mcu_info.part_family) {
  667. case EFM_FAMILY_ID_GECKO:
  668. LOG_INFO("Gecko MCU detected");
  669. break;
  670. case EFM_FAMILY_ID_GIANT_GECKO:
  671. LOG_INFO("Giant Gecko MCU detected");
  672. break;
  673. case EFM_FAMILY_ID_TINY_GECKO:
  674. LOG_INFO("Tiny Gecko MCU detected");
  675. break;
  676. case EFM_FAMILY_ID_LEOPARD_GECKO:
  677. LOG_INFO("Leopard Gecko MCU detected");
  678. break;
  679. default:
  680. LOG_ERROR("Unsupported MCU family %d",
  681. efm32_mcu_info.part_family);
  682. return ERROR_FAIL;
  683. }
  684. LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
  685. LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
  686. assert(0 != efm32_mcu_info.page_size);
  687. int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
  688. efm32_mcu_info.page_size;
  689. assert(num_pages > 0);
  690. if (bank->sectors) {
  691. free(bank->sectors);
  692. bank->sectors = NULL;
  693. }
  694. bank->base = base_address;
  695. bank->size = (num_pages * efm32_mcu_info.page_size);
  696. bank->num_sectors = num_pages;
  697. ret = efm32x_read_lock_data(bank);
  698. if (ERROR_OK != ret) {
  699. LOG_ERROR("Failed to read LB data");
  700. return ret;
  701. }
  702. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  703. for (i = 0; i < num_pages; i++) {
  704. bank->sectors[i].offset = i * efm32_mcu_info.page_size;
  705. bank->sectors[i].size = efm32_mcu_info.page_size;
  706. bank->sectors[i].is_erased = -1;
  707. bank->sectors[i].is_protected = 1;
  708. }
  709. efm32x_info->probed = 1;
  710. return ERROR_OK;
  711. }
  712. static int efm32x_auto_probe(struct flash_bank *bank)
  713. {
  714. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  715. if (efm32x_info->probed)
  716. return ERROR_OK;
  717. return efm32x_probe(bank);
  718. }
  719. static int efm32x_protect_check(struct flash_bank *bank)
  720. {
  721. struct target *target = bank->target;
  722. int ret = 0;
  723. int i = 0;
  724. if (target->state != TARGET_HALTED) {
  725. LOG_ERROR("Target not halted");
  726. return ERROR_TARGET_NOT_HALTED;
  727. }
  728. ret = efm32x_read_lock_data(bank);
  729. if (ERROR_OK != ret) {
  730. LOG_ERROR("Failed to read LB data");
  731. return ret;
  732. }
  733. assert(NULL != bank->sectors);
  734. for (i = 0; i < bank->num_sectors; i++)
  735. bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
  736. return ERROR_OK;
  737. }
  738. static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
  739. {
  740. struct efm32_info info;
  741. int ret = 0;
  742. int printed = 0;
  743. ret = efm32x_read_info(bank, &info);
  744. if (ERROR_OK != ret) {
  745. LOG_ERROR("Failed to read EFM32 info");
  746. return ret;
  747. }
  748. printed = snprintf(buf, buf_size, "EFM32 ");
  749. buf += printed;
  750. buf_size -= printed;
  751. if (0 >= buf_size)
  752. return ERROR_BUF_TOO_SMALL;
  753. switch (info.part_family) {
  754. case EFM_FAMILY_ID_GECKO:
  755. printed = snprintf(buf, buf_size, "Gecko");
  756. break;
  757. case EFM_FAMILY_ID_GIANT_GECKO:
  758. printed = snprintf(buf, buf_size, "Giant Gecko");
  759. break;
  760. case EFM_FAMILY_ID_TINY_GECKO:
  761. printed = snprintf(buf, buf_size, "Tiny Gecko");
  762. break;
  763. case EFM_FAMILY_ID_LEOPARD_GECKO:
  764. printed = snprintf(buf, buf_size, "Leopard Gecko");
  765. break;
  766. }
  767. buf += printed;
  768. buf_size -= printed;
  769. if (0 >= buf_size)
  770. return ERROR_BUF_TOO_SMALL;
  771. printed = snprintf(buf, buf_size, " - Rev: %d", info.prod_rev);
  772. buf += printed;
  773. buf_size -= printed;
  774. if (0 >= buf_size)
  775. return ERROR_BUF_TOO_SMALL;
  776. return ERROR_OK;
  777. }
  778. static const struct command_registration efm32x_exec_command_handlers[] = {
  779. COMMAND_REGISTRATION_DONE
  780. };
  781. static const struct command_registration efm32x_command_handlers[] = {
  782. {
  783. .name = "efm32",
  784. .mode = COMMAND_ANY,
  785. .help = "efm32 flash command group",
  786. .usage = "",
  787. .chain = efm32x_exec_command_handlers,
  788. },
  789. COMMAND_REGISTRATION_DONE
  790. };
  791. struct flash_driver efm32_flash = {
  792. .name = "efm32",
  793. .commands = efm32x_command_handlers,
  794. .flash_bank_command = efm32x_flash_bank_command,
  795. .erase = efm32x_erase,
  796. .protect = efm32x_protect,
  797. .write = efm32x_write,
  798. .read = default_flash_read,
  799. .probe = efm32x_probe,
  800. .auto_probe = efm32x_auto_probe,
  801. .erase_check = default_flash_blank_check,
  802. .protect_check = efm32x_protect_check,
  803. .info = get_efm32x_info,
  804. };