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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. *
  8. * Copyright (C) 2011 by Erik Botö
  9. * erik.boto@pelagicore.com
  10. *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <helper/binarybuffer.h>
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. /* em357 register locations */
  34. #define EM357_FLASH_ACR 0x40008000
  35. #define EM357_FLASH_KEYR 0x40008004
  36. #define EM357_FLASH_OPTKEYR 0x40008008
  37. #define EM357_FLASH_SR 0x4000800C
  38. #define EM357_FLASH_CR 0x40008010
  39. #define EM357_FLASH_AR 0x40008014
  40. #define EM357_FLASH_OBR 0x4000801C
  41. #define EM357_FLASH_WRPR 0x40008020
  42. #define EM357_FPEC_CLK 0x4000402c
  43. /* option byte location */
  44. #define EM357_OB_RDP 0x08040800
  45. #define EM357_OB_WRP0 0x08040808
  46. #define EM357_OB_WRP1 0x0804080A
  47. #define EM357_OB_WRP2 0x0804080C
  48. /* FLASH_CR register bits */
  49. #define FLASH_PG (1 << 0)
  50. #define FLASH_PER (1 << 1)
  51. #define FLASH_MER (1 << 2)
  52. #define FLASH_OPTPG (1 << 4)
  53. #define FLASH_OPTER (1 << 5)
  54. #define FLASH_STRT (1 << 6)
  55. #define FLASH_LOCK (1 << 7)
  56. #define FLASH_OPTWRE (1 << 9)
  57. /* FLASH_SR register bits */
  58. #define FLASH_BSY (1 << 0)
  59. #define FLASH_PGERR (1 << 2)
  60. #define FLASH_WRPRTERR (1 << 4)
  61. #define FLASH_EOP (1 << 5)
  62. /* EM357_FLASH_OBR bit definitions (reading) */
  63. #define OPT_ERROR 0
  64. #define OPT_READOUT 1
  65. /* register unlock keys */
  66. #define KEY1 0x45670123
  67. #define KEY2 0xCDEF89AB
  68. struct em357_options {
  69. uint16_t RDP;
  70. uint16_t user_options;
  71. uint16_t protection[3];
  72. };
  73. struct em357_flash_bank {
  74. struct em357_options option_bytes;
  75. int ppage_size;
  76. int probed;
  77. };
  78. static int em357_mass_erase(struct flash_bank *bank);
  79. /* flash bank em357 <base> <size> 0 0 <target#>
  80. */
  81. FLASH_BANK_COMMAND_HANDLER(em357_flash_bank_command)
  82. {
  83. struct em357_flash_bank *em357_info;
  84. if (CMD_ARGC < 6)
  85. return ERROR_COMMAND_SYNTAX_ERROR;
  86. em357_info = malloc(sizeof(struct em357_flash_bank));
  87. bank->driver_priv = em357_info;
  88. em357_info->probed = 0;
  89. return ERROR_OK;
  90. }
  91. static inline int em357_get_flash_status(struct flash_bank *bank, uint32_t *status)
  92. {
  93. struct target *target = bank->target;
  94. return target_read_u32(target, EM357_FLASH_SR, status);
  95. }
  96. static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
  97. {
  98. struct target *target = bank->target;
  99. uint32_t status;
  100. int retval = ERROR_OK;
  101. /* wait for busy to clear */
  102. for (;; ) {
  103. retval = em357_get_flash_status(bank, &status);
  104. if (retval != ERROR_OK)
  105. return retval;
  106. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  107. if ((status & FLASH_BSY) == 0)
  108. break;
  109. if (timeout-- <= 0) {
  110. LOG_ERROR("timed out waiting for flash");
  111. return ERROR_FAIL;
  112. }
  113. alive_sleep(1);
  114. }
  115. if (status & FLASH_WRPRTERR) {
  116. LOG_ERROR("em357 device protected");
  117. retval = ERROR_FAIL;
  118. }
  119. if (status & FLASH_PGERR) {
  120. LOG_ERROR("em357 device programming failed");
  121. retval = ERROR_FAIL;
  122. }
  123. /* Clear but report errors */
  124. if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
  125. /* If this operation fails, we ignore it and report the original
  126. * retval
  127. */
  128. target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
  129. }
  130. return retval;
  131. }
  132. static int em357_read_options(struct flash_bank *bank)
  133. {
  134. uint32_t optiondata;
  135. struct em357_flash_bank *em357_info = NULL;
  136. struct target *target = bank->target;
  137. em357_info = bank->driver_priv;
  138. /* read current option bytes */
  139. int retval = target_read_u32(target, EM357_FLASH_OBR, &optiondata);
  140. if (retval != ERROR_OK)
  141. return retval;
  142. em357_info->option_bytes.user_options = (uint16_t)0xFFFC | ((optiondata >> 2) & 0x03);
  143. em357_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
  144. if (optiondata & (1 << OPT_READOUT))
  145. LOG_INFO("Device Security Bit Set");
  146. /* each bit refers to a 4bank protection */
  147. retval = target_read_u32(target, EM357_FLASH_WRPR, &optiondata);
  148. if (retval != ERROR_OK)
  149. return retval;
  150. em357_info->option_bytes.protection[0] = (uint16_t)optiondata;
  151. em357_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
  152. em357_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
  153. return ERROR_OK;
  154. }
  155. static int em357_erase_options(struct flash_bank *bank)
  156. {
  157. struct em357_flash_bank *em357_info = NULL;
  158. struct target *target = bank->target;
  159. em357_info = bank->driver_priv;
  160. /* read current options */
  161. em357_read_options(bank);
  162. /* unlock flash registers */
  163. int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
  164. if (retval != ERROR_OK)
  165. return retval;
  166. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
  167. if (retval != ERROR_OK)
  168. return retval;
  169. /* unlock option flash registers */
  170. retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
  171. if (retval != ERROR_OK)
  172. return retval;
  173. retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
  174. if (retval != ERROR_OK)
  175. return retval;
  176. /* erase option bytes */
  177. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
  178. if (retval != ERROR_OK)
  179. return retval;
  180. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
  181. if (retval != ERROR_OK)
  182. return retval;
  183. retval = em357_wait_status_busy(bank, 10);
  184. if (retval != ERROR_OK)
  185. return retval;
  186. /* clear readout protection and complementary option bytes
  187. * this will also force a device unlock if set */
  188. em357_info->option_bytes.RDP = 0x5AA5;
  189. return ERROR_OK;
  190. }
  191. static int em357_write_options(struct flash_bank *bank)
  192. {
  193. struct em357_flash_bank *em357_info = NULL;
  194. struct target *target = bank->target;
  195. em357_info = bank->driver_priv;
  196. /* unlock flash registers */
  197. int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
  198. if (retval != ERROR_OK)
  199. return retval;
  200. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
  201. if (retval != ERROR_OK)
  202. return retval;
  203. /* unlock option flash registers */
  204. retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
  205. if (retval != ERROR_OK)
  206. return retval;
  207. retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
  208. if (retval != ERROR_OK)
  209. return retval;
  210. /* program option bytes */
  211. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
  212. if (retval != ERROR_OK)
  213. return retval;
  214. retval = em357_wait_status_busy(bank, 10);
  215. if (retval != ERROR_OK)
  216. return retval;
  217. /* write protection byte 1 */
  218. retval = target_write_u16(target, EM357_OB_WRP0, em357_info->option_bytes.protection[0]);
  219. if (retval != ERROR_OK)
  220. return retval;
  221. retval = em357_wait_status_busy(bank, 10);
  222. if (retval != ERROR_OK)
  223. return retval;
  224. /* write protection byte 2 */
  225. retval = target_write_u16(target, EM357_OB_WRP1, em357_info->option_bytes.protection[1]);
  226. if (retval != ERROR_OK)
  227. return retval;
  228. retval = em357_wait_status_busy(bank, 10);
  229. if (retval != ERROR_OK)
  230. return retval;
  231. /* write protection byte 3 */
  232. retval = target_write_u16(target, EM357_OB_WRP2, em357_info->option_bytes.protection[2]);
  233. if (retval != ERROR_OK)
  234. return retval;
  235. retval = em357_wait_status_busy(bank, 10);
  236. if (retval != ERROR_OK)
  237. return retval;
  238. /* write readout protection bit */
  239. retval = target_write_u16(target, EM357_OB_RDP, em357_info->option_bytes.RDP);
  240. if (retval != ERROR_OK)
  241. return retval;
  242. retval = em357_wait_status_busy(bank, 10);
  243. if (retval != ERROR_OK)
  244. return retval;
  245. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
  246. if (retval != ERROR_OK)
  247. return retval;
  248. return ERROR_OK;
  249. }
  250. static int em357_protect_check(struct flash_bank *bank)
  251. {
  252. struct target *target = bank->target;
  253. struct em357_flash_bank *em357_info = bank->driver_priv;
  254. uint32_t protection;
  255. int i, s;
  256. int num_bits;
  257. int set;
  258. if (target->state != TARGET_HALTED) {
  259. LOG_ERROR("Target not halted");
  260. return ERROR_TARGET_NOT_HALTED;
  261. }
  262. /* each bit refers to a 4bank protection (bit 0-23) */
  263. int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
  264. if (retval != ERROR_OK)
  265. return retval;
  266. /* each protection bit is for 4 * 2K pages */
  267. num_bits = (bank->num_sectors / em357_info->ppage_size);
  268. for (i = 0; i < num_bits; i++) {
  269. set = 1;
  270. if (protection & (1 << i))
  271. set = 0;
  272. for (s = 0; s < em357_info->ppage_size; s++)
  273. bank->sectors[(i * em357_info->ppage_size) + s].is_protected = set;
  274. }
  275. return ERROR_OK;
  276. }
  277. static int em357_erase(struct flash_bank *bank, int first, int last)
  278. {
  279. struct target *target = bank->target;
  280. int i;
  281. if (bank->target->state != TARGET_HALTED) {
  282. LOG_ERROR("Target not halted");
  283. return ERROR_TARGET_NOT_HALTED;
  284. }
  285. if ((first == 0) && (last == (bank->num_sectors - 1)))
  286. return em357_mass_erase(bank);
  287. /* Enable FPEC clock */
  288. target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
  289. /* unlock flash registers */
  290. int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
  291. if (retval != ERROR_OK)
  292. return retval;
  293. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
  294. if (retval != ERROR_OK)
  295. return retval;
  296. for (i = first; i <= last; i++) {
  297. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER);
  298. if (retval != ERROR_OK)
  299. return retval;
  300. retval = target_write_u32(target, EM357_FLASH_AR,
  301. bank->base + bank->sectors[i].offset);
  302. if (retval != ERROR_OK)
  303. return retval;
  304. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER | FLASH_STRT);
  305. if (retval != ERROR_OK)
  306. return retval;
  307. retval = em357_wait_status_busy(bank, 100);
  308. if (retval != ERROR_OK)
  309. return retval;
  310. bank->sectors[i].is_erased = 1;
  311. }
  312. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
  313. if (retval != ERROR_OK)
  314. return retval;
  315. return ERROR_OK;
  316. }
  317. static int em357_protect(struct flash_bank *bank, int set, int first, int last)
  318. {
  319. struct em357_flash_bank *em357_info = NULL;
  320. struct target *target = bank->target;
  321. uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
  322. int i, reg, bit;
  323. int status;
  324. uint32_t protection;
  325. em357_info = bank->driver_priv;
  326. if (target->state != TARGET_HALTED) {
  327. LOG_ERROR("Target not halted");
  328. return ERROR_TARGET_NOT_HALTED;
  329. }
  330. if ((first % em357_info->ppage_size) != 0) {
  331. LOG_WARNING("aligned start protect sector to a %d sector boundary",
  332. em357_info->ppage_size);
  333. first = first - (first % em357_info->ppage_size);
  334. }
  335. if (((last + 1) % em357_info->ppage_size) != 0) {
  336. LOG_WARNING("aligned end protect sector to a %d sector boundary",
  337. em357_info->ppage_size);
  338. last++;
  339. last = last - (last % em357_info->ppage_size);
  340. last--;
  341. }
  342. /* each bit refers to a 4bank protection */
  343. int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
  344. if (retval != ERROR_OK)
  345. return retval;
  346. prot_reg[0] = (uint16_t)protection;
  347. prot_reg[1] = (uint16_t)(protection >> 8);
  348. prot_reg[2] = (uint16_t)(protection >> 16);
  349. for (i = first; i <= last; i++) {
  350. reg = (i / em357_info->ppage_size) / 8;
  351. bit = (i / em357_info->ppage_size) - (reg * 8);
  352. LOG_WARNING("reg, bit: %d, %d", reg, bit);
  353. if (set)
  354. prot_reg[reg] &= ~(1 << bit);
  355. else
  356. prot_reg[reg] |= (1 << bit);
  357. }
  358. status = em357_erase_options(bank);
  359. if (retval != ERROR_OK)
  360. return status;
  361. em357_info->option_bytes.protection[0] = prot_reg[0];
  362. em357_info->option_bytes.protection[1] = prot_reg[1];
  363. em357_info->option_bytes.protection[2] = prot_reg[2];
  364. return em357_write_options(bank);
  365. }
  366. static int em357_write_block(struct flash_bank *bank, uint8_t *buffer,
  367. uint32_t offset, uint32_t count)
  368. {
  369. struct target *target = bank->target;
  370. uint32_t buffer_size = 16384;
  371. struct working_area *write_algorithm;
  372. struct working_area *source;
  373. uint32_t address = bank->base + offset;
  374. struct reg_param reg_params[4];
  375. struct armv7m_algorithm armv7m_info;
  376. int retval = ERROR_OK;
  377. /* see contib/loaders/flash/stm32x.s for src, the same is used here except for
  378. * a modified *_FLASH_BASE */
  379. static const uint8_t em357_flash_write_code[] = {
  380. /* #define EM357_FLASH_CR_OFFSET 0x10
  381. * #define EM357_FLASH_SR_OFFSET 0x0C
  382. * write: */
  383. 0x08, 0x4c, /* ldr r4, EM357_FLASH_BASE */
  384. 0x1c, 0x44, /* add r4, r3 */
  385. /* write_half_word: */
  386. 0x01, 0x23, /* movs r3, #0x01 */
  387. 0x23, 0x61, /* str r3, [r4,
  388. *#EM357_FLASH_CR_OFFSET] */
  389. 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
  390. 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
  391. /* busy: */
  392. 0xe3, 0x68, /* ldr r3, [r4,
  393. *#EM357_FLASH_SR_OFFSET] */
  394. 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
  395. 0xfb, 0xd0, /* beq busy */
  396. 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
  397. 0x01, 0xd1, /* bne exit */
  398. 0x01, 0x3a, /* subs r2, r2, #0x01 */
  399. 0xf0, 0xd1, /* bne write_half_word */
  400. /* exit: */
  401. 0x00, 0xbe, /* bkpt #0x00 */
  402. 0x00, 0x80, 0x00, 0x40, /* EM357_FLASH_BASE: .word 0x40008000 */
  403. };
  404. /* flash write code */
  405. if (target_alloc_working_area(target, sizeof(em357_flash_write_code),
  406. &write_algorithm) != ERROR_OK) {
  407. LOG_WARNING("no working area available, can't do block memory writes");
  408. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  409. }
  410. ;
  411. retval = target_write_buffer(target, write_algorithm->address,
  412. sizeof(em357_flash_write_code), (uint8_t *)em357_flash_write_code);
  413. if (retval != ERROR_OK)
  414. return retval;
  415. /* memory buffer */
  416. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  417. buffer_size /= 2;
  418. if (buffer_size <= 256) {
  419. /* we already allocated the writing code, but failed to get a
  420. * buffer, free the algorithm */
  421. target_free_working_area(target, write_algorithm);
  422. LOG_WARNING(
  423. "no large enough working area available, can't do block memory writes");
  424. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  425. }
  426. }
  427. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  428. armv7m_info.core_mode = ARM_MODE_THREAD;
  429. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  430. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  431. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  432. init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
  433. while (count > 0) {
  434. uint32_t thisrun_count = (count > (buffer_size / 2)) ?
  435. (buffer_size / 2) : count;
  436. retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
  437. if (retval != ERROR_OK)
  438. break;
  439. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  440. buf_set_u32(reg_params[1].value, 0, 32, address);
  441. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
  442. buf_set_u32(reg_params[3].value, 0, 32, 0);
  443. retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
  444. write_algorithm->address, 0, 10000, &armv7m_info);
  445. if (retval != ERROR_OK) {
  446. LOG_ERROR("error executing em357 flash write algorithm");
  447. break;
  448. }
  449. if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR) {
  450. LOG_ERROR("flash memory not erased before writing");
  451. /* Clear but report errors */
  452. target_write_u32(target, EM357_FLASH_SR, FLASH_PGERR);
  453. retval = ERROR_FAIL;
  454. break;
  455. }
  456. if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR) {
  457. LOG_ERROR("flash memory write protected");
  458. /* Clear but report errors */
  459. target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR);
  460. retval = ERROR_FAIL;
  461. break;
  462. }
  463. buffer += thisrun_count * 2;
  464. address += thisrun_count * 2;
  465. count -= thisrun_count;
  466. }
  467. target_free_working_area(target, source);
  468. target_free_working_area(target, write_algorithm);
  469. destroy_reg_param(&reg_params[0]);
  470. destroy_reg_param(&reg_params[1]);
  471. destroy_reg_param(&reg_params[2]);
  472. destroy_reg_param(&reg_params[3]);
  473. return retval;
  474. }
  475. static int em357_write(struct flash_bank *bank, uint8_t *buffer,
  476. uint32_t offset, uint32_t count)
  477. {
  478. struct target *target = bank->target;
  479. uint32_t words_remaining = (count / 2);
  480. uint32_t bytes_remaining = (count & 0x00000001);
  481. uint32_t address = bank->base + offset;
  482. uint32_t bytes_written = 0;
  483. int retval;
  484. if (bank->target->state != TARGET_HALTED) {
  485. LOG_ERROR("Target not halted");
  486. return ERROR_TARGET_NOT_HALTED;
  487. }
  488. if (offset & 0x1) {
  489. LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
  490. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  491. }
  492. /* unlock flash registers */
  493. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
  494. if (retval != ERROR_OK)
  495. return retval;
  496. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
  497. if (retval != ERROR_OK)
  498. return retval;
  499. target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
  500. /* multiple half words (2-byte) to be programmed? */
  501. if (words_remaining > 0) {
  502. /* try using a block write */
  503. retval = em357_write_block(bank, buffer, offset, words_remaining);
  504. if (retval != ERROR_OK) {
  505. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  506. /* if block write failed (no sufficient working area),
  507. * we use normal (slow) single dword accesses */
  508. LOG_WARNING(
  509. "couldn't use block writes, falling back to single memory accesses");
  510. }
  511. } else {
  512. buffer += words_remaining * 2;
  513. address += words_remaining * 2;
  514. words_remaining = 0;
  515. }
  516. }
  517. if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
  518. return retval;
  519. while (words_remaining > 0) {
  520. uint16_t value;
  521. memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
  522. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
  523. if (retval != ERROR_OK)
  524. return retval;
  525. retval = target_write_u16(target, address, value);
  526. if (retval != ERROR_OK)
  527. return retval;
  528. retval = em357_wait_status_busy(bank, 5);
  529. if (retval != ERROR_OK)
  530. return retval;
  531. bytes_written += 2;
  532. words_remaining--;
  533. address += 2;
  534. }
  535. if (bytes_remaining) {
  536. uint16_t value = 0xffff;
  537. memcpy(&value, buffer + bytes_written, bytes_remaining);
  538. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
  539. if (retval != ERROR_OK)
  540. return retval;
  541. retval = target_write_u16(target, address, value);
  542. if (retval != ERROR_OK)
  543. return retval;
  544. retval = em357_wait_status_busy(bank, 5);
  545. if (retval != ERROR_OK)
  546. return retval;
  547. }
  548. return target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
  549. }
  550. static int em357_probe(struct flash_bank *bank)
  551. {
  552. struct target *target = bank->target;
  553. struct em357_flash_bank *em357_info = bank->driver_priv;
  554. int i;
  555. uint16_t num_pages;
  556. int page_size;
  557. uint32_t base_address = 0x08000000;
  558. em357_info->probed = 0;
  559. switch (bank->size) {
  560. case 0x10000:
  561. /* 64k -- 64 1k pages */
  562. num_pages = 64;
  563. page_size = 1024;
  564. break;
  565. case 0x20000:
  566. /* 128k -- 128 1k pages */
  567. num_pages = 128;
  568. page_size = 1024;
  569. break;
  570. case 0x30000:
  571. /* 192k -- 96 2k pages */
  572. num_pages = 96;
  573. page_size = 2048;
  574. break;
  575. case 0x40000:
  576. /* 256k -- 128 2k pages */
  577. num_pages = 128;
  578. page_size = 2048;
  579. break;
  580. default:
  581. LOG_WARNING("No size specified for em357 flash driver, assuming 192k!");
  582. num_pages = 96;
  583. page_size = 2048;
  584. break;
  585. }
  586. /* Enable FPEC CLK */
  587. int retval = target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
  588. if (retval != ERROR_OK)
  589. return retval;
  590. em357_info->ppage_size = 4;
  591. LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024);
  592. if (bank->sectors) {
  593. free(bank->sectors);
  594. bank->sectors = NULL;
  595. }
  596. bank->base = base_address;
  597. bank->size = (num_pages * page_size);
  598. bank->num_sectors = num_pages;
  599. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  600. for (i = 0; i < num_pages; i++) {
  601. bank->sectors[i].offset = i * page_size;
  602. bank->sectors[i].size = page_size;
  603. bank->sectors[i].is_erased = -1;
  604. bank->sectors[i].is_protected = 1;
  605. }
  606. em357_info->probed = 1;
  607. return ERROR_OK;
  608. }
  609. static int em357_auto_probe(struct flash_bank *bank)
  610. {
  611. struct em357_flash_bank *em357_info = bank->driver_priv;
  612. if (em357_info->probed)
  613. return ERROR_OK;
  614. return em357_probe(bank);
  615. }
  616. static int get_em357_info(struct flash_bank *bank, char *buf, int buf_size)
  617. {
  618. snprintf(buf, buf_size, "em357\n");
  619. return ERROR_OK;
  620. }
  621. COMMAND_HANDLER(em357_handle_lock_command)
  622. {
  623. struct target *target = NULL;
  624. struct em357_flash_bank *em357_info = NULL;
  625. if (CMD_ARGC < 1)
  626. return ERROR_COMMAND_SYNTAX_ERROR;
  627. struct flash_bank *bank;
  628. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  629. if (ERROR_OK != retval)
  630. return retval;
  631. em357_info = bank->driver_priv;
  632. target = bank->target;
  633. if (target->state != TARGET_HALTED) {
  634. LOG_ERROR("Target not halted");
  635. return ERROR_TARGET_NOT_HALTED;
  636. }
  637. if (em357_erase_options(bank) != ERROR_OK) {
  638. command_print(CMD_CTX, "em357 failed to erase options");
  639. return ERROR_OK;
  640. }
  641. /* set readout protection */
  642. em357_info->option_bytes.RDP = 0;
  643. if (em357_write_options(bank) != ERROR_OK) {
  644. command_print(CMD_CTX, "em357 failed to lock device");
  645. return ERROR_OK;
  646. }
  647. command_print(CMD_CTX, "em357 locked");
  648. return ERROR_OK;
  649. }
  650. COMMAND_HANDLER(em357_handle_unlock_command)
  651. {
  652. struct target *target = NULL;
  653. if (CMD_ARGC < 1)
  654. return ERROR_COMMAND_SYNTAX_ERROR;
  655. struct flash_bank *bank;
  656. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  657. if (ERROR_OK != retval)
  658. return retval;
  659. target = bank->target;
  660. if (target->state != TARGET_HALTED) {
  661. LOG_ERROR("Target not halted");
  662. return ERROR_TARGET_NOT_HALTED;
  663. }
  664. if (em357_erase_options(bank) != ERROR_OK) {
  665. command_print(CMD_CTX, "em357 failed to unlock device");
  666. return ERROR_OK;
  667. }
  668. if (em357_write_options(bank) != ERROR_OK) {
  669. command_print(CMD_CTX, "em357 failed to lock device");
  670. return ERROR_OK;
  671. }
  672. command_print(CMD_CTX, "em357 unlocked.\n"
  673. "INFO: a reset or power cycle is required "
  674. "for the new settings to take effect.");
  675. return ERROR_OK;
  676. }
  677. static int em357_mass_erase(struct flash_bank *bank)
  678. {
  679. struct target *target = bank->target;
  680. if (target->state != TARGET_HALTED) {
  681. LOG_ERROR("Target not halted");
  682. return ERROR_TARGET_NOT_HALTED;
  683. }
  684. /* Make sure the flash clock is on */
  685. target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
  686. /* unlock option flash registers */
  687. int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
  688. if (retval != ERROR_OK)
  689. return retval;
  690. retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
  691. if (retval != ERROR_OK)
  692. return retval;
  693. /* mass erase flash memory */
  694. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER);
  695. if (retval != ERROR_OK)
  696. return retval;
  697. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER | FLASH_STRT);
  698. if (retval != ERROR_OK)
  699. return retval;
  700. retval = em357_wait_status_busy(bank, 100);
  701. if (retval != ERROR_OK)
  702. return retval;
  703. retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
  704. if (retval != ERROR_OK)
  705. return retval;
  706. return ERROR_OK;
  707. }
  708. COMMAND_HANDLER(em357_handle_mass_erase_command)
  709. {
  710. int i;
  711. if (CMD_ARGC < 1)
  712. return ERROR_COMMAND_SYNTAX_ERROR;
  713. struct flash_bank *bank;
  714. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  715. if (ERROR_OK != retval)
  716. return retval;
  717. retval = em357_mass_erase(bank);
  718. if (retval == ERROR_OK) {
  719. /* set all sectors as erased */
  720. for (i = 0; i < bank->num_sectors; i++)
  721. bank->sectors[i].is_erased = 1;
  722. command_print(CMD_CTX, "em357 mass erase complete");
  723. } else
  724. command_print(CMD_CTX, "em357 mass erase failed");
  725. return retval;
  726. }
  727. static const struct command_registration em357_exec_command_handlers[] = {
  728. {
  729. .name = "lock",
  730. .usage = "<bank>",
  731. .handler = em357_handle_lock_command,
  732. .mode = COMMAND_EXEC,
  733. .help = "Lock entire flash device.",
  734. },
  735. {
  736. .name = "unlock",
  737. .usage = "<bank>",
  738. .handler = em357_handle_unlock_command,
  739. .mode = COMMAND_EXEC,
  740. .help = "Unlock entire protected flash device.",
  741. },
  742. {
  743. .name = "mass_erase",
  744. .usage = "<bank>",
  745. .handler = em357_handle_mass_erase_command,
  746. .mode = COMMAND_EXEC,
  747. .help = "Erase entire flash device.",
  748. },
  749. COMMAND_REGISTRATION_DONE
  750. };
  751. static const struct command_registration em357_command_handlers[] = {
  752. {
  753. .name = "em357",
  754. .mode = COMMAND_ANY,
  755. .help = "em357 flash command group",
  756. .usage = "",
  757. .chain = em357_exec_command_handlers,
  758. },
  759. COMMAND_REGISTRATION_DONE
  760. };
  761. struct flash_driver em357_flash = {
  762. .name = "em357",
  763. .commands = em357_command_handlers,
  764. .flash_bank_command = em357_flash_bank_command,
  765. .erase = em357_erase,
  766. .protect = em357_protect,
  767. .write = em357_write,
  768. .read = default_flash_read,
  769. .probe = em357_probe,
  770. .auto_probe = em357_auto_probe,
  771. .erase_check = default_flash_blank_check,
  772. .protect_check = em357_protect_check,
  773. .info = get_em357_info,
  774. };