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  1. /***************************************************************************
  2. * Copyright (C) 2011 by Marc Willam, Holger Wech *
  3. * openOCD.fseu(AT)de.fujitsu.com *
  4. * Copyright (C) 2011 Ronny Strutz *
  5. * *
  6. * This program is free software; you can redistribute it and/or modify *
  7. * it under the terms of the GNU General Public License as published by *
  8. * the Free Software Foundation; either version 2 of the License, or *
  9. * (at your option) any later version. *
  10. * *
  11. * This program is distributed in the hope that it will be useful, *
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  14. * GNU General Public License for more details. *
  15. * *
  16. * You should have received a copy of the GNU General Public License *
  17. * along with this program; if not, write to the *
  18. * Free Software Foundation, Inc., *
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  20. ***************************************************************************/
  21. #ifdef HAVE_CONFIG_H
  22. #include "config.h"
  23. #endif
  24. #include "imp.h"
  25. #include <helper/binarybuffer.h>
  26. #include <target/algorithm.h>
  27. #include <target/armv7m.h>
  28. #define FLASH_DQ6 0x00000040 /* Data toggle flag bit (TOGG) position */
  29. #define FLASH_DQ5 0x00000020 /* Time limit exceeding flag bit (TLOV) position */
  30. enum fm3_variant {
  31. mb9bfxx1, /* Flash Type '1' */
  32. mb9bfxx2,
  33. mb9bfxx3,
  34. mb9bfxx4,
  35. mb9bfxx5,
  36. mb9bfxx6,
  37. mb9bfxx7,
  38. mb9bfxx8,
  39. mb9afxx1, /* Flash Type '2' */
  40. mb9afxx2,
  41. mb9afxx3,
  42. mb9afxx4,
  43. mb9afxx5,
  44. mb9afxx6,
  45. mb9afxx7,
  46. mb9afxx8,
  47. };
  48. enum fm3_flash_type {
  49. fm3_no_flash_type = 0,
  50. fm3_flash_type1 = 1,
  51. fm3_flash_type2 = 2
  52. };
  53. struct fm3_flash_bank {
  54. enum fm3_variant variant;
  55. enum fm3_flash_type flashtype;
  56. int probed;
  57. };
  58. FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
  59. {
  60. struct fm3_flash_bank *fm3_info;
  61. if (CMD_ARGC < 6)
  62. return ERROR_COMMAND_SYNTAX_ERROR;
  63. fm3_info = malloc(sizeof(struct fm3_flash_bank));
  64. bank->driver_priv = fm3_info;
  65. /* Flash type '1' */
  66. if (strcmp(CMD_ARGV[5], "mb9bfxx1.cpu") == 0) {
  67. fm3_info->variant = mb9bfxx1;
  68. fm3_info->flashtype = fm3_flash_type1;
  69. } else if (strcmp(CMD_ARGV[5], "mb9bfxx2.cpu") == 0) {
  70. fm3_info->variant = mb9bfxx2;
  71. fm3_info->flashtype = fm3_flash_type1;
  72. } else if (strcmp(CMD_ARGV[5], "mb9bfxx3.cpu") == 0) {
  73. fm3_info->variant = mb9bfxx3;
  74. fm3_info->flashtype = fm3_flash_type1;
  75. } else if (strcmp(CMD_ARGV[5], "mb9bfxx4.cpu") == 0) {
  76. fm3_info->variant = mb9bfxx4;
  77. fm3_info->flashtype = fm3_flash_type1;
  78. } else if (strcmp(CMD_ARGV[5], "mb9bfxx5.cpu") == 0) {
  79. fm3_info->variant = mb9bfxx5;
  80. fm3_info->flashtype = fm3_flash_type1;
  81. } else if (strcmp(CMD_ARGV[5], "mb9bfxx6.cpu") == 0) {
  82. fm3_info->variant = mb9bfxx6;
  83. fm3_info->flashtype = fm3_flash_type1;
  84. } else if (strcmp(CMD_ARGV[5], "mb9bfxx7.cpu") == 0) {
  85. fm3_info->variant = mb9bfxx7;
  86. fm3_info->flashtype = fm3_flash_type1;
  87. } else if (strcmp(CMD_ARGV[5], "mb9bfxx8.cpu") == 0) {
  88. fm3_info->variant = mb9bfxx8;
  89. fm3_info->flashtype = fm3_flash_type1;
  90. } else if (strcmp(CMD_ARGV[5], "mb9afxx1.cpu") == 0) { /* Flash type '2' */
  91. fm3_info->variant = mb9afxx1;
  92. fm3_info->flashtype = fm3_flash_type2;
  93. } else if (strcmp(CMD_ARGV[5], "mb9afxx2.cpu") == 0) {
  94. fm3_info->variant = mb9afxx2;
  95. fm3_info->flashtype = fm3_flash_type2;
  96. } else if (strcmp(CMD_ARGV[5], "mb9afxx3.cpu") == 0) {
  97. fm3_info->variant = mb9afxx3;
  98. fm3_info->flashtype = fm3_flash_type2;
  99. } else if (strcmp(CMD_ARGV[5], "mb9afxx4.cpu") == 0) {
  100. fm3_info->variant = mb9afxx4;
  101. fm3_info->flashtype = fm3_flash_type2;
  102. } else if (strcmp(CMD_ARGV[5], "mb9afxx5.cpu") == 0) {
  103. fm3_info->variant = mb9afxx5;
  104. fm3_info->flashtype = fm3_flash_type2;
  105. } else if (strcmp(CMD_ARGV[5], "mb9afxx6.cpu") == 0) {
  106. fm3_info->variant = mb9afxx6;
  107. fm3_info->flashtype = fm3_flash_type2;
  108. } else if (strcmp(CMD_ARGV[5], "mb9afxx7.cpu") == 0) {
  109. fm3_info->variant = mb9afxx7;
  110. fm3_info->flashtype = fm3_flash_type2;
  111. } else if (strcmp(CMD_ARGV[5], "mb9afxx8.cpu") == 0) {
  112. fm3_info->variant = mb9afxx8;
  113. fm3_info->flashtype = fm3_flash_type2;
  114. }
  115. /* unknown Flash type */
  116. else {
  117. LOG_ERROR("unknown fm3 variant: %s", CMD_ARGV[5]);
  118. free(fm3_info);
  119. return ERROR_FLASH_BANK_INVALID;
  120. }
  121. fm3_info->probed = 0;
  122. return ERROR_OK;
  123. }
  124. /* Data polling algorithm */
  125. static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms)
  126. {
  127. int retval = ERROR_OK;
  128. uint16_t state1, state2;
  129. int ms = 0;
  130. /* While(1) loop exit via "break" and "return" on error */
  131. while (1) {
  132. /* dummy-read - see flash manual */
  133. retval = target_read_u16(target, offset, &state1);
  134. if (retval != ERROR_OK)
  135. return retval;
  136. /* Data polling 1 */
  137. retval = target_read_u16(target, offset, &state1);
  138. if (retval != ERROR_OK)
  139. return retval;
  140. /* Data polling 2 */
  141. retval = target_read_u16(target, offset, &state2);
  142. if (retval != ERROR_OK)
  143. return retval;
  144. /* Flash command finished via polled data equal? */
  145. if ((state1 & FLASH_DQ6) == (state2 & FLASH_DQ6))
  146. break;
  147. /* Timeout Flag? */
  148. else if (state1 & FLASH_DQ5) {
  149. /* Retry data polling */
  150. /* Data polling 1 */
  151. retval = target_read_u16(target, offset, &state1);
  152. if (retval != ERROR_OK)
  153. return retval;
  154. /* Data polling 2 */
  155. retval = target_read_u16(target, offset, &state2);
  156. if (retval != ERROR_OK)
  157. return retval;
  158. /* Flash command finished via polled data equal? */
  159. if ((state1 & FLASH_DQ6) != (state2 & FLASH_DQ6))
  160. return ERROR_FLASH_OPERATION_FAILED;
  161. /* finish anyway */
  162. break;
  163. }
  164. usleep(1000);
  165. ++ms;
  166. /* Polling time exceeded? */
  167. if (ms > timeout_ms) {
  168. LOG_ERROR("Polling data reading timed out!");
  169. return ERROR_FLASH_OPERATION_FAILED;
  170. }
  171. }
  172. if (retval == ERROR_OK)
  173. LOG_DEBUG("fm3_busy_wait(%x) needs about %d ms", offset, ms);
  174. return retval;
  175. }
  176. static int fm3_erase(struct flash_bank *bank, int first, int last)
  177. {
  178. struct fm3_flash_bank *fm3_info = bank->driver_priv;
  179. struct target *target = bank->target;
  180. int retval = ERROR_OK;
  181. uint32_t u32DummyRead;
  182. int sector, odd;
  183. uint32_t u32FlashType;
  184. uint32_t u32FlashSeqAddress1;
  185. uint32_t u32FlashSeqAddress2;
  186. u32FlashType = (uint32_t) fm3_info->flashtype;
  187. if (u32FlashType == fm3_flash_type1) {
  188. u32FlashSeqAddress1 = 0x00001550;
  189. u32FlashSeqAddress2 = 0x00000AA8;
  190. } else if (u32FlashType == fm3_flash_type2) {
  191. u32FlashSeqAddress1 = 0x00000AA8;
  192. u32FlashSeqAddress2 = 0x00000554;
  193. } else {
  194. LOG_ERROR("Flash/Device type unknown!");
  195. return ERROR_FLASH_OPERATION_FAILED;
  196. }
  197. if (target->state != TARGET_HALTED) {
  198. LOG_ERROR("Target not halted");
  199. return ERROR_TARGET_NOT_HALTED;
  200. }
  201. LOG_INFO("Fujitsu MB9Bxxx: Sector Erase ... (%d to %d)", first, last);
  202. /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */
  203. retval = target_write_u32(target, 0x40000000, 0x0001);
  204. if (retval != ERROR_OK)
  205. return retval;
  206. /* dummy read of FASZR */
  207. retval = target_read_u32(target, 0x40000000, &u32DummyRead);
  208. if (retval != ERROR_OK)
  209. return retval;
  210. for (sector = first ; sector <= last ; sector++) {
  211. uint32_t offset = bank->sectors[sector].offset;
  212. for (odd = 0; odd < 2 ; odd++) {
  213. if (odd)
  214. offset += 4;
  215. /* Flash unlock sequence */
  216. retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA);
  217. if (retval != ERROR_OK)
  218. return retval;
  219. retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. retval = target_write_u16(target, u32FlashSeqAddress1, 0x0080);
  223. if (retval != ERROR_OK)
  224. return retval;
  225. retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA);
  226. if (retval != ERROR_OK)
  227. return retval;
  228. retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055);
  229. if (retval != ERROR_OK)
  230. return retval;
  231. /* Sector erase command (0x0030) */
  232. retval = target_write_u16(target, offset, 0x0030);
  233. if (retval != ERROR_OK)
  234. return retval;
  235. retval = fm3_busy_wait(target, offset, 500);
  236. if (retval != ERROR_OK)
  237. return retval;
  238. }
  239. bank->sectors[sector].is_erased = 1;
  240. }
  241. /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */
  242. retval = target_write_u32(target, 0x40000000, 0x0002);
  243. if (retval != ERROR_OK)
  244. return retval;
  245. retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
  246. return retval;
  247. }
  248. static int fm3_write_block(struct flash_bank *bank, uint8_t *buffer,
  249. uint32_t offset, uint32_t count)
  250. {
  251. struct fm3_flash_bank *fm3_info = bank->driver_priv;
  252. struct target *target = bank->target;
  253. uint32_t buffer_size = 2048; /* 8192 for MB9Bxx6! */
  254. struct working_area *write_algorithm;
  255. struct working_area *source;
  256. uint32_t address = bank->base + offset;
  257. struct reg_param reg_params[6];
  258. struct armv7m_algorithm armv7m_info;
  259. int retval = ERROR_OK;
  260. uint32_t u32FlashType;
  261. uint32_t u32FlashSeqAddress1;
  262. uint32_t u32FlashSeqAddress2;
  263. u32FlashType = (uint32_t) fm3_info->flashtype;
  264. if (u32FlashType == fm3_flash_type1) {
  265. u32FlashSeqAddress1 = 0x00001550;
  266. u32FlashSeqAddress2 = 0x00000AA8;
  267. } else if (u32FlashType == fm3_flash_type2) {
  268. u32FlashSeqAddress1 = 0x00000AA8;
  269. u32FlashSeqAddress2 = 0x00000554;
  270. } else {
  271. LOG_ERROR("Flash/Device type unknown!");
  272. return ERROR_FLASH_OPERATION_FAILED;
  273. }
  274. /* RAMCODE used for fm3 Flash programming: */
  275. /* R0 keeps source start address (u32Source) */
  276. /* R1 keeps target start address (u32Target) */
  277. /* R2 keeps number of halfwords to write (u32Count) */
  278. /* R3 keeps Flash Sequence address 1 (u32FlashSeq1) */
  279. /* R4 keeps Flash Sequence address 2 (u32FlashSeq2) */
  280. /* R5 returns result value (u32FlashResult) */
  281. const uint8_t fm3_flash_write_code[] = {
  282. /* fm3_FLASH_IF->FASZ &= 0xFFFD; */
  283. 0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
  284. 0x2D, 0x68, /* LDR R5, [R5] */
  285. 0x4F, 0xF6, 0xFD, 0x76, /* MOVW R6, #0xFFFD */
  286. 0x35, 0x40, /* ANDS R5, R5, R6 */
  287. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  288. 0x35, 0x60, /* STR R5, [R6] */
  289. /* fm3_FLASH_IF->FASZ |= 1; */
  290. 0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
  291. 0x2D, 0x68, /* LDR R5, [R3] */
  292. 0x55, 0xF0, 0x01, 0x05, /* ORRS.W R5, R5, #1 */
  293. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  294. 0x35, 0x60, /* STR R5, [R6] */
  295. /* u32DummyRead = fm3_FLASH_IF->FASZ; */
  296. 0x28, 0x4D, /* LDR.N R5, ??u32DummyRead */
  297. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  298. 0x36, 0x68, /* LDR R6, [R6] */
  299. 0x2E, 0x60, /* STR R6, [R5] */
  300. /* u32FlashResult = FLASH_WRITE_NO_RESULT */
  301. 0x26, 0x4D, /* LDR.N R5, ??u32FlashResult */
  302. 0x00, 0x26, /* MOVS R6, #0 */
  303. 0x2E, 0x60, /* STR R6, [R5] */
  304. /* while ((u32Count > 0 ) */
  305. /* && (u32FlashResult */
  306. /* == FLASH_WRITE_NO_RESULT)) */
  307. 0x01, 0x2A, /* L0: CMP R2, #1 */
  308. 0x2C, 0xDB, /* BLT.N L1 */
  309. 0x24, 0x4D, /* LDR.N R5, ??u32FlashResult */
  310. 0x2D, 0x68, /* LDR R5, [R5] */
  311. 0x00, 0x2D, /* CMP R5, #0 */
  312. 0x28, 0xD1, /* BNE.N L1 */
  313. /* *u32FlashSeq1 = FLASH_WRITE_1; */
  314. 0xAA, 0x25, /* MOVS R5, #0xAA */
  315. 0x1D, 0x60, /* STR R5, [R3] */
  316. /* *u32FlashSeq2 = FLASH_WRITE_2; */
  317. 0x55, 0x25, /* MOVS R5, #0x55 */
  318. 0x25, 0x60, /* STR R5, [R4] */
  319. /* *u32FlashSeq1 = FLASH_WRITE_3; */
  320. 0xA0, 0x25, /* MOVS R5, #0xA0 */
  321. 0x1D, 0x60, /* STRH R5, [R3] */
  322. /* *(volatile uint16_t*)u32Target */
  323. /* = *(volatile uint16_t*)u32Source; */
  324. 0x05, 0x88, /* LDRH R5, [R0] */
  325. 0x0D, 0x80, /* STRH R5, [R1] */
  326. /* while (u32FlashResult */
  327. /* == FLASH_WRITE_NO_RESTULT) */
  328. 0x1E, 0x4D, /* L2: LDR.N R5, ??u32FlashResult */
  329. 0x2D, 0x68, /* LDR R5, [R5] */
  330. 0x00, 0x2D, /* CMP R5, #0 */
  331. 0x11, 0xD1, /* BNE.N L3 */
  332. /* if ((*(volatile uint16_t*)u32Target */
  333. /* & FLASH_DQ5) == FLASH_DQ5) */
  334. 0x0D, 0x88, /* LDRH R5, [R1] */
  335. 0xAD, 0x06, /* LSLS R5, R5, #0x1A */
  336. 0x02, 0xD5, /* BPL.N L4 */
  337. /* u32FlashResult = FLASH_WRITE_TIMEOUT */
  338. 0x1A, 0x4D, /* LDR.N R5, ??u32FlashResult */
  339. 0x02, 0x26, /* MOVS R6, #2 */
  340. 0x2E, 0x60, /* STR R6, [R5] */
  341. /* if ((*(volatile uint16_t *)u32Target */
  342. /* & FLASH_DQ7) */
  343. /* == (*(volatile uint16_t*)u32Source */
  344. /* & FLASH_DQ7)) */
  345. 0x0D, 0x88, /* L4: LDRH R5, [R1] */
  346. 0x15, 0xF0, 0x80, 0x05, /* ANDS.W R5, R5, #0x80 */
  347. 0x06, 0x88, /* LDRH R6, [R0] */
  348. 0x16, 0xF0, 0x80, 0x06, /* ANDS.W R6, R6, #0x80 */
  349. 0xB5, 0x42, /* CMP R5, R6 */
  350. 0xED, 0xD1, /* BNE.N L2 */
  351. /* u32FlashResult = FLASH_WRITE_OKAY */
  352. 0x15, 0x4D, /* LDR.N R5, ??u32FlashResult */
  353. 0x01, 0x26, /* MOVS R6, #1 */
  354. 0x2E, 0x60, /* STR R6, [R5] */
  355. 0xE9, 0xE7, /* B.N L2 */
  356. /* if (u32FlashResult */
  357. /* != FLASH_WRITE_TIMEOUT) */
  358. 0x13, 0x4D, /* LDR.N R5, ??u32FlashResult */
  359. 0x2D, 0x68, /* LDR R5, [R5] */
  360. 0x02, 0x2D, /* CMP R5, #2 */
  361. 0x02, 0xD0, /* BEQ.N L5 */
  362. /* u32FlashResult = FLASH_WRITE_NO_RESULT */
  363. 0x11, 0x4D, /* LDR.N R5, ??u32FlashResult */
  364. 0x00, 0x26, /* MOVS R6, #0 */
  365. 0x2E, 0x60, /* STR R6, [R5] */
  366. /* u32Count--; */
  367. 0x52, 0x1E, /* L5: SUBS R2, R2, #1 */
  368. /* u32Source += 2; */
  369. 0x80, 0x1C, /* ADDS R0, R0, #2 */
  370. /* u32Target += 2; */
  371. 0x89, 0x1C, /* ADDS R1, R1, #2 */
  372. 0xD0, 0xE7, /* B.N L0 */
  373. /* fm3_FLASH_IF->FASZ &= 0xFFFE; */
  374. 0x5F, 0xF0, 0x80, 0x45, /* L1: MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
  375. 0x2D, 0x68, /* LDR R5, [R5] */
  376. 0x4F, 0xF6, 0xFE, 0x76, /* MOVW R6, #0xFFFE */
  377. 0x35, 0x40, /* ANDS R5, R5, R6 */
  378. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  379. 0x35, 0x60, /* STR R5, [R6] */
  380. /* fm3_FLASH_IF->FASZ |= 2; */
  381. 0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
  382. 0x2D, 0x68, /* LDR R5, [R5] */
  383. 0x55, 0xF0, 0x02, 0x05, /* ORRS.W R5, R5, #2 */
  384. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  385. 0x35, 0x60, /* STR R5, [R6] */
  386. /* u32DummyRead = fm3_FLASH_IF->FASZ; */
  387. 0x04, 0x4D, /* LDR.N R5, ??u32DummyRead */
  388. 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
  389. 0x36, 0x68, /* LDR R6, [R6] */
  390. 0x2E, 0x60, /* STR R6, [R5] */
  391. /* copy u32FlashResult to R3 for return */
  392. /* value */
  393. 0xDF, 0xF8, 0x08, 0x50, /* LDR.W R5, ??u32FlashResult */
  394. 0x2D, 0x68, /* LDR R5, [R5] */
  395. /* Breakpoint here */
  396. 0x00, 0xBE, /* BKPT #0 */
  397. /* The following address pointers assume, that the code is running from */
  398. /* address 0x1FFF8008. These address pointers will be patched, if a */
  399. /* different start address in RAM is used (e.g. for Flash type 2)! */
  400. 0x00, 0x80, 0xFF, 0x1F, /* u32DummyRead address in RAM (0x1FFF8000) */
  401. 0x04, 0x80, 0xFF, 0x1F /* u32FlashResult address in RAM (0x1FFF8004) */
  402. };
  403. LOG_INFO("Fujitsu MB9B500: FLASH Write ...");
  404. /* disable HW watchdog */
  405. retval = target_write_u32(target, 0x40011C00, 0x1ACCE551);
  406. if (retval != ERROR_OK)
  407. return retval;
  408. retval = target_write_u32(target, 0x40011C00, 0xE5331AAE);
  409. if (retval != ERROR_OK)
  410. return retval;
  411. retval = target_write_u32(target, 0x40011008, 0x00000000);
  412. if (retval != ERROR_OK)
  413. return retval;
  414. count = count / 2; /* number bytes -> number halfwords */
  415. /* check code alignment */
  416. if (offset & 0x1) {
  417. LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
  418. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  419. }
  420. /* allocate working area with flash programming code */
  421. if (target_alloc_working_area(target, sizeof(fm3_flash_write_code),
  422. &write_algorithm) != ERROR_OK) {
  423. LOG_WARNING("no working area available, can't do block memory writes");
  424. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  425. }
  426. retval = target_write_buffer(target, write_algorithm->address,
  427. sizeof(fm3_flash_write_code), fm3_flash_write_code);
  428. if (retval != ERROR_OK)
  429. return retval;
  430. /* memory buffer */
  431. while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
  432. buffer_size /= 2;
  433. if (buffer_size <= 256) {
  434. /* free working area, write algorithm already allocated */
  435. target_free_working_area(target, write_algorithm);
  436. LOG_WARNING("No large enough working area available, can't do block memory writes");
  437. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  438. }
  439. }
  440. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  441. armv7m_info.core_mode = ARM_MODE_THREAD;
  442. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* source start address */
  443. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* target start address */
  444. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* number of halfwords to program */
  445. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* Flash Sequence address 1 */
  446. init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* Flash Sequence address 1 */
  447. init_reg_param(&reg_params[5], "r5", 32, PARAM_IN); /* result */
  448. /* write code buffer and use Flash programming code within fm3 */
  449. /* Set breakpoint to 0 with time-out of 1000 ms */
  450. while (count > 0) {
  451. uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
  452. retval = target_write_buffer(target, write_algorithm->address, 8,
  453. fm3_flash_write_code);
  454. if (retval != ERROR_OK)
  455. break;
  456. /* Patching 'local variable address' for different RAM addresses */
  457. if (write_algorithm->address != 0x1FFF8008) {
  458. /* Algorithm: u32DummyRead: */
  459. retval = target_write_u32(target, (write_algorithm->address)
  460. + sizeof(fm3_flash_write_code) - 8, (write_algorithm->address) - 8);
  461. if (retval != ERROR_OK)
  462. break;
  463. /* Algorithm: u32FlashResult: */
  464. retval = target_write_u32(target, (write_algorithm->address)
  465. + sizeof(fm3_flash_write_code) - 4, (write_algorithm->address) - 4);
  466. if (retval != ERROR_OK)
  467. break;
  468. }
  469. retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
  470. if (retval != ERROR_OK)
  471. break;
  472. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  473. buf_set_u32(reg_params[1].value, 0, 32, address);
  474. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
  475. buf_set_u32(reg_params[3].value, 0, 32, u32FlashSeqAddress1);
  476. buf_set_u32(reg_params[4].value, 0, 32, u32FlashSeqAddress2);
  477. retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
  478. write_algorithm->address, 0, 1000, &armv7m_info);
  479. if (retval != ERROR_OK) {
  480. LOG_ERROR("Error executing fm3 Flash programming algorithm");
  481. retval = ERROR_FLASH_OPERATION_FAILED;
  482. break;
  483. }
  484. if (buf_get_u32(reg_params[5].value, 0, 32) != ERROR_OK) {
  485. LOG_ERROR("Fujitsu MB9[A/B]FXXX: Flash programming ERROR (Timeout) -> Reg R3: %x",
  486. buf_get_u32(reg_params[5].value, 0, 32));
  487. retval = ERROR_FLASH_OPERATION_FAILED;
  488. break;
  489. }
  490. buffer += thisrun_count * 2;
  491. address += thisrun_count * 2;
  492. count -= thisrun_count;
  493. }
  494. target_free_working_area(target, source);
  495. target_free_working_area(target, write_algorithm);
  496. destroy_reg_param(&reg_params[0]);
  497. destroy_reg_param(&reg_params[1]);
  498. destroy_reg_param(&reg_params[2]);
  499. destroy_reg_param(&reg_params[3]);
  500. destroy_reg_param(&reg_params[4]);
  501. destroy_reg_param(&reg_params[5]);
  502. return retval;
  503. }
  504. static int fm3_probe(struct flash_bank *bank)
  505. {
  506. struct fm3_flash_bank *fm3_info = bank->driver_priv;
  507. uint16_t num_pages;
  508. if (bank->target->state != TARGET_HALTED) {
  509. LOG_ERROR("Target not halted");
  510. return ERROR_TARGET_NOT_HALTED;
  511. }
  512. /*
  513. -- page-- start -- blocksize - mpu - totalFlash --
  514. page0 0x00000 16k
  515. page1 0x04000 16k
  516. page2 0x08000 96k ___ fxx3 128k Flash
  517. page3 0x20000 128k ___ fxx4 256k Flash
  518. page4 0x40000 128k ___ fxx5 384k Flash
  519. page5 0x60000 128k ___ fxx6 512k Flash
  520. -----------------------
  521. page6 0x80000 128k
  522. page7 0xa0000 128k ___ fxx7 256k Flash
  523. page8 0xc0000 128k
  524. page9 0xe0000 128k ___ fxx8 256k Flash
  525. */
  526. num_pages = 10; /* max number of Flash pages for malloc */
  527. fm3_info->probed = 0;
  528. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  529. bank->base = 0x00000000;
  530. bank->size = 32 * 1024; /* bytes */
  531. bank->sectors[0].offset = 0;
  532. bank->sectors[0].size = 16 * 1024;
  533. bank->sectors[0].is_erased = -1;
  534. bank->sectors[0].is_protected = -1;
  535. bank->sectors[1].offset = 0x4000;
  536. bank->sectors[1].size = 16 * 1024;
  537. bank->sectors[1].is_erased = -1;
  538. bank->sectors[1].is_protected = -1;
  539. if ((fm3_info->variant == mb9bfxx1)
  540. || (fm3_info->variant == mb9afxx1)) {
  541. num_pages = 3;
  542. bank->size = 64 * 1024; /* bytes */
  543. bank->num_sectors = num_pages;
  544. bank->sectors[2].offset = 0x8000;
  545. bank->sectors[2].size = 32 * 1024;
  546. bank->sectors[2].is_erased = -1;
  547. bank->sectors[2].is_protected = -1;
  548. }
  549. if ((fm3_info->variant == mb9bfxx2)
  550. || (fm3_info->variant == mb9bfxx4)
  551. || (fm3_info->variant == mb9bfxx5)
  552. || (fm3_info->variant == mb9bfxx6)
  553. || (fm3_info->variant == mb9bfxx7)
  554. || (fm3_info->variant == mb9bfxx8)
  555. || (fm3_info->variant == mb9afxx2)
  556. || (fm3_info->variant == mb9afxx4)
  557. || (fm3_info->variant == mb9afxx5)
  558. || (fm3_info->variant == mb9afxx6)
  559. || (fm3_info->variant == mb9afxx7)
  560. || (fm3_info->variant == mb9afxx8)) {
  561. num_pages = 3;
  562. bank->size = 128 * 1024; /* bytes */
  563. bank->num_sectors = num_pages;
  564. bank->sectors[2].offset = 0x8000;
  565. bank->sectors[2].size = 96 * 1024;
  566. bank->sectors[2].is_erased = -1;
  567. bank->sectors[2].is_protected = -1;
  568. }
  569. if ((fm3_info->variant == mb9bfxx4)
  570. || (fm3_info->variant == mb9bfxx5)
  571. || (fm3_info->variant == mb9bfxx6)
  572. || (fm3_info->variant == mb9bfxx7)
  573. || (fm3_info->variant == mb9bfxx8)
  574. || (fm3_info->variant == mb9afxx4)
  575. || (fm3_info->variant == mb9afxx5)
  576. || (fm3_info->variant == mb9afxx6)
  577. || (fm3_info->variant == mb9afxx7)
  578. || (fm3_info->variant == mb9afxx8)) {
  579. num_pages = 4;
  580. bank->size = 256 * 1024; /* bytes */
  581. bank->num_sectors = num_pages;
  582. bank->sectors[3].offset = 0x20000;
  583. bank->sectors[3].size = 128 * 1024;
  584. bank->sectors[3].is_erased = -1;
  585. bank->sectors[3].is_protected = -1;
  586. }
  587. if ((fm3_info->variant == mb9bfxx5)
  588. || (fm3_info->variant == mb9bfxx6)
  589. || (fm3_info->variant == mb9bfxx7)
  590. || (fm3_info->variant == mb9bfxx8)
  591. || (fm3_info->variant == mb9afxx5)
  592. || (fm3_info->variant == mb9afxx6)
  593. || (fm3_info->variant == mb9afxx7)
  594. || (fm3_info->variant == mb9afxx8)) {
  595. num_pages = 5;
  596. bank->size = 384 * 1024; /* bytes */
  597. bank->num_sectors = num_pages;
  598. bank->sectors[4].offset = 0x40000;
  599. bank->sectors[4].size = 128 * 1024;
  600. bank->sectors[4].is_erased = -1;
  601. bank->sectors[4].is_protected = -1;
  602. }
  603. if ((fm3_info->variant == mb9bfxx6)
  604. || (fm3_info->variant == mb9bfxx7)
  605. || (fm3_info->variant == mb9bfxx8)
  606. || (fm3_info->variant == mb9afxx6)
  607. || (fm3_info->variant == mb9afxx7)
  608. || (fm3_info->variant == mb9afxx8)) {
  609. num_pages = 6;
  610. bank->size = 512 * 1024; /* bytes */
  611. bank->num_sectors = num_pages;
  612. bank->sectors[5].offset = 0x60000;
  613. bank->sectors[5].size = 128 * 1024;
  614. bank->sectors[5].is_erased = -1;
  615. bank->sectors[5].is_protected = -1;
  616. }
  617. if ((fm3_info->variant == mb9bfxx7)
  618. || (fm3_info->variant == mb9bfxx8)
  619. || (fm3_info->variant == mb9afxx7)
  620. || (fm3_info->variant == mb9afxx8)) {
  621. num_pages = 8;
  622. bank->size = 768 * 1024; /* bytes */
  623. bank->num_sectors = num_pages;
  624. bank->sectors[6].offset = 0x80000;
  625. bank->sectors[6].size = 128 * 1024;
  626. bank->sectors[6].is_erased = -1;
  627. bank->sectors[6].is_protected = -1;
  628. bank->sectors[7].offset = 0xa0000;
  629. bank->sectors[7].size = 128 * 1024;
  630. bank->sectors[7].is_erased = -1;
  631. bank->sectors[7].is_protected = -1;
  632. }
  633. if ((fm3_info->variant == mb9bfxx8)
  634. || (fm3_info->variant == mb9afxx8)) {
  635. num_pages = 10;
  636. bank->size = 1024 * 1024; /* bytes */
  637. bank->num_sectors = num_pages;
  638. bank->sectors[8].offset = 0xc0000;
  639. bank->sectors[8].size = 128 * 1024;
  640. bank->sectors[8].is_erased = -1;
  641. bank->sectors[8].is_protected = -1;
  642. bank->sectors[9].offset = 0xe0000;
  643. bank->sectors[9].size = 128 * 1024;
  644. bank->sectors[9].is_erased = -1;
  645. bank->sectors[9].is_protected = -1;
  646. }
  647. fm3_info->probed = 1;
  648. return ERROR_OK;
  649. }
  650. static int fm3_auto_probe(struct flash_bank *bank)
  651. {
  652. struct fm3_flash_bank *fm3_info = bank->driver_priv;
  653. if (fm3_info->probed)
  654. return ERROR_OK;
  655. return fm3_probe(bank);
  656. }
  657. static int fm3_info(struct flash_bank *bank, char *buf, int buf_size)
  658. {
  659. snprintf(buf, buf_size, "Fujitsu fm3 Device does not support Chip-ID (Type unknown)");
  660. return ERROR_OK;
  661. }
  662. /* Chip erase */
  663. static int fm3_chip_erase(struct flash_bank *bank)
  664. {
  665. struct target *target = bank->target;
  666. struct fm3_flash_bank *fm3_info2 = bank->driver_priv;
  667. int retval = ERROR_OK;
  668. uint32_t u32DummyRead;
  669. uint32_t u32FlashType;
  670. uint32_t u32FlashSeqAddress1;
  671. uint32_t u32FlashSeqAddress2;
  672. u32FlashType = (uint32_t) fm3_info2->flashtype;
  673. if (u32FlashType == fm3_flash_type1) {
  674. LOG_INFO("*** Erasing mb9bfxxx type");
  675. u32FlashSeqAddress1 = 0x00001550;
  676. u32FlashSeqAddress2 = 0x00000AA8;
  677. } else if (u32FlashType == fm3_flash_type2) {
  678. LOG_INFO("*** Erasing mb9afxxx type");
  679. u32FlashSeqAddress1 = 0x00000AA8;
  680. u32FlashSeqAddress2 = 0x00000554;
  681. } else {
  682. LOG_ERROR("Flash/Device type unknown!");
  683. return ERROR_FLASH_OPERATION_FAILED;
  684. }
  685. if (target->state != TARGET_HALTED) {
  686. LOG_ERROR("Target not halted");
  687. return ERROR_TARGET_NOT_HALTED;
  688. }
  689. LOG_INFO("Fujitsu MB9[AB]xxx: Chip Erase ... (may take several seconds)");
  690. /* Implement Flash chip erase (mass erase) completely on host */
  691. /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
  692. retval = target_write_u32(target, 0x40000000, 0x0001);
  693. if (retval != ERROR_OK)
  694. return retval;
  695. /* dummy read of FASZR */
  696. retval = target_read_u32(target, 0x40000000, &u32DummyRead);
  697. if (retval != ERROR_OK)
  698. return retval;
  699. /* Flash unlock sequence */
  700. retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA);
  701. if (retval != ERROR_OK)
  702. return retval;
  703. retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055);
  704. if (retval != ERROR_OK)
  705. return retval;
  706. retval = target_write_u16(target, u32FlashSeqAddress1, 0x0080);
  707. if (retval != ERROR_OK)
  708. return retval;
  709. retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA);
  710. if (retval != ERROR_OK)
  711. return retval;
  712. retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055);
  713. if (retval != ERROR_OK)
  714. return retval;
  715. /* Chip Erase command (0x0010) */
  716. retval = target_write_u16(target, u32FlashSeqAddress1, 0x0010);
  717. if (retval != ERROR_OK)
  718. return retval;
  719. retval = fm3_busy_wait(target, u32FlashSeqAddress2, 20000); /* 20s timeout */
  720. if (retval != ERROR_OK)
  721. return retval;
  722. /* FASZR = 0x02, Re-enables CPU Run Mode (32-bit Flash access) */
  723. retval = target_write_u32(target, 0x40000000, 0x0002);
  724. if (retval != ERROR_OK)
  725. return retval;
  726. retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
  727. return retval;
  728. }
  729. COMMAND_HANDLER(fm3_handle_chip_erase_command)
  730. {
  731. int i;
  732. if (CMD_ARGC < 1)
  733. return ERROR_COMMAND_SYNTAX_ERROR;
  734. struct flash_bank *bank;
  735. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  736. if (ERROR_OK != retval)
  737. return retval;
  738. if (fm3_chip_erase(bank) == ERROR_OK) {
  739. /* set all sectors as erased */
  740. for (i = 0; i < bank->num_sectors; i++)
  741. bank->sectors[i].is_erased = 1;
  742. command_print(CMD_CTX, "fm3 chip erase complete");
  743. } else {
  744. command_print(CMD_CTX, "fm3 chip erase failed");
  745. }
  746. return ERROR_OK;
  747. }
  748. static const struct command_registration fm3_exec_command_handlers[] = {
  749. {
  750. .name = "chip_erase",
  751. .usage = "<bank>",
  752. .handler = fm3_handle_chip_erase_command,
  753. .mode = COMMAND_EXEC,
  754. .help = "Erase entire Flash device.",
  755. },
  756. COMMAND_REGISTRATION_DONE
  757. };
  758. static const struct command_registration fm3_command_handlers[] = {
  759. {
  760. .name = "fm3",
  761. .mode = COMMAND_ANY,
  762. .help = "fm3 Flash command group",
  763. .usage = "",
  764. .chain = fm3_exec_command_handlers,
  765. },
  766. COMMAND_REGISTRATION_DONE
  767. };
  768. struct flash_driver fm3_flash = {
  769. .name = "fm3",
  770. .commands = fm3_command_handlers,
  771. .flash_bank_command = fm3_flash_bank_command,
  772. .erase = fm3_erase,
  773. .write = fm3_write_block,
  774. .probe = fm3_probe,
  775. .auto_probe = fm3_auto_probe,
  776. .erase_check = default_flash_blank_check,
  777. .info = fm3_info,
  778. };