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  1. /***************************************************************************
  2. * Copyright (C) 2008 by *
  3. * Karl RobinSod <karl.robinsod@gmail.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. /***************************************************************************
  21. * There are some things to notice
  22. *
  23. * You need to unprotect flash sectors each time you connect the OpenOCD
  24. * Dumping 1MB takes about 60 Seconds
  25. * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
  26. * Writing 1MB takes 88 seconds
  27. *
  28. ***************************************************************************/
  29. #ifdef HAVE_CONFIG_H
  30. #include "config.h"
  31. #endif
  32. #include "imp.h"
  33. #include <helper/binarybuffer.h>
  34. #define LOAD_TIMER_ERASE 0
  35. #define LOAD_TIMER_WRITE 1
  36. #define FLASH_PAGE_SIZE 512
  37. /* LPC288X control registers */
  38. #define DBGU_CIDR 0x8000507C
  39. /* LPC288X flash registers */
  40. #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
  41. #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
  42. #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
  43. #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
  44. #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0
  45. **/
  46. #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
  47. #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
  48. #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
  49. #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
  50. #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
  51. #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
  52. #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power
  53. *savings. R/W 1*/
  54. #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from
  55. *Power Down mode. R/W -*/
  56. /* F_CTRL bits */
  57. #define FC_CS 0x0001
  58. #define FC_FUNC 0x0002
  59. #define FC_WEN 0x0004
  60. #define FC_RD_LATCH 0x0020
  61. #define FC_PROTECT 0x0080
  62. #define FC_SET_DATA 0x0400
  63. #define FC_RSSL 0x0800
  64. #define FC_PROG_REQ 0x1000
  65. #define FC_CLR_BUF 0x4000
  66. #define FC_LOAD_REQ 0x8000
  67. /* F_STAT bits */
  68. #define FS_DONE 0x0001
  69. #define FS_PROGGNT 0x0002
  70. #define FS_RDY 0x0004
  71. #define FS_ERR 0x0020
  72. /* F_PROG_TIME */
  73. #define FPT_TIME_MASK 0x7FFF
  74. #define FPT_ENABLE 0x8000
  75. /* F_WAIT */
  76. #define FW_WAIT_STATES_MASK 0x00FF
  77. #define FW_SET_MASK 0xC000
  78. /* F_CLK_TIME */
  79. #define FCT_CLK_DIV_MASK 0x0FFF
  80. struct lpc288x_flash_bank {
  81. uint32_t working_area;
  82. uint32_t working_area_size;
  83. /* chip id register */
  84. uint32_t cidr;
  85. const char *target_name;
  86. uint32_t cclk;
  87. uint32_t sector_size_break;
  88. };
  89. static uint32_t lpc288x_wait_status_busy(struct flash_bank *bank, int timeout);
  90. static void lpc288x_load_timer(int erase, struct target *target);
  91. static void lpc288x_set_flash_clk(struct flash_bank *bank);
  92. static uint32_t lpc288x_system_ready(struct flash_bank *bank);
  93. static uint32_t lpc288x_wait_status_busy(struct flash_bank *bank, int timeout)
  94. {
  95. uint32_t status;
  96. struct target *target = bank->target;
  97. do {
  98. alive_sleep(1);
  99. timeout--;
  100. target_read_u32(target, F_STAT, &status);
  101. } while (((status & FS_DONE) == 0) && timeout);
  102. if (timeout == 0) {
  103. LOG_DEBUG("Timedout!");
  104. return ERROR_FLASH_OPERATION_FAILED;
  105. }
  106. return ERROR_OK;
  107. }
  108. /* Read device id register and fill in driver info structure */
  109. static int lpc288x_read_part_info(struct flash_bank *bank)
  110. {
  111. struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
  112. struct target *target = bank->target;
  113. uint32_t cidr;
  114. int i = 0;
  115. uint32_t offset;
  116. if (lpc288x_info->cidr == 0x0102100A)
  117. return ERROR_OK;/* already probed, multiple probes may cause memory leak, not
  118. *allowed */
  119. /* Read and parse chip identification register */
  120. target_read_u32(target, DBGU_CIDR, &cidr);
  121. if (cidr != 0x0102100A) {
  122. LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32 ")", cidr);
  123. return ERROR_FLASH_OPERATION_FAILED;
  124. }
  125. lpc288x_info->cidr = cidr;
  126. lpc288x_info->sector_size_break = 0x000F0000;
  127. lpc288x_info->target_name = "LPC288x";
  128. /* setup the sector info... */
  129. offset = bank->base;
  130. bank->num_sectors = 23;
  131. bank->sectors = malloc(sizeof(struct flash_sector) * 23);
  132. for (i = 0; i < 15; i++) {
  133. bank->sectors[i].offset = offset;
  134. bank->sectors[i].size = 64 * 1024;
  135. offset += bank->sectors[i].size;
  136. bank->sectors[i].is_erased = -1;
  137. bank->sectors[i].is_protected = 1;
  138. }
  139. for (i = 15; i < 23; i++) {
  140. bank->sectors[i].offset = offset;
  141. bank->sectors[i].size = 8 * 1024;
  142. offset += bank->sectors[i].size;
  143. bank->sectors[i].is_erased = -1;
  144. bank->sectors[i].is_protected = 1;
  145. }
  146. return ERROR_OK;
  147. }
  148. static int lpc288x_protect_check(struct flash_bank *bank)
  149. {
  150. return ERROR_OK;
  151. }
  152. /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
  153. FLASH_BANK_COMMAND_HANDLER(lpc288x_flash_bank_command)
  154. {
  155. struct lpc288x_flash_bank *lpc288x_info;
  156. if (CMD_ARGC < 6)
  157. return ERROR_COMMAND_SYNTAX_ERROR;
  158. lpc288x_info = malloc(sizeof(struct lpc288x_flash_bank));
  159. bank->driver_priv = lpc288x_info;
  160. /* part wasn't probed for info yet */
  161. lpc288x_info->cidr = 0;
  162. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], lpc288x_info->cclk);
  163. return ERROR_OK;
  164. }
  165. /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
  166. * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
  167. * AHB = 12 MHz ?
  168. * 12000000/66000 = 182
  169. * CLK_DIV = 60 ? */
  170. static void lpc288x_set_flash_clk(struct flash_bank *bank)
  171. {
  172. uint32_t clk_time;
  173. struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
  174. clk_time = (lpc288x_info->cclk / 66000) / 3;
  175. target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN);
  176. target_write_u32(bank->target, F_CLK_TIME, clk_time);
  177. }
  178. /* AHB tcyc (in ns) 83 ns
  179. * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
  180. * = 9412 (9500) (AN10548 9375)
  181. * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
  182. * = 23 (75) (AN10548 72 - is this wrong?)
  183. * TODO: Sort out timing calcs ;) */
  184. static void lpc288x_load_timer(int erase, struct target *target)
  185. {
  186. if (erase == LOAD_TIMER_ERASE)
  187. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
  188. else
  189. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
  190. }
  191. static uint32_t lpc288x_system_ready(struct flash_bank *bank)
  192. {
  193. struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
  194. if (lpc288x_info->cidr == 0)
  195. return ERROR_FLASH_BANK_NOT_PROBED;
  196. if (bank->target->state != TARGET_HALTED) {
  197. LOG_ERROR("Target not halted");
  198. return ERROR_TARGET_NOT_HALTED;
  199. }
  200. return ERROR_OK;
  201. }
  202. static int lpc288x_erase_check(struct flash_bank *bank)
  203. {
  204. uint32_t status = lpc288x_system_ready(bank); /* probed? halted? */
  205. if (status != ERROR_OK) {
  206. LOG_INFO("Processor not halted/not probed");
  207. return status;
  208. }
  209. return ERROR_OK;
  210. }
  211. static int lpc288x_erase(struct flash_bank *bank, int first, int last)
  212. {
  213. uint32_t status;
  214. int sector;
  215. struct target *target = bank->target;
  216. status = lpc288x_system_ready(bank); /* probed? halted? */
  217. if (status != ERROR_OK)
  218. return status;
  219. if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
  220. LOG_INFO("Bad sector range");
  221. return ERROR_FLASH_SECTOR_INVALID;
  222. }
  223. /* Configure the flash controller timing */
  224. lpc288x_set_flash_clk(bank);
  225. for (sector = first; sector <= last; sector++) {
  226. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  227. return ERROR_FLASH_OPERATION_FAILED;
  228. lpc288x_load_timer(LOAD_TIMER_ERASE, target);
  229. target_write_u32(target, bank->sectors[sector].offset, 0x00);
  230. target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS);
  231. }
  232. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  233. return ERROR_FLASH_OPERATION_FAILED;
  234. return ERROR_OK;
  235. }
  236. static int lpc288x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  237. {
  238. uint8_t page_buffer[FLASH_PAGE_SIZE];
  239. uint32_t status, source_offset, dest_offset;
  240. struct target *target = bank->target;
  241. uint32_t bytes_remaining = count;
  242. uint32_t first_sector, last_sector, sector, page;
  243. int i;
  244. /* probed? halted? */
  245. status = lpc288x_system_ready(bank);
  246. if (status != ERROR_OK)
  247. return status;
  248. /* Initialise search indices */
  249. first_sector = last_sector = 0xffffffff;
  250. /* validate the write range... */
  251. for (i = 0; i < bank->num_sectors; i++) {
  252. if ((offset >= bank->sectors[i].offset) &&
  253. (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
  254. (first_sector == 0xffffffff)) {
  255. first_sector = i;
  256. /* all writes must start on a sector boundary... */
  257. if (offset % bank->sectors[i].size) {
  258. LOG_INFO(
  259. "offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
  260. offset,
  261. bank->sectors[i].size);
  262. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  263. }
  264. }
  265. if (((offset + count) > bank->sectors[i].offset) &&
  266. ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
  267. (last_sector == 0xffffffff))
  268. last_sector = i;
  269. }
  270. /* Range check... */
  271. if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
  272. LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
  273. return ERROR_FLASH_DST_OUT_OF_BANK;
  274. }
  275. /* Configure the flash controller timing */
  276. lpc288x_set_flash_clk(bank);
  277. /* initialise the offsets */
  278. source_offset = 0;
  279. dest_offset = 0;
  280. for (sector = first_sector; sector <= last_sector; sector++) {
  281. for (page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++) {
  282. if (bytes_remaining == 0) {
  283. count = 0;
  284. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  285. } else if (bytes_remaining < FLASH_PAGE_SIZE) {
  286. count = bytes_remaining;
  287. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  288. memcpy(page_buffer, &buffer[source_offset], count);
  289. } else {
  290. count = FLASH_PAGE_SIZE;
  291. memcpy(page_buffer, &buffer[source_offset], count);
  292. }
  293. /* Wait for flash to become ready */
  294. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  295. return ERROR_FLASH_OPERATION_FAILED;
  296. /* fill flash data latches with 1's */
  297. target_write_u32(target, F_CTRL, FC_CS | FC_SET_DATA | FC_WEN | FC_FUNC);
  298. target_write_u32(target, F_CTRL, FC_CS | FC_WEN | FC_FUNC);
  299. /*would be better to use the clean target_write_buffer() interface but
  300. * it seems not to be a LOT slower....
  301. * bulk_write_memory() is no quicker :(*/
  302. #if 1
  303. if (target_write_memory(target, offset + dest_offset, 4, 128,
  304. page_buffer) != ERROR_OK) {
  305. LOG_ERROR("Write failed s %" PRIx32 " p %" PRIx32 "", sector, page);
  306. return ERROR_FLASH_OPERATION_FAILED;
  307. }
  308. #else
  309. if (target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE,
  310. page_buffer) != ERROR_OK) {
  311. LOG_INFO("Write to flash buffer failed");
  312. return ERROR_FLASH_OPERATION_FAILED;
  313. }
  314. #endif
  315. dest_offset += FLASH_PAGE_SIZE;
  316. source_offset += count;
  317. bytes_remaining -= count;
  318. lpc288x_load_timer(LOAD_TIMER_WRITE, target);
  319. target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC |
  320. FC_CS);
  321. }
  322. }
  323. return ERROR_OK;
  324. }
  325. static int lpc288x_probe(struct flash_bank *bank)
  326. {
  327. /* we only deal with LPC2888 so flash config is fixed */
  328. struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
  329. int retval;
  330. if (lpc288x_info->cidr != 0)
  331. return ERROR_OK;/* already probed */
  332. if (bank->target->state != TARGET_HALTED) {
  333. LOG_ERROR("Target not halted");
  334. return ERROR_TARGET_NOT_HALTED;
  335. }
  336. retval = lpc288x_read_part_info(bank);
  337. if (retval != ERROR_OK)
  338. return retval;
  339. return ERROR_OK;
  340. }
  341. static int lpc288x_info(struct flash_bank *bank, char *buf, int buf_size)
  342. {
  343. snprintf(buf, buf_size, "lpc288x flash driver");
  344. return ERROR_OK;
  345. }
  346. static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last)
  347. {
  348. int lockregion, status;
  349. uint32_t value;
  350. struct target *target = bank->target;
  351. /* probed? halted? */
  352. status = lpc288x_system_ready(bank);
  353. if (status != ERROR_OK)
  354. return status;
  355. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  356. return ERROR_FLASH_SECTOR_INVALID;
  357. /* Configure the flash controller timing */
  358. lpc288x_set_flash_clk(bank);
  359. for (lockregion = first; lockregion <= last; lockregion++) {
  360. if (set) {
  361. /* write an odd value to base addy to protect... */
  362. value = 0x01;
  363. } else {
  364. /* write an even value to base addy to unprotect... */
  365. value = 0x00;
  366. }
  367. target_write_u32(target, bank->sectors[lockregion].offset, value);
  368. target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC |
  369. FC_CS);
  370. }
  371. return ERROR_OK;
  372. }
  373. struct flash_driver lpc288x_flash = {
  374. .name = "lpc288x",
  375. .flash_bank_command = lpc288x_flash_bank_command,
  376. .erase = lpc288x_erase,
  377. .protect = lpc288x_protect,
  378. .write = lpc288x_write,
  379. .read = default_flash_read,
  380. .probe = lpc288x_probe,
  381. .auto_probe = lpc288x_probe,
  382. .erase_check = lpc288x_erase_check,
  383. .protect_check = lpc288x_protect_check,
  384. .info = lpc288x_info,
  385. };