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  1. /***************************************************************************
  2. * Copyright (C) 2012 by George Harris *
  3. * george@luminairecoffee.com *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "imp.h"
  24. #include "spi.h"
  25. #include <jtag/jtag.h>
  26. #include <helper/time_support.h>
  27. #include <target/algorithm.h>
  28. #include <target/armv7m.h>
  29. /* Offsets from ssp_base into config & data registers */
  30. #define SSP_CR0 (0x00) /* Control register 0 */
  31. #define SSP_CR1 (0x04) /* Control register 1 */
  32. #define SSP_DATA (0x08) /* Data register (TX and RX) */
  33. #define SSP_SR (0x0C) /* Status register */
  34. #define SSP_CPSR (0x10) /* Clock prescale register */
  35. /* Status register fields */
  36. #define SSP_BSY (0x00000010)
  37. /* Timeout in ms */
  38. #define SSP_CMD_TIMEOUT (100)
  39. #define SSP_PROBE_TIMEOUT (100)
  40. #define SSP_MAX_TIMEOUT (3000)
  41. struct lpcspifi_flash_bank {
  42. int probed;
  43. uint32_t ssp_base;
  44. uint32_t io_base;
  45. uint32_t ioconfig_base;
  46. uint32_t bank_num;
  47. uint32_t max_spi_clock_mhz;
  48. struct flash_device *dev;
  49. };
  50. struct lpcspifi_target {
  51. char *name;
  52. uint32_t tap_idcode;
  53. uint32_t spifi_base;
  54. uint32_t ssp_base;
  55. uint32_t io_base;
  56. uint32_t ioconfig_base; /* base address for the port word pin registers */
  57. };
  58. static struct lpcspifi_target target_devices[] = {
  59. /* name, tap_idcode, spifi_base, ssp_base, io_base, ioconfig_base */
  60. { "LPC43xx/18xx", 0x4ba00477, 0x14000000, 0x40083000, 0x400F4000, 0x40086000 },
  61. { NULL, 0, 0, 0, 0, 0 }
  62. };
  63. /* flash_bank lpcspifi <base> <size> <chip_width> <bus_width> <target>
  64. */
  65. FLASH_BANK_COMMAND_HANDLER(lpcspifi_flash_bank_command)
  66. {
  67. struct lpcspifi_flash_bank *lpcspifi_info;
  68. if (CMD_ARGC < 6)
  69. return ERROR_COMMAND_SYNTAX_ERROR;
  70. lpcspifi_info = malloc(sizeof(struct lpcspifi_flash_bank));
  71. if (lpcspifi_info == NULL) {
  72. LOG_ERROR("not enough memory");
  73. return ERROR_FAIL;
  74. }
  75. bank->driver_priv = lpcspifi_info;
  76. lpcspifi_info->probed = 0;
  77. return ERROR_OK;
  78. }
  79. static inline int ioconfig_write_reg(struct target *target, uint32_t ioconfig_base, uint32_t offset, uint32_t value)
  80. {
  81. return target_write_u32(target, ioconfig_base + offset, value);
  82. }
  83. static inline int ssp_write_reg(struct target *target, uint32_t ssp_base, uint32_t offset, uint32_t value)
  84. {
  85. return target_write_u32(target, ssp_base + offset, value);
  86. }
  87. static inline int io_write_reg(struct target *target, uint32_t io_base, uint32_t offset, uint32_t value)
  88. {
  89. return target_write_u32(target, io_base + offset, value);
  90. }
  91. static inline int ssp_read_reg(struct target *target, uint32_t ssp_base, uint32_t offset, uint32_t *value)
  92. {
  93. return target_read_u32(target, ssp_base + offset, value);
  94. }
  95. static int ssp_setcs(struct target *target, uint32_t io_base, unsigned int value)
  96. {
  97. return io_write_reg(target, io_base, 0x12ac, value ? 0xffffffff : 0x00000000);
  98. }
  99. /* Poll the SSP busy flag. When this comes back as 0, the transfer is complete
  100. * and the controller is idle. */
  101. static int poll_ssp_busy(struct target *target, uint32_t ssp_base, int timeout)
  102. {
  103. long long endtime;
  104. uint32_t value;
  105. int retval;
  106. retval = ssp_read_reg(target, ssp_base, SSP_SR, &value);
  107. if ((retval == ERROR_OK) && (value & SSP_BSY) == 0)
  108. return ERROR_OK;
  109. else if (retval != ERROR_OK)
  110. return retval;
  111. endtime = timeval_ms() + timeout;
  112. do {
  113. alive_sleep(1);
  114. retval = ssp_read_reg(target, ssp_base, SSP_SR, &value);
  115. if ((retval == ERROR_OK) && (value & SSP_BSY) == 0)
  116. return ERROR_OK;
  117. else if (retval != ERROR_OK)
  118. return retval;
  119. } while (timeval_ms() < endtime);
  120. LOG_ERROR("Timeout while polling BSY");
  121. return ERROR_FLASH_OPERATION_FAILED;
  122. }
  123. /* Un-initialize the ssp module and initialize the SPIFI module */
  124. static int lpcspifi_set_hw_mode(struct flash_bank *bank)
  125. {
  126. struct target *target = bank->target;
  127. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  128. uint32_t ssp_base = lpcspifi_info->ssp_base;
  129. struct armv7m_algorithm armv7m_info;
  130. struct working_area *spifi_init_algorithm;
  131. struct reg_param reg_params[1];
  132. int retval = ERROR_OK;
  133. LOG_DEBUG("Uninitializing LPC43xx SSP");
  134. /* Turn off the SSP module */
  135. retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000000);
  136. if (retval != ERROR_OK)
  137. return retval;
  138. /* see contrib/loaders/flash/lpcspifi_init.S for src */
  139. static const uint8_t spifi_init_code[] = {
  140. 0x4f, 0xea, 0x00, 0x08, 0xa1, 0xb0, 0x00, 0xaf,
  141. 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
  142. 0x4f, 0xf0, 0xf3, 0x02, 0xc3, 0xf8, 0x8c, 0x21,
  143. 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
  144. 0x4f, 0xf4, 0xc0, 0x42, 0xc4, 0xf2, 0x08, 0x02,
  145. 0x4f, 0xf4, 0xc0, 0x41, 0xc4, 0xf2, 0x08, 0x01,
  146. 0x4f, 0xf4, 0xc0, 0x40, 0xc4, 0xf2, 0x08, 0x00,
  147. 0x4f, 0xf0, 0xd3, 0x04, 0xc0, 0xf8, 0x9c, 0x41,
  148. 0x20, 0x46, 0xc1, 0xf8, 0x98, 0x01, 0x01, 0x46,
  149. 0xc2, 0xf8, 0x94, 0x11, 0xc3, 0xf8, 0x90, 0x11,
  150. 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
  151. 0x4f, 0xf0, 0x13, 0x02, 0xc3, 0xf8, 0xa0, 0x21,
  152. 0x40, 0xf2, 0x18, 0x13, 0xc1, 0xf2, 0x40, 0x03,
  153. 0x1b, 0x68, 0x1c, 0x68, 0x40, 0xf2, 0xb4, 0x30,
  154. 0xc1, 0xf2, 0x00, 0x00, 0x4f, 0xf0, 0x03, 0x01,
  155. 0x4f, 0xf0, 0xc0, 0x02, 0x4f, 0xea, 0x08, 0x03,
  156. 0xa0, 0x47, 0x00, 0xf0, 0x00, 0xb8, 0x00, 0xbe
  157. };
  158. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  159. armv7m_info.core_mode = ARM_MODE_THREAD;
  160. LOG_DEBUG("Allocating working area for SPIFI init algorithm");
  161. /* Get memory for spifi initialization algorithm */
  162. retval = target_alloc_working_area(target, sizeof(spifi_init_code),
  163. &spifi_init_algorithm);
  164. if (retval != ERROR_OK) {
  165. LOG_ERROR("Insufficient working area to initialize SPIFI "\
  166. "module. You must allocate at least %zdB of working "\
  167. "area in order to use this driver.",
  168. sizeof(spifi_init_code)
  169. );
  170. return retval;
  171. }
  172. LOG_DEBUG("Writing algorithm to working area at 0x%08x",
  173. spifi_init_algorithm->address);
  174. /* Write algorithm to working area */
  175. retval = target_write_buffer(target,
  176. spifi_init_algorithm->address,
  177. sizeof(spifi_init_code),
  178. spifi_init_code
  179. );
  180. if (retval != ERROR_OK) {
  181. target_free_working_area(target, spifi_init_algorithm);
  182. return retval;
  183. }
  184. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* spifi clk speed */
  185. /* For now, the algorithm will set up the SPIFI module
  186. * @ the IRC clock speed. In the future, it could be made
  187. * a bit smarter to use other clock sources if the user has
  188. * already configured them in order to speed up memory-
  189. * mapped reads. */
  190. buf_set_u32(reg_params[0].value, 0, 32, 12);
  191. /* Run the algorithm */
  192. LOG_DEBUG("Running SPIFI init algorithm");
  193. retval = target_run_algorithm(target, 0 , NULL, 1, reg_params,
  194. spifi_init_algorithm->address,
  195. spifi_init_algorithm->address + sizeof(spifi_init_code) - 2,
  196. 1000, &armv7m_info);
  197. if (retval != ERROR_OK)
  198. LOG_ERROR("Error executing SPIFI init algorithm");
  199. target_free_working_area(target, spifi_init_algorithm);
  200. destroy_reg_param(&reg_params[0]);
  201. return retval;
  202. }
  203. /* Initialize the ssp module */
  204. static int lpcspifi_set_sw_mode(struct flash_bank *bank)
  205. {
  206. struct target *target = bank->target;
  207. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  208. uint32_t ssp_base = lpcspifi_info->ssp_base;
  209. uint32_t io_base = lpcspifi_info->io_base;
  210. uint32_t ioconfig_base = lpcspifi_info->ioconfig_base;
  211. int retval = ERROR_OK;
  212. /* Re-initialize SPIFI. There are a couple of errata on this, so this makes
  213. sure that nothing's in an unhappy state. */
  214. retval = lpcspifi_set_hw_mode(bank);
  215. /* If we couldn't initialize hardware mode, don't even bother continuing */
  216. if (retval != ERROR_OK)
  217. return retval;
  218. /* Initialize the pins */
  219. retval = ioconfig_write_reg(target, ioconfig_base, 0x194, 0x00000040);
  220. if (retval == ERROR_OK)
  221. retval = ioconfig_write_reg(target, ioconfig_base, 0x1a0, 0x00000044);
  222. if (retval == ERROR_OK)
  223. retval = ioconfig_write_reg(target, ioconfig_base, 0x190, 0x00000040);
  224. if (retval == ERROR_OK)
  225. retval = ioconfig_write_reg(target, ioconfig_base, 0x19c, 0x000000ed);
  226. if (retval == ERROR_OK)
  227. retval = ioconfig_write_reg(target, ioconfig_base, 0x198, 0x000000ed);
  228. if (retval == ERROR_OK)
  229. retval = ioconfig_write_reg(target, ioconfig_base, 0x18c, 0x000000ea);
  230. /* Set CS high & as an output */
  231. if (retval == ERROR_OK)
  232. retval = io_write_reg(target, io_base, 0x12ac, 0xffffffff);
  233. if (retval == ERROR_OK)
  234. retval = io_write_reg(target, io_base, 0x2014, 0x00000800);
  235. /* Initialize the module */
  236. if (retval == ERROR_OK)
  237. retval = ssp_write_reg(target, ssp_base, SSP_CR0, 0x00000007);
  238. if (retval == ERROR_OK)
  239. retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000000);
  240. if (retval == ERROR_OK)
  241. retval = ssp_write_reg(target, ssp_base, SSP_CPSR, 0x00000008);
  242. if (retval == ERROR_OK)
  243. retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000002);
  244. /* If something didn't work out, attempt to return SPIFI to HW mode */
  245. if (retval != ERROR_OK)
  246. lpcspifi_set_hw_mode(bank);
  247. return retval;
  248. }
  249. /* Read the status register of the external SPI flash chip. */
  250. static int read_status_reg(struct flash_bank *bank, uint32_t *status)
  251. {
  252. struct target *target = bank->target;
  253. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  254. uint32_t ssp_base = lpcspifi_info->ssp_base;
  255. uint32_t io_base = lpcspifi_info->io_base;
  256. uint32_t value;
  257. int retval = ERROR_OK;
  258. retval = ssp_setcs(target, io_base, 0);
  259. if (retval == ERROR_OK)
  260. retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_READ_STATUS);
  261. if (retval == ERROR_OK)
  262. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  263. if (retval == ERROR_OK)
  264. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  265. /* Dummy write to clock in the register */
  266. if (retval == ERROR_OK)
  267. retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
  268. if (retval == ERROR_OK)
  269. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  270. if (retval == ERROR_OK)
  271. retval = ssp_setcs(target, io_base, 1);
  272. if (retval == ERROR_OK)
  273. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  274. if (retval == ERROR_OK)
  275. *status = value;
  276. return retval;
  277. }
  278. /* check for BSY bit in flash status register */
  279. /* timeout in ms */
  280. static int wait_till_ready(struct flash_bank *bank, int timeout)
  281. {
  282. uint32_t status;
  283. int retval;
  284. long long endtime;
  285. endtime = timeval_ms() + timeout;
  286. do {
  287. /* read flash status register */
  288. retval = read_status_reg(bank, &status);
  289. if (retval != ERROR_OK)
  290. return retval;
  291. if ((status & SPIFLASH_BSY_BIT) == 0)
  292. return ERROR_OK;
  293. alive_sleep(1);
  294. } while (timeval_ms() < endtime);
  295. LOG_ERROR("timeout waiting for flash to finish write/erase operation");
  296. return ERROR_FAIL;
  297. }
  298. /* Send "write enable" command to SPI flash chip. */
  299. static int lpcspifi_write_enable(struct flash_bank *bank)
  300. {
  301. struct target *target = bank->target;
  302. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  303. uint32_t ssp_base = lpcspifi_info->ssp_base;
  304. uint32_t io_base = lpcspifi_info->io_base;
  305. uint32_t status, value;
  306. int retval = ERROR_OK;
  307. retval = ssp_setcs(target, io_base, 0);
  308. if (retval == ERROR_OK)
  309. retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_WRITE_ENABLE);
  310. if (retval == ERROR_OK)
  311. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  312. if (retval == ERROR_OK)
  313. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  314. if (retval == ERROR_OK)
  315. retval = ssp_setcs(target, io_base, 1);
  316. /* read flash status register */
  317. if (retval == ERROR_OK)
  318. retval = read_status_reg(bank, &status);
  319. if (retval != ERROR_OK)
  320. return retval;
  321. /* Check write enabled */
  322. if ((status & SPIFLASH_WE_BIT) == 0) {
  323. LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
  324. return ERROR_FAIL;
  325. }
  326. return retval;
  327. }
  328. static int lpcspifi_bulk_erase(struct flash_bank *bank)
  329. {
  330. struct target *target = bank->target;
  331. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  332. uint32_t ssp_base = lpcspifi_info->ssp_base;
  333. uint32_t io_base = lpcspifi_info->io_base;
  334. uint32_t value;
  335. int retval = ERROR_OK;
  336. retval = lpcspifi_set_sw_mode(bank);
  337. if (retval == ERROR_OK)
  338. retval = lpcspifi_write_enable(bank);
  339. /* send SPI command "bulk erase" */
  340. if (retval == ERROR_OK)
  341. ssp_setcs(target, io_base, 0);
  342. if (retval == ERROR_OK)
  343. retval = ssp_write_reg(target, ssp_base, SSP_DATA, lpcspifi_info->dev->chip_erase_cmd);
  344. if (retval == ERROR_OK)
  345. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  346. if (retval == ERROR_OK)
  347. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  348. if (retval == ERROR_OK)
  349. retval = ssp_setcs(target, io_base, 1);
  350. /* poll flash BSY for self-timed bulk erase */
  351. if (retval == ERROR_OK)
  352. retval = wait_till_ready(bank, bank->num_sectors*SSP_MAX_TIMEOUT);
  353. return retval;
  354. }
  355. static int lpcspifi_erase(struct flash_bank *bank, int first, int last)
  356. {
  357. struct target *target = bank->target;
  358. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  359. struct reg_param reg_params[4];
  360. struct armv7m_algorithm armv7m_info;
  361. struct working_area *erase_algorithm;
  362. int retval = ERROR_OK;
  363. int sector;
  364. LOG_DEBUG("erase from sector %d to sector %d", first, last);
  365. if (target->state != TARGET_HALTED) {
  366. LOG_ERROR("Target not halted");
  367. return ERROR_TARGET_NOT_HALTED;
  368. }
  369. if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
  370. LOG_ERROR("Flash sector invalid");
  371. return ERROR_FLASH_SECTOR_INVALID;
  372. }
  373. if (!(lpcspifi_info->probed)) {
  374. LOG_ERROR("Flash bank not probed");
  375. return ERROR_FLASH_BANK_NOT_PROBED;
  376. }
  377. for (sector = first; sector <= last; sector++) {
  378. if (bank->sectors[sector].is_protected) {
  379. LOG_ERROR("Flash sector %d protected", sector);
  380. return ERROR_FAIL;
  381. }
  382. }
  383. /* If we're erasing the entire chip and the flash supports
  384. * it, use a bulk erase instead of going sector-by-sector. */
  385. if (first == 0 && last == (bank->num_sectors - 1)
  386. && lpcspifi_info->dev->chip_erase_cmd != lpcspifi_info->dev->erase_cmd) {
  387. LOG_DEBUG("Chip supports the bulk erase command."\
  388. " Will use bulk erase instead of sector-by-sector erase.");
  389. retval = lpcspifi_bulk_erase(bank);
  390. if (retval == ERROR_OK) {
  391. retval = lpcspifi_set_hw_mode(bank);
  392. return retval;
  393. } else
  394. LOG_WARNING("Bulk flash erase failed. Falling back to sector-by-sector erase.");
  395. }
  396. retval = lpcspifi_set_hw_mode(bank);
  397. if (retval != ERROR_OK)
  398. return retval;
  399. /* see contrib/loaders/flash/lpcspifi_erase.S for src */
  400. static const uint8_t lpcspifi_flash_erase_code[] = {
  401. 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x08, 0x0a,
  402. 0x4f, 0xf0, 0xea, 0x08, 0xca, 0xf8, 0x8c, 0x81,
  403. 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x90, 0x81,
  404. 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x94, 0x81,
  405. 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x98, 0x81,
  406. 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x9c, 0x81,
  407. 0x4f, 0xf0, 0x44, 0x08, 0xca, 0xf8, 0xa0, 0x81,
  408. 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
  409. 0x4f, 0xf4, 0x00, 0x68, 0xca, 0xf8, 0x14, 0x80,
  410. 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
  411. 0x4f, 0xf0, 0xff, 0x08, 0xca, 0xf8, 0xab, 0x80,
  412. 0x4f, 0xf0, 0x00, 0x0a, 0xc4, 0xf2, 0x05, 0x0a,
  413. 0x4f, 0xf0, 0x00, 0x08, 0xc0, 0xf2, 0x00, 0x18,
  414. 0xca, 0xf8, 0x94, 0x80, 0x4f, 0xf4, 0x00, 0x5a,
  415. 0xc4, 0xf2, 0x05, 0x0a, 0x4f, 0xf0, 0x01, 0x08,
  416. 0xca, 0xf8, 0x00, 0x87, 0x4f, 0xf4, 0x40, 0x5a,
  417. 0xc4, 0xf2, 0x08, 0x0a, 0x4f, 0xf0, 0x07, 0x08,
  418. 0xca, 0xf8, 0x00, 0x80, 0x4f, 0xf0, 0x02, 0x08,
  419. 0xca, 0xf8, 0x10, 0x80, 0xca, 0xf8, 0x04, 0x80,
  420. 0x00, 0xf0, 0x52, 0xf8, 0x4f, 0xf0, 0x06, 0x09,
  421. 0x00, 0xf0, 0x3b, 0xf8, 0x00, 0xf0, 0x48, 0xf8,
  422. 0x00, 0xf0, 0x4a, 0xf8, 0x4f, 0xf0, 0x05, 0x09,
  423. 0x00, 0xf0, 0x33, 0xf8, 0x4f, 0xf0, 0x00, 0x09,
  424. 0x00, 0xf0, 0x2f, 0xf8, 0x00, 0xf0, 0x3c, 0xf8,
  425. 0x19, 0xf0, 0x02, 0x0f, 0x00, 0xf0, 0x45, 0x80,
  426. 0x00, 0xf0, 0x3a, 0xf8, 0x4f, 0xea, 0x02, 0x09,
  427. 0x00, 0xf0, 0x23, 0xf8, 0x4f, 0xea, 0x10, 0x49,
  428. 0x00, 0xf0, 0x1f, 0xf8, 0x4f, 0xea, 0x10, 0x29,
  429. 0x00, 0xf0, 0x1b, 0xf8, 0x4f, 0xea, 0x00, 0x09,
  430. 0x00, 0xf0, 0x17, 0xf8, 0x00, 0xf0, 0x24, 0xf8,
  431. 0x00, 0xf0, 0x26, 0xf8, 0x4f, 0xf0, 0x05, 0x09,
  432. 0x00, 0xf0, 0x0f, 0xf8, 0x4f, 0xf0, 0x00, 0x09,
  433. 0x00, 0xf0, 0x0b, 0xf8, 0x00, 0xf0, 0x18, 0xf8,
  434. 0x19, 0xf0, 0x01, 0x0f, 0x7f, 0xf4, 0xf0, 0xaf,
  435. 0x01, 0x39, 0xf9, 0xb1, 0x18, 0x44, 0xff, 0xf7,
  436. 0xbf, 0xbf, 0x4f, 0xf4, 0x40, 0x5a, 0xc4, 0xf2,
  437. 0x08, 0x0a, 0xca, 0xf8, 0x08, 0x90, 0xda, 0xf8,
  438. 0x0c, 0x90, 0x19, 0xf0, 0x10, 0x0f, 0x7f, 0xf4,
  439. 0xfa, 0xaf, 0xda, 0xf8, 0x08, 0x90, 0x70, 0x47,
  440. 0x4f, 0xf0, 0xff, 0x08, 0x00, 0xf0, 0x02, 0xb8,
  441. 0x4f, 0xf0, 0x00, 0x08, 0x4f, 0xf4, 0x80, 0x4a,
  442. 0xc4, 0xf2, 0x0f, 0x0a, 0xca, 0xf8, 0xab, 0x80,
  443. 0x70, 0x47, 0x00, 0x20, 0x00, 0xbe, 0xff, 0xff
  444. };
  445. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  446. armv7m_info.core_mode = ARM_MODE_THREAD;
  447. /* Get memory for spifi initialization algorithm */
  448. retval = target_alloc_working_area(target, sizeof(lpcspifi_flash_erase_code),
  449. &erase_algorithm);
  450. if (retval != ERROR_OK) {
  451. LOG_ERROR("Insufficient working area. You must configure a working"\
  452. " area of at least %zdB in order to erase SPIFI flash.",
  453. sizeof(lpcspifi_flash_erase_code));
  454. return retval;
  455. }
  456. /* Write algorithm to working area */
  457. retval = target_write_buffer(target, erase_algorithm->address,
  458. sizeof(lpcspifi_flash_erase_code), lpcspifi_flash_erase_code);
  459. if (retval != ERROR_OK) {
  460. target_free_working_area(target, erase_algorithm);
  461. return retval;
  462. }
  463. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* Start address */
  464. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* Sector count */
  465. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* Erase command */
  466. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* Sector size */
  467. buf_set_u32(reg_params[0].value, 0, 32, bank->sectors[first].offset);
  468. buf_set_u32(reg_params[1].value, 0, 32, last - first + 1);
  469. buf_set_u32(reg_params[2].value, 0, 32, lpcspifi_info->dev->erase_cmd);
  470. buf_set_u32(reg_params[3].value, 0, 32, bank->sectors[first].size);
  471. /* Run the algorithm */
  472. retval = target_run_algorithm(target, 0 , NULL, 4, reg_params,
  473. erase_algorithm->address,
  474. erase_algorithm->address + sizeof(lpcspifi_flash_erase_code) - 4,
  475. 3000*(last - first + 1), &armv7m_info);
  476. if (retval != ERROR_OK)
  477. LOG_ERROR("Error executing flash erase algorithm");
  478. target_free_working_area(target, erase_algorithm);
  479. destroy_reg_param(&reg_params[0]);
  480. destroy_reg_param(&reg_params[1]);
  481. destroy_reg_param(&reg_params[2]);
  482. destroy_reg_param(&reg_params[3]);
  483. retval = lpcspifi_set_hw_mode(bank);
  484. return retval;
  485. }
  486. static int lpcspifi_protect(struct flash_bank *bank, int set,
  487. int first, int last)
  488. {
  489. int sector;
  490. for (sector = first; sector <= last; sector++)
  491. bank->sectors[sector].is_protected = set;
  492. return ERROR_OK;
  493. }
  494. static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer,
  495. uint32_t offset, uint32_t count)
  496. {
  497. struct target *target = bank->target;
  498. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  499. uint32_t page_size, fifo_size;
  500. struct working_area *fifo;
  501. struct reg_param reg_params[5];
  502. struct armv7m_algorithm armv7m_info;
  503. struct working_area *write_algorithm;
  504. int sector;
  505. int retval = ERROR_OK;
  506. LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
  507. offset, count);
  508. if (target->state != TARGET_HALTED) {
  509. LOG_ERROR("Target not halted");
  510. return ERROR_TARGET_NOT_HALTED;
  511. }
  512. if (offset + count > lpcspifi_info->dev->size_in_bytes) {
  513. LOG_WARNING("Writes past end of flash. Extra data discarded.");
  514. count = lpcspifi_info->dev->size_in_bytes - offset;
  515. }
  516. /* Check sector protection */
  517. for (sector = 0; sector < bank->num_sectors; sector++) {
  518. /* Start offset in or before this sector? */
  519. /* End offset in or behind this sector? */
  520. if ((offset <
  521. (bank->sectors[sector].offset + bank->sectors[sector].size))
  522. && ((offset + count - 1) >= bank->sectors[sector].offset)
  523. && bank->sectors[sector].is_protected) {
  524. LOG_ERROR("Flash sector %d protected", sector);
  525. return ERROR_FAIL;
  526. }
  527. }
  528. page_size = lpcspifi_info->dev->pagesize;
  529. retval = lpcspifi_set_hw_mode(bank);
  530. if (retval != ERROR_OK)
  531. return retval;
  532. /* see contrib/loaders/flash/lpcspifi_write.S for src */
  533. static const uint8_t lpcspifi_flash_write_code[] = {
  534. 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x08, 0x0a,
  535. 0x4f, 0xf0, 0xea, 0x08, 0xca, 0xf8, 0x8c, 0x81,
  536. 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x90, 0x81,
  537. 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x94, 0x81,
  538. 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x98, 0x81,
  539. 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x9c, 0x81,
  540. 0x4f, 0xf0, 0x44, 0x08, 0xca, 0xf8, 0xa0, 0x81,
  541. 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
  542. 0x4f, 0xf4, 0x00, 0x68, 0xca, 0xf8, 0x14, 0x80,
  543. 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
  544. 0x4f, 0xf0, 0xff, 0x08, 0xca, 0xf8, 0xab, 0x80,
  545. 0x4f, 0xf0, 0x00, 0x0a, 0xc4, 0xf2, 0x05, 0x0a,
  546. 0x4f, 0xf0, 0x00, 0x08, 0xc0, 0xf2, 0x00, 0x18,
  547. 0xca, 0xf8, 0x94, 0x80, 0x4f, 0xf4, 0x00, 0x5a,
  548. 0xc4, 0xf2, 0x05, 0x0a, 0x4f, 0xf0, 0x01, 0x08,
  549. 0xca, 0xf8, 0x00, 0x87, 0x4f, 0xf4, 0x40, 0x5a,
  550. 0xc4, 0xf2, 0x08, 0x0a, 0x4f, 0xf0, 0x07, 0x08,
  551. 0xca, 0xf8, 0x00, 0x80, 0x4f, 0xf0, 0x02, 0x08,
  552. 0xca, 0xf8, 0x10, 0x80, 0xca, 0xf8, 0x04, 0x80,
  553. 0x4f, 0xf0, 0x00, 0x0b, 0xa3, 0x44, 0x93, 0x45,
  554. 0x7f, 0xf6, 0xfc, 0xaf, 0x00, 0xf0, 0x6a, 0xf8,
  555. 0x4f, 0xf0, 0x06, 0x09, 0x00, 0xf0, 0x53, 0xf8,
  556. 0x00, 0xf0, 0x60, 0xf8, 0x00, 0xf0, 0x62, 0xf8,
  557. 0x4f, 0xf0, 0x05, 0x09, 0x00, 0xf0, 0x4b, 0xf8,
  558. 0x4f, 0xf0, 0x00, 0x09, 0x00, 0xf0, 0x47, 0xf8,
  559. 0x00, 0xf0, 0x54, 0xf8, 0x19, 0xf0, 0x02, 0x0f,
  560. 0x00, 0xf0, 0x5d, 0x80, 0x00, 0xf0, 0x52, 0xf8,
  561. 0x4f, 0xf0, 0x02, 0x09, 0x00, 0xf0, 0x3b, 0xf8,
  562. 0x4f, 0xea, 0x12, 0x49, 0x00, 0xf0, 0x37, 0xf8,
  563. 0x4f, 0xea, 0x12, 0x29, 0x00, 0xf0, 0x33, 0xf8,
  564. 0x4f, 0xea, 0x02, 0x09, 0x00, 0xf0, 0x2f, 0xf8,
  565. 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f,
  566. 0x00, 0xf0, 0x47, 0x80, 0x47, 0x68, 0x47, 0x45,
  567. 0x3f, 0xf4, 0xf6, 0xaf, 0x17, 0xf8, 0x01, 0x9b,
  568. 0x00, 0xf0, 0x21, 0xf8, 0x8f, 0x42, 0x28, 0xbf,
  569. 0x00, 0xf1, 0x08, 0x07, 0x47, 0x60, 0x01, 0x3b,
  570. 0xbb, 0xb3, 0x02, 0xf1, 0x01, 0x02, 0x93, 0x45,
  571. 0x7f, 0xf4, 0xe6, 0xaf, 0x00, 0xf0, 0x22, 0xf8,
  572. 0xa3, 0x44, 0x00, 0xf0, 0x23, 0xf8, 0x4f, 0xf0,
  573. 0x05, 0x09, 0x00, 0xf0, 0x0c, 0xf8, 0x4f, 0xf0,
  574. 0x00, 0x09, 0x00, 0xf0, 0x08, 0xf8, 0x00, 0xf0,
  575. 0x15, 0xf8, 0x19, 0xf0, 0x01, 0x0f, 0x7f, 0xf4,
  576. 0xf0, 0xaf, 0xff, 0xf7, 0xa7, 0xbf, 0x4f, 0xf4,
  577. 0x40, 0x5a, 0xc4, 0xf2, 0x08, 0x0a, 0xca, 0xf8,
  578. 0x08, 0x90, 0xda, 0xf8, 0x0c, 0x90, 0x19, 0xf0,
  579. 0x10, 0x0f, 0x7f, 0xf4, 0xfa, 0xaf, 0xda, 0xf8,
  580. 0x08, 0x90, 0x70, 0x47, 0x4f, 0xf0, 0xff, 0x08,
  581. 0x00, 0xf0, 0x02, 0xb8, 0x4f, 0xf0, 0x00, 0x08,
  582. 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
  583. 0xca, 0xf8, 0xab, 0x80, 0x70, 0x47, 0x00, 0x20,
  584. 0x50, 0x60, 0x30, 0x46, 0x00, 0xbe, 0xff, 0xff
  585. };
  586. if (target_alloc_working_area(target, sizeof(lpcspifi_flash_write_code),
  587. &write_algorithm) != ERROR_OK) {
  588. LOG_ERROR("Insufficient working area. You must configure"\
  589. " a working area > %zdB in order to write to SPIFI flash.",
  590. sizeof(lpcspifi_flash_write_code));
  591. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  592. };
  593. retval = target_write_buffer(target, write_algorithm->address,
  594. sizeof(lpcspifi_flash_write_code),
  595. lpcspifi_flash_write_code);
  596. if (retval != ERROR_OK) {
  597. target_free_working_area(target, write_algorithm);
  598. return retval;
  599. }
  600. /* FIFO allocation */
  601. fifo_size = target_get_working_area_avail(target);
  602. if (fifo_size == 0) {
  603. /* if we already allocated the writing code but failed to get fifo
  604. * space, free the algorithm */
  605. target_free_working_area(target, write_algorithm);
  606. LOG_ERROR("Insufficient working area. Please allocate at least"\
  607. " %zdB of working area to enable flash writes.",
  608. sizeof(lpcspifi_flash_write_code) + 1
  609. );
  610. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  611. } else if (fifo_size < page_size)
  612. LOG_WARNING("Working area size is limited; flash writes may be"\
  613. " slow. Increase working area size to at least %zdB"\
  614. " to reduce write times.",
  615. sizeof(lpcspifi_flash_write_code) + page_size
  616. );
  617. else if (fifo_size > 0x2000) /* Beyond this point, we start to get diminishing returns */
  618. fifo_size = 0x2000;
  619. if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
  620. target_free_working_area(target, write_algorithm);
  621. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  622. };
  623. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  624. armv7m_info.core_mode = ARM_MODE_THREAD;
  625. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
  626. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
  627. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
  628. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
  629. init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* page size */
  630. buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
  631. buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
  632. buf_set_u32(reg_params[2].value, 0, 32, offset);
  633. buf_set_u32(reg_params[3].value, 0, 32, count);
  634. buf_set_u32(reg_params[4].value, 0, 32, page_size);
  635. retval = target_run_flash_async_algorithm(target, buffer, count, 1,
  636. 0, NULL,
  637. 5, reg_params,
  638. fifo->address, fifo->size,
  639. write_algorithm->address, 0,
  640. &armv7m_info
  641. );
  642. if (retval != ERROR_OK)
  643. LOG_ERROR("Error executing flash write algorithm");
  644. target_free_working_area(target, fifo);
  645. target_free_working_area(target, write_algorithm);
  646. destroy_reg_param(&reg_params[0]);
  647. destroy_reg_param(&reg_params[1]);
  648. destroy_reg_param(&reg_params[2]);
  649. destroy_reg_param(&reg_params[3]);
  650. destroy_reg_param(&reg_params[4]);
  651. /* Switch to HW mode before return to prompt */
  652. retval = lpcspifi_set_hw_mode(bank);
  653. return retval;
  654. }
  655. /* Return ID of flash device */
  656. /* On exit, SW mode is kept */
  657. static int lpcspifi_read_flash_id(struct flash_bank *bank, uint32_t *id)
  658. {
  659. struct target *target = bank->target;
  660. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  661. uint32_t ssp_base = lpcspifi_info->ssp_base;
  662. uint32_t io_base = lpcspifi_info->io_base;
  663. uint32_t value;
  664. int retval;
  665. if (target->state != TARGET_HALTED) {
  666. LOG_ERROR("Target not halted");
  667. return ERROR_TARGET_NOT_HALTED;
  668. }
  669. LOG_DEBUG("Getting ID");
  670. retval = lpcspifi_set_sw_mode(bank);
  671. if (retval != ERROR_OK)
  672. return retval;
  673. /* poll WIP */
  674. if (retval == ERROR_OK)
  675. retval = wait_till_ready(bank, SSP_PROBE_TIMEOUT);
  676. /* Send SPI command "read ID" */
  677. if (retval == ERROR_OK)
  678. retval = ssp_setcs(target, io_base, 0);
  679. if (retval == ERROR_OK)
  680. retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_READ_ID);
  681. if (retval == ERROR_OK)
  682. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  683. if (retval == ERROR_OK)
  684. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  685. /* Dummy write to clock in data */
  686. if (retval == ERROR_OK)
  687. retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
  688. if (retval == ERROR_OK)
  689. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  690. if (retval == ERROR_OK)
  691. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  692. if (retval == ERROR_OK)
  693. ((uint8_t *)id)[0] = value;
  694. /* Dummy write to clock in data */
  695. if (retval == ERROR_OK)
  696. retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
  697. if (retval == ERROR_OK)
  698. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  699. if (retval == ERROR_OK)
  700. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  701. if (retval == ERROR_OK)
  702. ((uint8_t *)id)[1] = value;
  703. /* Dummy write to clock in data */
  704. if (retval == ERROR_OK)
  705. retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
  706. if (retval == ERROR_OK)
  707. retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
  708. if (retval == ERROR_OK)
  709. retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
  710. if (retval == ERROR_OK)
  711. ((uint8_t *)id)[2] = value;
  712. if (retval == ERROR_OK)
  713. retval = ssp_setcs(target, io_base, 1);
  714. return retval;
  715. }
  716. static int lpcspifi_probe(struct flash_bank *bank)
  717. {
  718. struct target *target = bank->target;
  719. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  720. uint32_t ssp_base;
  721. uint32_t io_base;
  722. uint32_t ioconfig_base;
  723. struct flash_sector *sectors;
  724. uint32_t id = 0; /* silence uninitialized warning */
  725. struct lpcspifi_target *target_device;
  726. int retval;
  727. /* If we've already probed, we should be fine to skip this time. */
  728. if (lpcspifi_info->probed)
  729. return ERROR_OK;
  730. lpcspifi_info->probed = 0;
  731. for (target_device = target_devices ; target_device->name ; ++target_device)
  732. if (target_device->tap_idcode == target->tap->idcode)
  733. break;
  734. if (!target_device->name) {
  735. LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SPIFI capable",
  736. target->tap->idcode);
  737. return ERROR_FAIL;
  738. }
  739. ssp_base = target_device->ssp_base;
  740. io_base = target_device->io_base;
  741. ioconfig_base = target_device->ioconfig_base;
  742. lpcspifi_info->ssp_base = ssp_base;
  743. lpcspifi_info->io_base = io_base;
  744. lpcspifi_info->ioconfig_base = ioconfig_base;
  745. lpcspifi_info->bank_num = bank->bank_number;
  746. LOG_DEBUG("Valid SPIFI on device %s at address 0x%" PRIx32,
  747. target_device->name, bank->base);
  748. /* read and decode flash ID; returns in SW mode */
  749. retval = lpcspifi_read_flash_id(bank, &id);
  750. if (retval != ERROR_OK)
  751. return retval;
  752. retval = lpcspifi_set_hw_mode(bank);
  753. if (retval != ERROR_OK)
  754. return retval;
  755. lpcspifi_info->dev = NULL;
  756. for (struct flash_device *p = flash_devices; p->name ; p++)
  757. if (p->device_id == id) {
  758. lpcspifi_info->dev = p;
  759. break;
  760. }
  761. if (!lpcspifi_info->dev) {
  762. LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
  763. return ERROR_FAIL;
  764. }
  765. LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
  766. lpcspifi_info->dev->name, lpcspifi_info->dev->device_id);
  767. /* Set correct size value */
  768. bank->size = lpcspifi_info->dev->size_in_bytes;
  769. /* create and fill sectors array */
  770. bank->num_sectors =
  771. lpcspifi_info->dev->size_in_bytes / lpcspifi_info->dev->sectorsize;
  772. sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
  773. if (sectors == NULL) {
  774. LOG_ERROR("not enough memory");
  775. return ERROR_FAIL;
  776. }
  777. for (int sector = 0; sector < bank->num_sectors; sector++) {
  778. sectors[sector].offset = sector * lpcspifi_info->dev->sectorsize;
  779. sectors[sector].size = lpcspifi_info->dev->sectorsize;
  780. sectors[sector].is_erased = -1;
  781. sectors[sector].is_protected = 1;
  782. }
  783. bank->sectors = sectors;
  784. lpcspifi_info->probed = 1;
  785. return ERROR_OK;
  786. }
  787. static int lpcspifi_auto_probe(struct flash_bank *bank)
  788. {
  789. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  790. if (lpcspifi_info->probed)
  791. return ERROR_OK;
  792. return lpcspifi_probe(bank);
  793. }
  794. static int lpcspifi_protect_check(struct flash_bank *bank)
  795. {
  796. /* Nothing to do. Protection is only handled in SW. */
  797. return ERROR_OK;
  798. }
  799. static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size)
  800. {
  801. struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
  802. if (!(lpcspifi_info->probed)) {
  803. snprintf(buf, buf_size,
  804. "\nSPIFI flash bank not probed yet\n");
  805. return ERROR_OK;
  806. }
  807. snprintf(buf, buf_size, "\nSPIFI flash information:\n"
  808. " Device \'%s\' (ID 0x%08x)\n",
  809. lpcspifi_info->dev->name, lpcspifi_info->dev->device_id);
  810. return ERROR_OK;
  811. }
  812. struct flash_driver lpcspifi_flash = {
  813. .name = "lpcspifi",
  814. .flash_bank_command = lpcspifi_flash_bank_command,
  815. .erase = lpcspifi_erase,
  816. .protect = lpcspifi_protect,
  817. .write = lpcspifi_write,
  818. .read = default_flash_read,
  819. .probe = lpcspifi_probe,
  820. .auto_probe = lpcspifi_auto_probe,
  821. .erase_check = default_flash_blank_check,
  822. .protect_check = lpcspifi_protect_check,
  823. .info = get_lpcspifi_info,
  824. };