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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * Copyright (C) 2009 Michael Schwingen *
  5. * michael@schwingen.org *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ***************************************************************************/
  22. #ifdef HAVE_CONFIG_H
  23. #include "config.h"
  24. #endif
  25. #include "imp.h"
  26. #include "cfi.h"
  27. #include "non_cfi.h"
  28. #define KB 1024
  29. #define MB (1024*1024)
  30. #define ERASE_REGION(num, size) (((size/256) << 16) | (num-1))
  31. /* non-CFI compatible flashes */
  32. static struct non_cfi non_cfi_flashes[] = {
  33. {
  34. .mfr = CFI_MFR_SST,
  35. .id = 0xd4,
  36. .pri_id = 0x02,
  37. .dev_size = 64*KB,
  38. .interface_desc = 0x0, /* x8 only device */
  39. .max_buf_write_size = 0x0,
  40. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  41. .num_erase_regions = 1,
  42. .erase_region_info = {
  43. ERASE_REGION(16, 4*KB)
  44. }
  45. },
  46. {
  47. .mfr = CFI_MFR_SST,
  48. .id = 0xd5,
  49. .pri_id = 0x02,
  50. .dev_size = 128*KB,
  51. .interface_desc = 0x0, /* x8 only device */
  52. .max_buf_write_size = 0x0,
  53. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  54. .num_erase_regions = 1,
  55. .erase_region_info = {
  56. ERASE_REGION(32, 4*KB)
  57. }
  58. },
  59. {
  60. .mfr = CFI_MFR_SST,
  61. .id = 0xd6,
  62. .pri_id = 0x02,
  63. .dev_size = 256*KB,
  64. .interface_desc = 0x0, /* x8 only device */
  65. .max_buf_write_size = 0x0,
  66. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  67. .num_erase_regions = 1,
  68. .erase_region_info = {
  69. ERASE_REGION(64, 4*KB)
  70. }
  71. },
  72. {
  73. .mfr = CFI_MFR_SST,
  74. .id = 0xd7,
  75. .pri_id = 0x02,
  76. .dev_size = 512*KB,
  77. .interface_desc = 0x0, /* x8 only device */
  78. .max_buf_write_size = 0x0,
  79. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  80. .num_erase_regions = 1,
  81. .erase_region_info = {
  82. ERASE_REGION(128, 4*KB)
  83. }
  84. },
  85. {
  86. .mfr = CFI_MFR_AMD, /* Spansion AM29LV040B */
  87. .id = 0x4f,
  88. .pri_id = 0x02,
  89. .dev_size = 512*KB,
  90. .interface_desc = 0x0, /* x8 only device */
  91. .max_buf_write_size = 0x0,
  92. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  93. .num_erase_regions = 1,
  94. .erase_region_info = {
  95. ERASE_REGION(8, 64*KB)
  96. }
  97. },
  98. {
  99. .mfr = CFI_MFR_SST,
  100. .id = 0x2780,
  101. .pri_id = 0x02,
  102. .dev_size = 512*KB,
  103. .interface_desc = 0x2, /* x8 or x16 device */
  104. .max_buf_write_size = 0x0,
  105. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  106. .num_erase_regions = 1,
  107. .erase_region_info = {
  108. ERASE_REGION(128, 4*KB)
  109. }
  110. },
  111. {
  112. .mfr = CFI_MFR_ST,
  113. .id = 0xd6, /* ST29F400BB */
  114. .pri_id = 0x02,
  115. .dev_size = 512*KB,
  116. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  117. .max_buf_write_size = 0x0,
  118. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  119. .num_erase_regions = 4,
  120. .erase_region_info = {
  121. ERASE_REGION(1, 16*KB),
  122. ERASE_REGION(2, 8*KB),
  123. ERASE_REGION(1, 32*KB),
  124. ERASE_REGION(7, 64*KB)
  125. }
  126. },
  127. {
  128. .mfr = CFI_MFR_ST,
  129. .id = 0xd5, /* ST29F400BT */
  130. .pri_id = 0x02,
  131. .dev_size = 512*KB,
  132. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  133. .max_buf_write_size = 0x0,
  134. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  135. .num_erase_regions = 4,
  136. .erase_region_info = {
  137. ERASE_REGION(7, 64*KB),
  138. ERASE_REGION(1, 32*KB),
  139. ERASE_REGION(2, 8*KB),
  140. ERASE_REGION(1, 16*KB)
  141. }
  142. },
  143. /* SST 39VF* do not support DQ5 status polling - this currently is
  144. only supported by the host algorithm, not by the target code using
  145. the work area.
  146. Only true for 8-bit and 32-bit wide memories. 16-bit wide memories
  147. without DQ5 status polling are supported by the target code.
  148. */
  149. {
  150. .mfr = CFI_MFR_SST,
  151. .id = 0x2782, /* SST39xF160 */
  152. .pri_id = 0x02,
  153. .dev_size = 2*MB,
  154. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  155. .max_buf_write_size = 0x0,
  156. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  157. .num_erase_regions = 1,
  158. .erase_region_info = {
  159. ERASE_REGION(512, 4*KB)
  160. }
  161. },
  162. {
  163. .mfr = CFI_MFR_SST,
  164. .id = 0x2783, /* SST39VF320 */
  165. .pri_id = 0x02,
  166. .dev_size = 4*MB,
  167. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  168. .max_buf_write_size = 0x0,
  169. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  170. .num_erase_regions = 1,
  171. .erase_region_info = {
  172. ERASE_REGION(1024, 4*KB)
  173. }
  174. },
  175. {
  176. .mfr = CFI_MFR_SST,
  177. .id = 0x234b, /* SST39VF1601 */
  178. .pri_id = 0x02,
  179. .dev_size = 2*MB,
  180. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  181. .max_buf_write_size = 0x0,
  182. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  183. .num_erase_regions = 1,
  184. .erase_region_info = {
  185. ERASE_REGION(512, 4*KB)
  186. }
  187. },
  188. {
  189. .mfr = CFI_MFR_SST,
  190. .id = 0x274b, /* SST39WF1601 */
  191. .pri_id = 0x02,
  192. .dev_size = 2*MB,
  193. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  194. .max_buf_write_size = 0x0,
  195. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  196. .num_erase_regions = 1,
  197. .erase_region_info = {
  198. ERASE_REGION(512, 4*KB)
  199. }
  200. },
  201. {
  202. .mfr = CFI_MFR_SST,
  203. .id = 0x234a, /* SST39VF1602 */
  204. .pri_id = 0x02,
  205. .dev_size = 2*MB,
  206. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  207. .max_buf_write_size = 0x0,
  208. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  209. .num_erase_regions = 1,
  210. .erase_region_info = {
  211. ERASE_REGION(512, 4*KB)
  212. }
  213. },
  214. {
  215. .mfr = CFI_MFR_SST,
  216. .id = 0x235b, /* SST39VF3201 */
  217. .pri_id = 0x02,
  218. .dev_size = 4*MB,
  219. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  220. .max_buf_write_size = 0x0,
  221. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  222. .num_erase_regions = 1,
  223. .erase_region_info = {
  224. ERASE_REGION(1024, 4*KB)
  225. }
  226. },
  227. {
  228. .mfr = CFI_MFR_SST,
  229. .id = 0x235a, /* SST39VF3202 */
  230. .pri_id = 0x02,
  231. .dev_size = 4*MB,
  232. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  233. .max_buf_write_size = 0x0,
  234. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  235. .num_erase_regions = 1,
  236. .erase_region_info = {
  237. ERASE_REGION(1024, 4*KB)
  238. }
  239. },
  240. {
  241. .mfr = CFI_MFR_SST,
  242. .id = 0x236d, /* SST39VF6401B */
  243. .pri_id = 0x02,
  244. .dev_size = 8*MB,
  245. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  246. .max_buf_write_size = 0x0,
  247. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
  248. .num_erase_regions = 1,
  249. .erase_region_info = {
  250. ERASE_REGION(2048, 4*KB)
  251. }
  252. },
  253. {
  254. .mfr = CFI_MFR_AMD,
  255. .id = 0x22ab, /* AM29F400BB */
  256. .pri_id = 0x02,
  257. .dev_size = 512*KB,
  258. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  259. .max_buf_write_size = 0x0,
  260. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  261. .num_erase_regions = 4,
  262. .erase_region_info = {
  263. ERASE_REGION(1, 16*KB),
  264. ERASE_REGION(2, 8*KB),
  265. ERASE_REGION(1, 32*KB),
  266. ERASE_REGION(7, 64*KB)
  267. }
  268. },
  269. {
  270. .mfr = CFI_MFR_AMD,
  271. .id = 0x2223, /* AM29F400BT */
  272. .pri_id = 0x02,
  273. .dev_size = 512*KB,
  274. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  275. .max_buf_write_size = 0x0,
  276. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  277. .num_erase_regions = 4,
  278. .erase_region_info = {
  279. ERASE_REGION(7, 64*KB),
  280. ERASE_REGION(1, 32*KB),
  281. ERASE_REGION(2, 8*KB),
  282. ERASE_REGION(1, 16*KB)
  283. }
  284. },
  285. {
  286. .mfr = CFI_MFR_FUJITSU,
  287. .id = 0x226b, /* AM29SL800DB */
  288. .pri_id = 0x02,
  289. .dev_size = 1*MB,
  290. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  291. .max_buf_write_size = 0x0,
  292. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  293. .num_erase_regions = 4,
  294. .erase_region_info = {
  295. ERASE_REGION(1, 16*KB),
  296. ERASE_REGION(2, 8*KB),
  297. ERASE_REGION(1, 32*KB),
  298. ERASE_REGION(15, 64*KB)
  299. }
  300. },
  301. {
  302. .mfr = CFI_MFR_FUJITSU,
  303. .id = 0x22ea, /* MBM29SL800TE */
  304. .pri_id = 0x02,
  305. .dev_size = 1*MB,
  306. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  307. .max_buf_write_size = 0x0,
  308. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  309. .num_erase_regions = 4,
  310. .erase_region_info = {
  311. ERASE_REGION(15, 64*KB),
  312. ERASE_REGION(1, 32*KB),
  313. ERASE_REGION(2, 8*KB),
  314. ERASE_REGION(1, 16*KB)
  315. }
  316. },
  317. {
  318. .mfr = CFI_MFR_FUJITSU,
  319. .id = 0xba, /* 29LV400BC */
  320. .pri_id = 0x02,
  321. .dev_size = 512*KB,
  322. .interface_desc = 0x1, /* x8 or x16 device w/ nBYTE */
  323. .max_buf_write_size = 0x00,
  324. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  325. .num_erase_regions = 4,
  326. .erase_region_info = {
  327. ERASE_REGION(1, 16*KB),
  328. ERASE_REGION(2, 8*KB),
  329. ERASE_REGION(1, 32*KB),
  330. ERASE_REGION(7, 64*KB)
  331. }
  332. },
  333. {
  334. .mfr = CFI_MFR_AMIC,
  335. .id = 0xb31a, /* A29L800A */
  336. .pri_id = 0x02,
  337. .dev_size = 1*MB,
  338. .interface_desc = 0x2,
  339. .max_buf_write_size = 0x0,
  340. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  341. .num_erase_regions = 4,
  342. .erase_region_info = {
  343. ERASE_REGION(1, 16*KB),
  344. ERASE_REGION(2, 8*KB),
  345. ERASE_REGION(1, 32*KB),
  346. ERASE_REGION(15, 64*KB)
  347. }
  348. },
  349. {
  350. .mfr = CFI_MFR_MX,
  351. .id = 0x225b, /* MX29LV800B */
  352. .pri_id = 0x02,
  353. .dev_size = 1*MB,
  354. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  355. .max_buf_write_size = 0x0,
  356. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  357. .num_erase_regions = 4,
  358. .erase_region_info = {
  359. ERASE_REGION(1, 16*KB),
  360. ERASE_REGION(2, 8*KB),
  361. ERASE_REGION(1, 32*KB),
  362. ERASE_REGION(15, 64*KB)
  363. }
  364. },
  365. {
  366. .mfr = CFI_MFR_MX,
  367. .id = 0x2249, /* MX29LV160AB: 2MB */
  368. .pri_id = 0x02,
  369. .dev_size = 2*MB,
  370. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  371. .max_buf_write_size = 0x0,
  372. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  373. .num_erase_regions = 4,
  374. .erase_region_info = {
  375. ERASE_REGION(1, 16*KB),
  376. ERASE_REGION(2, 8*KB),
  377. ERASE_REGION(1, 32*KB),
  378. ERASE_REGION(31, 64*KB)
  379. }
  380. },
  381. {
  382. .mfr = CFI_MFR_MX,
  383. .id = 0x22C4, /* MX29LV160AT: 2MB */
  384. .pri_id = 0x02,
  385. .dev_size = 2*MB,
  386. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  387. .max_buf_write_size = 0x0,
  388. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  389. .num_erase_regions = 4,
  390. .erase_region_info = {
  391. ERASE_REGION(31, 64*KB),
  392. ERASE_REGION(1, 32*KB),
  393. ERASE_REGION(2, 8*KB),
  394. ERASE_REGION(1, 16*KB)
  395. }
  396. },
  397. {
  398. .mfr = CFI_MFR_EON,
  399. .id = 0x225b, /* EN29LV800BB */
  400. .pri_id = 0x02,
  401. .dev_size = 1*MB,
  402. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  403. .max_buf_write_size = 0x0,
  404. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  405. .num_erase_regions = 4,
  406. .erase_region_info = {
  407. ERASE_REGION(1, 16*KB),
  408. ERASE_REGION(2, 8*KB),
  409. ERASE_REGION(1, 32*KB),
  410. ERASE_REGION(15, 64*KB)
  411. }
  412. },
  413. {
  414. .mfr = CFI_MFR_ATMEL,
  415. .id = 0x00c0, /* Atmel 49BV1614 */
  416. .pri_id = 0x02,
  417. .dev_size = 2*MB,
  418. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  419. .max_buf_write_size = 0x0,
  420. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  421. .num_erase_regions = 3,
  422. .erase_region_info = {
  423. ERASE_REGION(8, 8*KB),
  424. ERASE_REGION(2, 32*KB),
  425. ERASE_REGION(30, 64*KB)
  426. }
  427. },
  428. {
  429. .mfr = CFI_MFR_ATMEL,
  430. .id = 0xC2, /* Atmel 49BV1614T */
  431. .pri_id = 0x02,
  432. .dev_size = 2*MB,
  433. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  434. .max_buf_write_size = 0x0,
  435. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  436. .num_erase_regions = 3,
  437. .erase_region_info = {
  438. ERASE_REGION(30, 64*KB),
  439. ERASE_REGION(2, 32*KB),
  440. ERASE_REGION(8, 8*KB)
  441. }
  442. },
  443. {
  444. .mfr = CFI_MFR_AMD,
  445. .id = 0x225b, /* S29AL008D */
  446. .pri_id = 0x02,
  447. .dev_size = 1*MB,
  448. .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
  449. .max_buf_write_size = 0x0,
  450. .status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
  451. .num_erase_regions = 4,
  452. .erase_region_info = {
  453. ERASE_REGION(1, 16*KB),
  454. ERASE_REGION(2, 8*KB),
  455. ERASE_REGION(1, 32*KB),
  456. ERASE_REGION(15, 64*KB)
  457. }
  458. },
  459. {
  460. .mfr = 0,
  461. .id = 0,
  462. }
  463. };
  464. void cfi_fixup_non_cfi(struct flash_bank *bank)
  465. {
  466. unsigned int mask;
  467. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  468. struct non_cfi *non_cfi = non_cfi_flashes;
  469. if (cfi_info->x16_as_x8)
  470. mask = 0xFF;
  471. else
  472. mask = 0xFFFF;
  473. for (non_cfi = non_cfi_flashes; non_cfi->mfr; non_cfi++) {
  474. if ((cfi_info->manufacturer == non_cfi->mfr)
  475. && (cfi_info->device_id == (non_cfi->id & mask)))
  476. break;
  477. }
  478. /* only fixup jedec flashs found in table */
  479. if (!non_cfi->mfr)
  480. return;
  481. cfi_info->not_cfi = 1;
  482. /* fill in defaults for non-critical data */
  483. cfi_info->vcc_min = 0x0;
  484. cfi_info->vcc_max = 0x0;
  485. cfi_info->vpp_min = 0x0;
  486. cfi_info->vpp_max = 0x0;
  487. /* these are used for timeouts - use vales that should be long enough
  488. for normal operation. */
  489. cfi_info->word_write_timeout_typ = 0x0a;
  490. cfi_info->buf_write_timeout_typ = 0x0d;
  491. cfi_info->block_erase_timeout_typ = 0x0d;
  492. cfi_info->chip_erase_timeout_typ = 0x10;
  493. cfi_info->word_write_timeout_max = 0x0;
  494. cfi_info->buf_write_timeout_max = 0x0;
  495. cfi_info->block_erase_timeout_max = 0x0;
  496. cfi_info->chip_erase_timeout_max = 0x0;
  497. cfi_info->qry[0] = 'Q';
  498. cfi_info->qry[1] = 'R';
  499. cfi_info->qry[2] = 'Y';
  500. cfi_info->pri_id = non_cfi->pri_id;
  501. cfi_info->pri_addr = 0x0;
  502. cfi_info->alt_id = 0x0;
  503. cfi_info->alt_addr = 0x0;
  504. cfi_info->alt_ext = NULL;
  505. cfi_info->interface_desc = non_cfi->interface_desc;
  506. cfi_info->max_buf_write_size = non_cfi->max_buf_write_size;
  507. cfi_info->status_poll_mask = non_cfi->status_poll_mask;
  508. cfi_info->num_erase_regions = non_cfi->num_erase_regions;
  509. size_t erase_region_info_size = sizeof(*cfi_info->erase_region_info) *
  510. cfi_info->num_erase_regions;
  511. cfi_info->erase_region_info = malloc(erase_region_info_size);
  512. memcpy(cfi_info->erase_region_info,
  513. non_cfi->erase_region_info, erase_region_info_size);
  514. cfi_info->dev_size = non_cfi->dev_size;
  515. if (cfi_info->pri_id == 0x2) {
  516. struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
  517. pri_ext->pri[0] = 'P';
  518. pri_ext->pri[1] = 'R';
  519. pri_ext->pri[2] = 'I';
  520. pri_ext->major_version = '1';
  521. pri_ext->minor_version = '0';
  522. pri_ext->SiliconRevision = 0x0;
  523. pri_ext->EraseSuspend = 0x0;
  524. pri_ext->EraseSuspend = 0x0;
  525. pri_ext->BlkProt = 0x0;
  526. pri_ext->TmpBlkUnprotect = 0x0;
  527. pri_ext->BlkProtUnprot = 0x0;
  528. pri_ext->SimultaneousOps = 0x0;
  529. pri_ext->BurstMode = 0x0;
  530. pri_ext->PageMode = 0x0;
  531. pri_ext->VppMin = 0x0;
  532. pri_ext->VppMax = 0x0;
  533. pri_ext->TopBottom = 0x0;
  534. pri_ext->_unlock1 = 0x5555;
  535. pri_ext->_unlock2 = 0x2AAA;
  536. pri_ext->_reversed_geometry = 0;
  537. cfi_info->pri_ext = pri_ext;
  538. } else if ((cfi_info->pri_id == 0x1) || (cfi_info->pri_id == 0x3)) {
  539. LOG_ERROR("BUG: non-CFI flashes using the Intel commandset are not yet supported");
  540. exit(-1);
  541. }
  542. }