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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2008 by John McCarthy *
  9. * jgmcc@magma.ca *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include <jtag/jtag.h>
  30. #include "imp.h"
  31. #include <target/algorithm.h>
  32. #include <target/mips32.h>
  33. #include <target/mips_m4k.h>
  34. #define PIC32MX_MANUF_ID 0x029
  35. /* pic32mx memory locations */
  36. #define PIC32MX_PHYS_RAM 0x00000000
  37. #define PIC32MX_PHYS_PGM_FLASH 0x1D000000
  38. #define PIC32MX_PHYS_PERIPHERALS 0x1F800000
  39. #define PIC32MX_PHYS_BOOT_FLASH 0x1FC00000
  40. /*
  41. * Translate Virtual and Physical addresses.
  42. * Note: These macros only work for KSEG0/KSEG1 addresses.
  43. */
  44. #define Virt2Phys(v) ((v) & 0x1FFFFFFF)
  45. /* pic32mx configuration register locations */
  46. #define PIC32MX_DEVCFG0_1_2 0xBFC00BFC
  47. #define PIC32MX_DEVCFG0 0xBFC02FFC
  48. #define PIC32MX_DEVCFG1 0xBFC02FF8
  49. #define PIC32MX_DEVCFG2 0xBFC02FF4
  50. #define PIC32MX_DEVCFG3 0xBFC02FF0
  51. #define PIC32MX_DEVID 0xBF80F220
  52. #define PIC32MX_BMXPFMSZ 0xBF882060
  53. #define PIC32MX_BMXBOOTSZ 0xBF882070
  54. #define PIC32MX_BMXDRMSZ 0xBF882040
  55. /* pic32mx flash controller register locations */
  56. #define PIC32MX_NVMCON 0xBF80F400
  57. #define PIC32MX_NVMCONCLR 0xBF80F404
  58. #define PIC32MX_NVMCONSET 0xBF80F408
  59. #define PIC32MX_NVMCONINV 0xBF80F40C
  60. #define NVMCON_NVMWR (1 << 15)
  61. #define NVMCON_NVMWREN (1 << 14)
  62. #define NVMCON_NVMERR (1 << 13)
  63. #define NVMCON_LVDERR (1 << 12)
  64. #define NVMCON_LVDSTAT (1 << 11)
  65. #define NVMCON_OP_PFM_ERASE 0x5
  66. #define NVMCON_OP_PAGE_ERASE 0x4
  67. #define NVMCON_OP_ROW_PROG 0x3
  68. #define NVMCON_OP_WORD_PROG 0x1
  69. #define NVMCON_OP_NOP 0x0
  70. #define PIC32MX_NVMKEY 0xBF80F410
  71. #define PIC32MX_NVMADDR 0xBF80F420
  72. #define PIC32MX_NVMADDRCLR 0xBF80F424
  73. #define PIC32MX_NVMADDRSET 0xBF80F428
  74. #define PIC32MX_NVMADDRINV 0xBF80F42C
  75. #define PIC32MX_NVMDATA 0xBF80F430
  76. #define PIC32MX_NVMSRCADDR 0xBF80F440
  77. /* flash unlock keys */
  78. #define NVMKEY1 0xAA996655
  79. #define NVMKEY2 0x556699AA
  80. #define MX_1_2 1 /* PIC32mx1xx/2xx */
  81. struct pic32mx_flash_bank {
  82. int probed;
  83. int dev_type; /* Default 0. 1 for Pic32MX1XX/2XX variant */
  84. };
  85. /*
  86. * DEVID values as per PIC32MX Flash Programming Specification Rev J
  87. */
  88. static const struct pic32mx_devs_s {
  89. uint32_t devid;
  90. const char *name;
  91. } pic32mx_devs[] = {
  92. {0x04A07053, "110F016B"},
  93. {0x04A09053, "110F016C"},
  94. {0x04A0B053, "110F016D"},
  95. {0x04A06053, "120F032B"},
  96. {0x04A08053, "120F032C"},
  97. {0x04A0A053, "120F032D"},
  98. {0x04D07053, "130F064B"},
  99. {0x04D09053, "130F064C"},
  100. {0x04D0B053, "130F064D"},
  101. {0x04D06053, "150F128B"},
  102. {0x04D08053, "150F128C"},
  103. {0x04D0A053, "150F128D"},
  104. {0x04A01053, "210F016B"},
  105. {0x04A03053, "210F016C"},
  106. {0x04A05053, "210F016D"},
  107. {0x04A00053, "220F032B"},
  108. {0x04A02053, "220F032C"},
  109. {0x04A04053, "220F032D"},
  110. {0x04D01053, "230F064B"},
  111. {0x04D03053, "230F064C"},
  112. {0x04D05053, "230F064D"},
  113. {0x04D00053, "250F128B"},
  114. {0x04D02053, "250F128C"},
  115. {0x04D04053, "250F128D"},
  116. {0x00938053, "360F512L"},
  117. {0x00934053, "360F256L"},
  118. {0x0092D053, "340F128L"},
  119. {0x0092A053, "320F128L"},
  120. {0x00916053, "340F512H"},
  121. {0x00912053, "340F256H"},
  122. {0x0090D053, "340F128H"},
  123. {0x0090A053, "320F128H"},
  124. {0x00906053, "320F064H"},
  125. {0x00902053, "320F032H"},
  126. {0x00978053, "460F512L"},
  127. {0x00974053, "460F256L"},
  128. {0x0096D053, "440F128L"},
  129. {0x00952053, "440F256H"},
  130. {0x00956053, "440F512H"},
  131. {0x0094D053, "440F128H"},
  132. {0x00942053, "420F032H"},
  133. {0x04307053, "795F512L"},
  134. {0x0430E053, "795F512H"},
  135. {0x04306053, "775F512L"},
  136. {0x0430D053, "775F512H"},
  137. {0x04312053, "775F256L"},
  138. {0x04303053, "775F256H"},
  139. {0x04417053, "764F128L"},
  140. {0x0440B053, "764F128H"},
  141. {0x04341053, "695F512L"},
  142. {0x04325053, "695F512H"},
  143. {0x04311053, "675F512L"},
  144. {0x0430C053, "675F512H"},
  145. {0x04305053, "675F256L"},
  146. {0x0430B053, "675F256H"},
  147. {0x04413053, "664F128L"},
  148. {0x04407053, "664F128H"},
  149. {0x04411053, "664F064L"},
  150. {0x04405053, "664F064H"},
  151. {0x0430F053, "575F512L"},
  152. {0x04309053, "575F512H"},
  153. {0x04333053, "575F256L"},
  154. {0x04317053, "575F256H"},
  155. {0x0440F053, "564F128L"},
  156. {0x04403053, "564F128H"},
  157. {0x0440D053, "564F064L"},
  158. {0x04401053, "564F064H"},
  159. {0x04400053, "534F064H"},
  160. {0x0440C053, "534F064L"},
  161. {0x00000000, NULL}
  162. };
  163. /* flash bank pic32mx <base> <size> 0 0 <target#>
  164. */
  165. FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
  166. {
  167. struct pic32mx_flash_bank *pic32mx_info;
  168. if (CMD_ARGC < 6)
  169. return ERROR_COMMAND_SYNTAX_ERROR;
  170. pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
  171. bank->driver_priv = pic32mx_info;
  172. pic32mx_info->probed = 0;
  173. pic32mx_info->dev_type = 0;
  174. return ERROR_OK;
  175. }
  176. static uint32_t pic32mx_get_flash_status(struct flash_bank *bank)
  177. {
  178. struct target *target = bank->target;
  179. uint32_t status;
  180. target_read_u32(target, PIC32MX_NVMCON, &status);
  181. return status;
  182. }
  183. static uint32_t pic32mx_wait_status_busy(struct flash_bank *bank, int timeout)
  184. {
  185. uint32_t status;
  186. /* wait for busy to clear */
  187. while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0)) {
  188. LOG_DEBUG("status: 0x%" PRIx32, status);
  189. alive_sleep(1);
  190. }
  191. if (timeout <= 0)
  192. LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
  193. return status;
  194. }
  195. static int pic32mx_nvm_exec(struct flash_bank *bank, uint32_t op, uint32_t timeout)
  196. {
  197. struct target *target = bank->target;
  198. uint32_t status;
  199. target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
  200. /* unlock flash registers */
  201. target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
  202. target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);
  203. /* start operation */
  204. target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);
  205. status = pic32mx_wait_status_busy(bank, timeout);
  206. /* lock flash registers */
  207. target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);
  208. return status;
  209. }
  210. static int pic32mx_protect_check(struct flash_bank *bank)
  211. {
  212. struct target *target = bank->target;
  213. struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
  214. uint32_t config0_address;
  215. uint32_t devcfg0;
  216. int s;
  217. int num_pages;
  218. if (target->state != TARGET_HALTED) {
  219. LOG_ERROR("Target not halted");
  220. return ERROR_TARGET_NOT_HALTED;
  221. }
  222. if (pic32mx_info->dev_type == MX_1_2)
  223. config0_address = PIC32MX_DEVCFG0_1_2;
  224. else
  225. config0_address = PIC32MX_DEVCFG0;
  226. target_read_u32(target, config0_address, &devcfg0);
  227. if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
  228. num_pages = 0xffff; /* All pages protected */
  229. else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
  230. if (devcfg0 & (1 << 24))
  231. num_pages = 0; /* All pages unprotected */
  232. else
  233. num_pages = 0xffff; /* All pages protected */
  234. } else {
  235. /* pgm flash */
  236. if (pic32mx_info->dev_type == MX_1_2)
  237. num_pages = (~devcfg0 >> 10) & 0x3f;
  238. else
  239. num_pages = (~devcfg0 >> 12) & 0xff;
  240. }
  241. for (s = 0; s < bank->num_sectors && s < num_pages; s++)
  242. bank->sectors[s].is_protected = 1;
  243. for (; s < bank->num_sectors; s++)
  244. bank->sectors[s].is_protected = 0;
  245. return ERROR_OK;
  246. }
  247. static int pic32mx_erase(struct flash_bank *bank, int first, int last)
  248. {
  249. struct target *target = bank->target;
  250. int i;
  251. uint32_t status;
  252. if (bank->target->state != TARGET_HALTED) {
  253. LOG_ERROR("Target not halted");
  254. return ERROR_TARGET_NOT_HALTED;
  255. }
  256. if ((first == 0) && (last == (bank->num_sectors - 1))
  257. && (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
  258. /* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
  259. * we need to use the MTAP to perform a full erase */
  260. LOG_DEBUG("Erasing entire program flash");
  261. status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
  262. if (status & NVMCON_NVMERR)
  263. return ERROR_FLASH_OPERATION_FAILED;
  264. if (status & NVMCON_LVDERR)
  265. return ERROR_FLASH_OPERATION_FAILED;
  266. return ERROR_OK;
  267. }
  268. for (i = first; i <= last; i++) {
  269. target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
  270. status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
  271. if (status & NVMCON_NVMERR)
  272. return ERROR_FLASH_OPERATION_FAILED;
  273. if (status & NVMCON_LVDERR)
  274. return ERROR_FLASH_OPERATION_FAILED;
  275. bank->sectors[i].is_erased = 1;
  276. }
  277. return ERROR_OK;
  278. }
  279. static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
  280. {
  281. struct target *target = bank->target;
  282. if (target->state != TARGET_HALTED) {
  283. LOG_ERROR("Target not halted");
  284. return ERROR_TARGET_NOT_HALTED;
  285. }
  286. return ERROR_OK;
  287. }
  288. /* see contib/loaders/flash/pic32mx.s for src */
  289. static uint32_t pic32mx_flash_write_code[] = {
  290. /* write: */
  291. 0x3C08AA99, /* lui $t0, 0xaa99 */
  292. 0x35086655, /* ori $t0, 0x6655 */
  293. 0x3C095566, /* lui $t1, 0x5566 */
  294. 0x352999AA, /* ori $t1, 0x99aa */
  295. 0x3C0ABF80, /* lui $t2, 0xbf80 */
  296. 0x354AF400, /* ori $t2, 0xf400 */
  297. 0x340B4003, /* ori $t3, $zero, 0x4003 */
  298. 0x340C8000, /* ori $t4, $zero, 0x8000 */
  299. /* write_row: */
  300. 0x2CD30080, /* sltiu $s3, $a2, 128 */
  301. 0x16600008, /* bne $s3, $zero, write_word */
  302. 0x340D4000, /* ori $t5, $zero, 0x4000 */
  303. 0xAD450020, /* sw $a1, 32($t2) */
  304. 0xAD440040, /* sw $a0, 64($t2) */
  305. 0x04110016, /* bal progflash */
  306. 0x24840200, /* addiu $a0, $a0, 512 */
  307. 0x24A50200, /* addiu $a1, $a1, 512 */
  308. 0x1000FFF7, /* beq $zero, $zero, write_row */
  309. 0x24C6FF80, /* addiu $a2, $a2, -128 */
  310. /* write_word: */
  311. 0x3C15A000, /* lui $s5, 0xa000 */
  312. 0x36B50000, /* ori $s5, $s5, 0x0 */
  313. 0x00952025, /* or $a0, $a0, $s5 */
  314. 0x10000008, /* beq $zero, $zero, next_word */
  315. 0x340B4001, /* ori $t3, $zero, 0x4001 */
  316. /* prog_word: */
  317. 0x8C940000, /* lw $s4, 0($a0) */
  318. 0xAD540030, /* sw $s4, 48($t2) */
  319. 0xAD450020, /* sw $a1, 32($t2) */
  320. 0x04110009, /* bal progflash */
  321. 0x24840004, /* addiu $a0, $a0, 4 */
  322. 0x24A50004, /* addiu $a1, $a1, 4 */
  323. 0x24C6FFFF, /* addiu $a2, $a2, -1 */
  324. /* next_word: */
  325. 0x14C0FFF8, /* bne $a2, $zero, prog_word */
  326. 0x00000000, /* nop */
  327. /* done: */
  328. 0x10000002, /* beq $zero, $zero, exit */
  329. 0x24040000, /* addiu $a0, $zero, 0 */
  330. /* error: */
  331. 0x26240000, /* addiu $a0, $s1, 0 */
  332. /* exit: */
  333. 0x7000003F, /* sdbbp */
  334. /* progflash: */
  335. 0xAD4B0000, /* sw $t3, 0($t2) */
  336. 0xAD480010, /* sw $t0, 16($t2) */
  337. 0xAD490010, /* sw $t1, 16($t2) */
  338. 0xAD4C0008, /* sw $t4, 8($t2) */
  339. /* waitflash: */
  340. 0x8D500000, /* lw $s0, 0($t2) */
  341. 0x020C8024, /* and $s0, $s0, $t4 */
  342. 0x1600FFFD, /* bne $s0, $zero, waitflash */
  343. 0x00000000, /* nop */
  344. 0x00000000, /* nop */
  345. 0x00000000, /* nop */
  346. 0x00000000, /* nop */
  347. 0x00000000, /* nop */
  348. 0x8D510000, /* lw $s1, 0($t2) */
  349. 0x30113000, /* andi $s1, $zero, 0x3000 */
  350. 0x1620FFEF, /* bne $s1, $zero, error */
  351. 0xAD4D0004, /* sw $t5, 4($t2) */
  352. 0x03E00008, /* jr $ra */
  353. 0x00000000 /* nop */
  354. };
  355. static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
  356. uint32_t offset, uint32_t count)
  357. {
  358. struct target *target = bank->target;
  359. uint32_t buffer_size = 16384;
  360. struct working_area *write_algorithm;
  361. struct working_area *source;
  362. uint32_t address = bank->base + offset;
  363. struct reg_param reg_params[3];
  364. uint32_t row_size;
  365. int retval = ERROR_OK;
  366. struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
  367. struct mips32_algorithm mips32_info;
  368. /* flash write code */
  369. if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code),
  370. &write_algorithm) != ERROR_OK) {
  371. LOG_WARNING("no working area available, can't do block memory writes");
  372. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  373. };
  374. /* Change values for counters and row size, depending on variant */
  375. if (pic32mx_info->dev_type == MX_1_2) {
  376. /* 128 byte row */
  377. pic32mx_flash_write_code[8] = 0x2CD30020;
  378. pic32mx_flash_write_code[14] = 0x24840080;
  379. pic32mx_flash_write_code[15] = 0x24A50080;
  380. pic32mx_flash_write_code[17] = 0x24C6FFE0;
  381. row_size = 128;
  382. } else {
  383. /* 512 byte row */
  384. pic32mx_flash_write_code[8] = 0x2CD30080;
  385. pic32mx_flash_write_code[14] = 0x24840200;
  386. pic32mx_flash_write_code[15] = 0x24A50200;
  387. pic32mx_flash_write_code[17] = 0x24C6FF80;
  388. row_size = 512;
  389. }
  390. retval = target_write_buffer(target, write_algorithm->address,
  391. sizeof(pic32mx_flash_write_code), (uint8_t *)pic32mx_flash_write_code);
  392. if (retval != ERROR_OK)
  393. return retval;
  394. /* memory buffer */
  395. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  396. buffer_size /= 2;
  397. if (buffer_size <= 256) {
  398. /* we already allocated the writing code, but failed to get a
  399. * buffer, free the algorithm */
  400. target_free_working_area(target, write_algorithm);
  401. LOG_WARNING("no large enough working area available, can't do block memory writes");
  402. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  403. }
  404. }
  405. mips32_info.common_magic = MIPS32_COMMON_MAGIC;
  406. mips32_info.isa_mode = MIPS32_ISA_MIPS32;
  407. init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
  408. init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
  409. init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT);
  410. int row_offset = offset % row_size;
  411. uint8_t *new_buffer = NULL;
  412. if (row_offset && (count >= (row_size / 4))) {
  413. new_buffer = malloc(buffer_size);
  414. if (new_buffer == NULL) {
  415. LOG_ERROR("Out of memory");
  416. return ERROR_FAIL;
  417. }
  418. memset(new_buffer, 0xff, row_offset);
  419. address -= row_offset;
  420. } else
  421. row_offset = 0;
  422. while (count > 0) {
  423. uint32_t status;
  424. uint32_t thisrun_count;
  425. if (row_offset) {
  426. thisrun_count = (count > ((buffer_size - row_offset) / 4)) ?
  427. ((buffer_size - row_offset) / 4) : count;
  428. memcpy(new_buffer + row_offset, buffer, thisrun_count * 4);
  429. retval = target_write_buffer(target, source->address,
  430. row_offset + thisrun_count * 4, new_buffer);
  431. if (retval != ERROR_OK)
  432. break;
  433. } else {
  434. thisrun_count = (count > (buffer_size / 4)) ?
  435. (buffer_size / 4) : count;
  436. retval = target_write_buffer(target, source->address,
  437. thisrun_count * 4, buffer);
  438. if (retval != ERROR_OK)
  439. break;
  440. }
  441. buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
  442. buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
  443. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
  444. retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
  445. write_algorithm->address,
  446. 0, 10000, &mips32_info);
  447. if (retval != ERROR_OK) {
  448. LOG_ERROR("error executing pic32mx flash write algorithm");
  449. retval = ERROR_FLASH_OPERATION_FAILED;
  450. break;
  451. }
  452. status = buf_get_u32(reg_params[0].value, 0, 32);
  453. if (status & NVMCON_NVMERR) {
  454. LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
  455. retval = ERROR_FLASH_OPERATION_FAILED;
  456. break;
  457. }
  458. if (status & NVMCON_LVDERR) {
  459. LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
  460. retval = ERROR_FLASH_OPERATION_FAILED;
  461. break;
  462. }
  463. buffer += thisrun_count * 4;
  464. address += thisrun_count * 4;
  465. count -= thisrun_count;
  466. if (row_offset) {
  467. address += row_offset;
  468. row_offset = 0;
  469. }
  470. }
  471. target_free_working_area(target, source);
  472. target_free_working_area(target, write_algorithm);
  473. destroy_reg_param(&reg_params[0]);
  474. destroy_reg_param(&reg_params[1]);
  475. destroy_reg_param(&reg_params[2]);
  476. if (new_buffer != NULL)
  477. free(new_buffer);
  478. return retval;
  479. }
  480. static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word)
  481. {
  482. struct target *target = bank->target;
  483. target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
  484. target_write_u32(target, PIC32MX_NVMDATA, word);
  485. return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
  486. }
  487. static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  488. {
  489. uint32_t words_remaining = (count / 4);
  490. uint32_t bytes_remaining = (count & 0x00000003);
  491. uint32_t address = bank->base + offset;
  492. uint32_t bytes_written = 0;
  493. uint32_t status;
  494. int retval;
  495. if (bank->target->state != TARGET_HALTED) {
  496. LOG_ERROR("Target not halted");
  497. return ERROR_TARGET_NOT_HALTED;
  498. }
  499. LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
  500. " count: 0x%8.8" PRIx32 "", bank->base, offset, count);
  501. if (offset & 0x3) {
  502. LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
  503. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  504. }
  505. /* multiple words (4-byte) to be programmed? */
  506. if (words_remaining > 0) {
  507. /* try using a block write */
  508. retval = pic32mx_write_block(bank, buffer, offset, words_remaining);
  509. if (retval != ERROR_OK) {
  510. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  511. /* if block write failed (no sufficient working area),
  512. * we use normal (slow) single dword accesses */
  513. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  514. } else if (retval == ERROR_FLASH_OPERATION_FAILED) {
  515. LOG_ERROR("flash writing failed");
  516. return retval;
  517. }
  518. } else {
  519. buffer += words_remaining * 4;
  520. address += words_remaining * 4;
  521. words_remaining = 0;
  522. }
  523. }
  524. while (words_remaining > 0) {
  525. uint32_t value;
  526. memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
  527. status = pic32mx_write_word(bank, address, value);
  528. if (status & NVMCON_NVMERR) {
  529. LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
  530. return ERROR_FLASH_OPERATION_FAILED;
  531. }
  532. if (status & NVMCON_LVDERR) {
  533. LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
  534. return ERROR_FLASH_OPERATION_FAILED;
  535. }
  536. bytes_written += 4;
  537. words_remaining--;
  538. address += 4;
  539. }
  540. if (bytes_remaining) {
  541. uint32_t value = 0xffffffff;
  542. memcpy(&value, buffer + bytes_written, bytes_remaining);
  543. status = pic32mx_write_word(bank, address, value);
  544. if (status & NVMCON_NVMERR) {
  545. LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
  546. return ERROR_FLASH_OPERATION_FAILED;
  547. }
  548. if (status & NVMCON_LVDERR) {
  549. LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
  550. return ERROR_FLASH_OPERATION_FAILED;
  551. }
  552. }
  553. return ERROR_OK;
  554. }
  555. static int pic32mx_probe(struct flash_bank *bank)
  556. {
  557. struct target *target = bank->target;
  558. struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
  559. struct mips32_common *mips32 = target->arch_info;
  560. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  561. int i;
  562. uint32_t num_pages = 0;
  563. uint32_t device_id;
  564. int page_size;
  565. pic32mx_info->probed = 0;
  566. device_id = ejtag_info->idcode;
  567. LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
  568. device_id,
  569. (unsigned)((device_id >> 1) & 0x7ff),
  570. (unsigned)((device_id >> 12) & 0xffff),
  571. (unsigned)((device_id >> 28) & 0xf));
  572. if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
  573. LOG_WARNING("Cannot identify target as a PIC32MX family.");
  574. return ERROR_FLASH_OPERATION_FAILED;
  575. }
  576. /* Check for PIC32mx1xx/2xx */
  577. for (i = 0; pic32mx_devs[i].name != NULL; i++) {
  578. if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
  579. if ((*(pic32mx_devs[i].name) == '1') || (*(pic32mx_devs[i].name) == '2'))
  580. pic32mx_info->dev_type = MX_1_2;
  581. break;
  582. }
  583. }
  584. if (pic32mx_info->dev_type == MX_1_2)
  585. page_size = 1024;
  586. else
  587. page_size = 4096;
  588. if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
  589. /* 0x1FC00000: Boot flash size */
  590. #if 0
  591. /* for some reason this register returns 8k for the boot bank size
  592. * this does not match the docs, so for now set the boot bank at a
  593. * fixed 12k */
  594. if (target_read_u32(target, PIC32MX_BMXBOOTSZ, &num_pages) != ERROR_OK) {
  595. LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 12k flash");
  596. num_pages = (12 * 1024);
  597. }
  598. #else
  599. /* fixed 12k boot bank - see comments above */
  600. if (pic32mx_info->dev_type == MX_1_2)
  601. num_pages = (3 * 1024);
  602. else
  603. num_pages = (12 * 1024);
  604. #endif
  605. } else {
  606. /* read the flash size from the device */
  607. if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
  608. if (pic32mx_info->dev_type == MX_1_2) {
  609. LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
  610. num_pages = (32 * 1024);
  611. } else {
  612. LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
  613. num_pages = (512 * 1024);
  614. }
  615. }
  616. }
  617. LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
  618. if (bank->sectors) {
  619. free(bank->sectors);
  620. bank->sectors = NULL;
  621. }
  622. /* calculate numbers of pages */
  623. num_pages /= page_size;
  624. bank->size = (num_pages * page_size);
  625. bank->num_sectors = num_pages;
  626. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  627. for (i = 0; i < (int)num_pages; i++) {
  628. bank->sectors[i].offset = i * page_size;
  629. bank->sectors[i].size = page_size;
  630. bank->sectors[i].is_erased = -1;
  631. bank->sectors[i].is_protected = 1;
  632. }
  633. pic32mx_info->probed = 1;
  634. return ERROR_OK;
  635. }
  636. static int pic32mx_auto_probe(struct flash_bank *bank)
  637. {
  638. struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
  639. if (pic32mx_info->probed)
  640. return ERROR_OK;
  641. return pic32mx_probe(bank);
  642. }
  643. static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
  644. {
  645. struct target *target = bank->target;
  646. struct mips32_common *mips32 = target->arch_info;
  647. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  648. uint32_t device_id;
  649. int printed = 0, i;
  650. device_id = ejtag_info->idcode;
  651. if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
  652. snprintf(buf, buf_size,
  653. "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
  654. (unsigned)((device_id >> 1) & 0x7ff),
  655. PIC32MX_MANUF_ID);
  656. return ERROR_FLASH_OPERATION_FAILED;
  657. }
  658. for (i = 0; pic32mx_devs[i].name != NULL; i++) {
  659. if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
  660. printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
  661. break;
  662. }
  663. }
  664. if (pic32mx_devs[i].name == NULL)
  665. printed = snprintf(buf, buf_size, "Unknown");
  666. buf += printed;
  667. buf_size -= printed;
  668. snprintf(buf, buf_size, " Ver: 0x%02x",
  669. (unsigned)((device_id >> 28) & 0xf));
  670. return ERROR_OK;
  671. }
  672. COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
  673. {
  674. uint32_t address, value;
  675. int status, res;
  676. if (CMD_ARGC != 3)
  677. return ERROR_COMMAND_SYNTAX_ERROR;
  678. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
  679. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
  680. struct flash_bank *bank;
  681. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
  682. if (ERROR_OK != retval)
  683. return retval;
  684. if (address < bank->base || address >= (bank->base + bank->size)) {
  685. command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
  686. return ERROR_OK;
  687. }
  688. res = ERROR_OK;
  689. status = pic32mx_write_word(bank, address, value);
  690. if (status & NVMCON_NVMERR)
  691. res = ERROR_FLASH_OPERATION_FAILED;
  692. if (status & NVMCON_LVDERR)
  693. res = ERROR_FLASH_OPERATION_FAILED;
  694. if (res == ERROR_OK)
  695. command_print(CMD_CTX, "pic32mx pgm word complete");
  696. else
  697. command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
  698. return ERROR_OK;
  699. }
  700. COMMAND_HANDLER(pic32mx_handle_unlock_command)
  701. {
  702. uint32_t mchip_cmd;
  703. struct target *target = NULL;
  704. struct mips_m4k_common *mips_m4k;
  705. struct mips_ejtag *ejtag_info;
  706. int timeout = 10;
  707. if (CMD_ARGC < 1) {
  708. command_print(CMD_CTX, "pic32mx unlock <bank>");
  709. return ERROR_COMMAND_SYNTAX_ERROR;
  710. }
  711. struct flash_bank *bank;
  712. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  713. if (ERROR_OK != retval)
  714. return retval;
  715. target = bank->target;
  716. mips_m4k = target_to_m4k(target);
  717. ejtag_info = &mips_m4k->mips32.ejtag_info;
  718. /* we have to use the MTAP to perform a full erase */
  719. mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
  720. mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
  721. /* first check status of device */
  722. mchip_cmd = MCHP_STATUS;
  723. mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
  724. if (mchip_cmd & (1 << 7)) {
  725. /* device is not locked */
  726. command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
  727. }
  728. /* unlock/erase device */
  729. mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
  730. jtag_add_sleep(200);
  731. mips_ejtag_drscan_8_out(ejtag_info, MCHP_ERASE);
  732. do {
  733. mchip_cmd = MCHP_STATUS;
  734. mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
  735. if (timeout-- == 0) {
  736. LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
  737. break;
  738. }
  739. alive_sleep(1);
  740. } while ((mchip_cmd & (1 << 2)) || (!(mchip_cmd & (1 << 3))));
  741. mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
  742. /* select ejtag tap */
  743. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  744. command_print(CMD_CTX, "pic32mx unlocked.\n"
  745. "INFO: a reset or power cycle is required "
  746. "for the new settings to take effect.");
  747. return ERROR_OK;
  748. }
  749. static const struct command_registration pic32mx_exec_command_handlers[] = {
  750. {
  751. .name = "pgm_word",
  752. .usage = "<addr> <value> <bank>",
  753. .handler = pic32mx_handle_pgm_word_command,
  754. .mode = COMMAND_EXEC,
  755. .help = "program a word",
  756. },
  757. {
  758. .name = "unlock",
  759. .handler = pic32mx_handle_unlock_command,
  760. .mode = COMMAND_EXEC,
  761. .usage = "[bank_id]",
  762. .help = "Unlock/Erase entire device.",
  763. },
  764. COMMAND_REGISTRATION_DONE
  765. };
  766. static const struct command_registration pic32mx_command_handlers[] = {
  767. {
  768. .name = "pic32mx",
  769. .mode = COMMAND_ANY,
  770. .help = "pic32mx flash command group",
  771. .usage = "",
  772. .chain = pic32mx_exec_command_handlers,
  773. },
  774. COMMAND_REGISTRATION_DONE
  775. };
  776. struct flash_driver pic32mx_flash = {
  777. .name = "pic32mx",
  778. .commands = pic32mx_command_handlers,
  779. .flash_bank_command = pic32mx_flash_bank_command,
  780. .erase = pic32mx_erase,
  781. .protect = pic32mx_protect,
  782. .write = pic32mx_write,
  783. .read = default_flash_read,
  784. .probe = pic32mx_probe,
  785. .auto_probe = pic32mx_auto_probe,
  786. .erase_check = default_flash_blank_check,
  787. .protect_check = pic32mx_protect_check,
  788. .info = pic32mx_info,
  789. };