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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  22. ***************************************************************************/
  23. /***************************************************************************
  24. * STELLARIS flash is tested on LM3S811, LM3S6965, LM3s3748, more.
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "jtag/interface.h"
  30. #include "imp.h"
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. #define DID0_VER(did0) ((did0 >> 28)&0x07)
  34. /* STELLARIS control registers */
  35. #define SCB_BASE 0x400FE000
  36. #define DID0 0x000
  37. #define DID1 0x004
  38. #define DC0 0x008
  39. #define DC1 0x010
  40. #define DC2 0x014
  41. #define DC3 0x018
  42. #define DC4 0x01C
  43. #define RIS 0x050
  44. #define RCC 0x060
  45. #define PLLCFG 0x064
  46. #define RCC2 0x070
  47. #define NVMSTAT 0x1a0
  48. /* "legacy" flash memory protection registers (64KB max) */
  49. #define FMPRE 0x130
  50. #define FMPPE 0x134
  51. /* new flash memory protection registers (for more than 64KB) */
  52. #define FMPRE0 0x200 /* PRE1 = PRE0 + 4, etc */
  53. #define FMPPE0 0x400 /* PPE1 = PPE0 + 4, etc */
  54. #define USECRL 0x140
  55. #define FLASH_CONTROL_BASE 0x400FD000
  56. #define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
  57. #define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
  58. #define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
  59. #define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
  60. #define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
  61. #define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
  62. #define AMISC 1
  63. #define PMISC 2
  64. #define AMASK 1
  65. #define PMASK 2
  66. /* Flash Controller Command bits */
  67. #define FMC_WRKEY (0xA442 << 16)
  68. #define FMC_COMT (1 << 3)
  69. #define FMC_MERASE (1 << 2)
  70. #define FMC_ERASE (1 << 1)
  71. #define FMC_WRITE (1 << 0)
  72. /* STELLARIS constants */
  73. /* values to write in FMA to commit write-"once" values */
  74. #define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */
  75. #define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */
  76. static void stellaris_read_clock_info(struct flash_bank *bank);
  77. static int stellaris_mass_erase(struct flash_bank *bank);
  78. struct stellaris_flash_bank {
  79. /* chip id register */
  80. uint32_t did0;
  81. uint32_t did1;
  82. uint32_t dc0;
  83. uint32_t dc1;
  84. const char *target_name;
  85. uint8_t target_class;
  86. uint32_t sramsiz;
  87. uint32_t flshsz;
  88. /* flash geometry */
  89. uint32_t num_pages;
  90. uint32_t pagesize;
  91. uint32_t pages_in_lockregion;
  92. /* nv memory bits */
  93. uint16_t num_lockbits;
  94. /* main clock status */
  95. uint32_t rcc;
  96. uint32_t rcc2;
  97. uint8_t mck_valid;
  98. uint8_t xtal_mask;
  99. uint32_t iosc_freq;
  100. uint32_t mck_freq;
  101. const char *iosc_desc;
  102. const char *mck_desc;
  103. };
  104. /* Autogenerated by contrib/gen-stellaris-part-header.pl */
  105. /* From Stellaris Firmware Development Package revision 9453 */
  106. static struct {
  107. uint8_t class;
  108. uint8_t partno;
  109. const char *partname;
  110. } StellarisParts[] = {
  111. {0x00, 0x01, "LM3S101"},
  112. {0x00, 0x02, "LM3S102"},
  113. {0x01, 0xBF, "LM3S1110"},
  114. {0x01, 0xC3, "LM3S1133"},
  115. {0x01, 0xC5, "LM3S1138"},
  116. {0x01, 0xC1, "LM3S1150"},
  117. {0x01, 0xC4, "LM3S1162"},
  118. {0x01, 0xC2, "LM3S1165"},
  119. {0x01, 0xEC, "LM3S1166"},
  120. {0x01, 0xC6, "LM3S1332"},
  121. {0x01, 0xBC, "LM3S1435"},
  122. {0x01, 0xBA, "LM3S1439"},
  123. {0x01, 0xBB, "LM3S1512"},
  124. {0x01, 0xC7, "LM3S1538"},
  125. {0x01, 0xDB, "LM3S1601"},
  126. {0x03, 0x06, "LM3S1607"},
  127. {0x01, 0xDA, "LM3S1608"},
  128. {0x01, 0xC0, "LM3S1620"},
  129. {0x04, 0xCD, "LM3S1621"},
  130. {0x03, 0x03, "LM3S1625"},
  131. {0x03, 0x04, "LM3S1626"},
  132. {0x03, 0x05, "LM3S1627"},
  133. {0x01, 0xB3, "LM3S1635"},
  134. {0x01, 0xEB, "LM3S1636"},
  135. {0x01, 0xBD, "LM3S1637"},
  136. {0x04, 0xB1, "LM3S1651"},
  137. {0x01, 0xB9, "LM3S1751"},
  138. {0x03, 0x10, "LM3S1776"},
  139. {0x04, 0x16, "LM3S1811"},
  140. {0x04, 0x3D, "LM3S1816"},
  141. {0x01, 0xB4, "LM3S1850"},
  142. {0x01, 0xDD, "LM3S1911"},
  143. {0x01, 0xDC, "LM3S1918"},
  144. {0x01, 0xB7, "LM3S1937"},
  145. {0x01, 0xBE, "LM3S1958"},
  146. {0x01, 0xB5, "LM3S1960"},
  147. {0x01, 0xB8, "LM3S1968"},
  148. {0x01, 0xEA, "LM3S1969"},
  149. {0x04, 0xCE, "LM3S1B21"},
  150. {0x06, 0xCA, "LM3S1C21"},
  151. {0x06, 0xCB, "LM3S1C26"},
  152. {0x06, 0x98, "LM3S1C58"},
  153. {0x06, 0xB0, "LM3S1D21"},
  154. {0x06, 0xCC, "LM3S1D26"},
  155. {0x06, 0x1D, "LM3S1F11"},
  156. {0x06, 0x1B, "LM3S1F16"},
  157. {0x06, 0xAF, "LM3S1G21"},
  158. {0x06, 0x95, "LM3S1G58"},
  159. {0x06, 0x1E, "LM3S1H11"},
  160. {0x06, 0x1C, "LM3S1H16"},
  161. {0x04, 0x0F, "LM3S1J11"},
  162. {0x04, 0x3C, "LM3S1J16"},
  163. {0x04, 0x0E, "LM3S1N11"},
  164. {0x04, 0x3B, "LM3S1N16"},
  165. {0x04, 0xB2, "LM3S1P51"},
  166. {0x04, 0x9E, "LM3S1R21"},
  167. {0x04, 0xC9, "LM3S1R26"},
  168. {0x04, 0x30, "LM3S1W16"},
  169. {0x04, 0x2F, "LM3S1Z16"},
  170. {0x01, 0x51, "LM3S2110"},
  171. {0x01, 0x84, "LM3S2139"},
  172. {0x03, 0x39, "LM3S2276"},
  173. {0x01, 0xA2, "LM3S2410"},
  174. {0x01, 0x59, "LM3S2412"},
  175. {0x01, 0x56, "LM3S2432"},
  176. {0x01, 0x5A, "LM3S2533"},
  177. {0x01, 0xE1, "LM3S2601"},
  178. {0x01, 0xE0, "LM3S2608"},
  179. {0x03, 0x33, "LM3S2616"},
  180. {0x01, 0x57, "LM3S2620"},
  181. {0x01, 0x85, "LM3S2637"},
  182. {0x01, 0x53, "LM3S2651"},
  183. {0x03, 0x80, "LM3S2671"},
  184. {0x03, 0x50, "LM3S2678"},
  185. {0x01, 0xA4, "LM3S2730"},
  186. {0x01, 0x52, "LM3S2739"},
  187. {0x03, 0x3A, "LM3S2776"},
  188. {0x04, 0x6D, "LM3S2793"},
  189. {0x01, 0xE3, "LM3S2911"},
  190. {0x01, 0xE2, "LM3S2918"},
  191. {0x01, 0xED, "LM3S2919"},
  192. {0x01, 0x54, "LM3S2939"},
  193. {0x01, 0x8F, "LM3S2948"},
  194. {0x01, 0x58, "LM3S2950"},
  195. {0x01, 0x55, "LM3S2965"},
  196. {0x04, 0x6C, "LM3S2B93"},
  197. {0x06, 0x94, "LM3S2D93"},
  198. {0x06, 0x93, "LM3S2U93"},
  199. {0x00, 0x19, "LM3S300"},
  200. {0x00, 0x11, "LM3S301"},
  201. {0x00, 0x1A, "LM3S308"},
  202. {0x00, 0x12, "LM3S310"},
  203. {0x00, 0x13, "LM3S315"},
  204. {0x00, 0x14, "LM3S316"},
  205. {0x00, 0x17, "LM3S317"},
  206. {0x00, 0x15, "LM3S328"},
  207. {0x03, 0x08, "LM3S3634"},
  208. {0x03, 0x43, "LM3S3651"},
  209. {0x04, 0xC8, "LM3S3654"},
  210. {0x03, 0x44, "LM3S3739"},
  211. {0x03, 0x49, "LM3S3748"},
  212. {0x03, 0x45, "LM3S3749"},
  213. {0x04, 0x42, "LM3S3826"},
  214. {0x04, 0x41, "LM3S3J26"},
  215. {0x04, 0x40, "LM3S3N26"},
  216. {0x04, 0x3F, "LM3S3W26"},
  217. {0x04, 0x3E, "LM3S3Z26"},
  218. {0x03, 0x81, "LM3S5632"},
  219. {0x04, 0x0C, "LM3S5651"},
  220. {0x03, 0x8A, "LM3S5652"},
  221. {0x04, 0x4D, "LM3S5656"},
  222. {0x03, 0x91, "LM3S5662"},
  223. {0x03, 0x96, "LM3S5732"},
  224. {0x03, 0x97, "LM3S5737"},
  225. {0x03, 0xA0, "LM3S5739"},
  226. {0x03, 0x99, "LM3S5747"},
  227. {0x03, 0xA7, "LM3S5749"},
  228. {0x03, 0x9A, "LM3S5752"},
  229. {0x03, 0x9C, "LM3S5762"},
  230. {0x04, 0x69, "LM3S5791"},
  231. {0x04, 0x0B, "LM3S5951"},
  232. {0x04, 0x4E, "LM3S5956"},
  233. {0x04, 0x68, "LM3S5B91"},
  234. {0x06, 0x2E, "LM3S5C31"},
  235. {0x06, 0x2C, "LM3S5C36"},
  236. {0x06, 0x5E, "LM3S5C51"},
  237. {0x06, 0x5B, "LM3S5C56"},
  238. {0x06, 0x5F, "LM3S5D51"},
  239. {0x06, 0x5C, "LM3S5D56"},
  240. {0x06, 0x87, "LM3S5D91"},
  241. {0x06, 0x2D, "LM3S5G31"},
  242. {0x06, 0x1F, "LM3S5G36"},
  243. {0x06, 0x5D, "LM3S5G51"},
  244. {0x06, 0x4F, "LM3S5G56"},
  245. {0x04, 0x09, "LM3S5K31"},
  246. {0x04, 0x4A, "LM3S5K36"},
  247. {0x04, 0x0A, "LM3S5P31"},
  248. {0x04, 0x48, "LM3S5P36"},
  249. {0x04, 0xB6, "LM3S5P3B"},
  250. {0x04, 0x0D, "LM3S5P51"},
  251. {0x04, 0x4C, "LM3S5P56"},
  252. {0x04, 0x07, "LM3S5R31"},
  253. {0x04, 0x4B, "LM3S5R36"},
  254. {0x04, 0x47, "LM3S5T36"},
  255. {0x06, 0x7F, "LM3S5U91"},
  256. {0x04, 0x46, "LM3S5Y36"},
  257. {0x00, 0x2A, "LM3S600"},
  258. {0x00, 0x21, "LM3S601"},
  259. {0x00, 0x2B, "LM3S608"},
  260. {0x00, 0x22, "LM3S610"},
  261. {0x01, 0xA1, "LM3S6100"},
  262. {0x00, 0x23, "LM3S611"},
  263. {0x01, 0x74, "LM3S6110"},
  264. {0x00, 0x24, "LM3S612"},
  265. {0x00, 0x25, "LM3S613"},
  266. {0x00, 0x26, "LM3S615"},
  267. {0x00, 0x28, "LM3S617"},
  268. {0x00, 0x29, "LM3S618"},
  269. {0x00, 0x27, "LM3S628"},
  270. {0x01, 0xA5, "LM3S6420"},
  271. {0x01, 0x82, "LM3S6422"},
  272. {0x01, 0x75, "LM3S6432"},
  273. {0x01, 0x76, "LM3S6537"},
  274. {0x01, 0x71, "LM3S6610"},
  275. {0x01, 0xE7, "LM3S6611"},
  276. {0x01, 0xE6, "LM3S6618"},
  277. {0x01, 0x83, "LM3S6633"},
  278. {0x01, 0x8B, "LM3S6637"},
  279. {0x01, 0xA3, "LM3S6730"},
  280. {0x01, 0x77, "LM3S6753"},
  281. {0x01, 0xE9, "LM3S6911"},
  282. {0x01, 0xE8, "LM3S6918"},
  283. {0x01, 0x89, "LM3S6938"},
  284. {0x01, 0x72, "LM3S6950"},
  285. {0x01, 0x78, "LM3S6952"},
  286. {0x01, 0x73, "LM3S6965"},
  287. {0x06, 0xAA, "LM3S6C11"},
  288. {0x06, 0xAC, "LM3S6C65"},
  289. {0x06, 0x9F, "LM3S6G11"},
  290. {0x06, 0xAB, "LM3S6G65"},
  291. {0x00, 0x38, "LM3S800"},
  292. {0x00, 0x31, "LM3S801"},
  293. {0x00, 0x39, "LM3S808"},
  294. {0x00, 0x32, "LM3S811"},
  295. {0x00, 0x33, "LM3S812"},
  296. {0x00, 0x34, "LM3S815"},
  297. {0x00, 0x36, "LM3S817"},
  298. {0x00, 0x37, "LM3S818"},
  299. {0x00, 0x35, "LM3S828"},
  300. {0x01, 0x64, "LM3S8530"},
  301. {0x01, 0x8E, "LM3S8538"},
  302. {0x01, 0x61, "LM3S8630"},
  303. {0x01, 0x63, "LM3S8730"},
  304. {0x01, 0x8D, "LM3S8733"},
  305. {0x01, 0x86, "LM3S8738"},
  306. {0x01, 0x65, "LM3S8930"},
  307. {0x01, 0x8C, "LM3S8933"},
  308. {0x01, 0x88, "LM3S8938"},
  309. {0x01, 0xA6, "LM3S8962"},
  310. {0x01, 0x62, "LM3S8970"},
  311. {0x01, 0xD7, "LM3S8971"},
  312. {0x06, 0xAE, "LM3S8C62"},
  313. {0x06, 0xAD, "LM3S8G62"},
  314. {0x04, 0xCF, "LM3S9781"},
  315. {0x04, 0x67, "LM3S9790"},
  316. {0x04, 0x6B, "LM3S9792"},
  317. {0x04, 0x2D, "LM3S9971"},
  318. {0x04, 0x20, "LM3S9997"},
  319. {0x04, 0xD0, "LM3S9B81"},
  320. {0x04, 0x66, "LM3S9B90"},
  321. {0x04, 0x6A, "LM3S9B92"},
  322. {0x04, 0x6E, "LM3S9B95"},
  323. {0x04, 0x6F, "LM3S9B96"},
  324. {0x04, 0x1D, "LM3S9BN2"},
  325. {0x04, 0x1E, "LM3S9BN5"},
  326. {0x04, 0x1F, "LM3S9BN6"},
  327. {0x06, 0x70, "LM3S9C97"},
  328. {0x06, 0xA9, "LM3S9D81"},
  329. {0x06, 0x7E, "LM3S9D90"},
  330. {0x06, 0x92, "LM3S9D92"},
  331. {0x06, 0x9D, "LM3S9D96"},
  332. {0x06, 0x7B, "LM3S9DN5"},
  333. {0x06, 0x7C, "LM3S9DN6"},
  334. {0x06, 0x60, "LM3S9G97"},
  335. {0x06, 0x79, "LM3S9GN5"},
  336. {0x04, 0x1B, "LM3S9L71"},
  337. {0x04, 0x18, "LM3S9L97"},
  338. {0x06, 0xA8, "LM3S9U81"},
  339. {0x06, 0x7D, "LM3S9U90"},
  340. {0x06, 0x90, "LM3S9U92"},
  341. {0x06, 0x9B, "LM3S9U96"},
  342. {0x05, 0x18, "LM4F110B2QR"},
  343. {0x05, 0x19, "LM4F110C4QR"},
  344. {0x05, 0x10, "LM4F110E5QR"},
  345. {0x05, 0x11, "LM4F110H5QR"},
  346. {0x05, 0x22, "LM4F111B2QR"},
  347. {0x05, 0x23, "LM4F111C4QR"},
  348. {0x05, 0x20, "LM4F111E5QR"},
  349. {0x05, 0x21, "LM4F111H5QR"},
  350. {0x05, 0x36, "LM4F112C4QC"},
  351. {0x05, 0x30, "LM4F112E5QC"},
  352. {0x05, 0x31, "LM4F112H5QC"},
  353. {0x05, 0x35, "LM4F112H5QD"},
  354. {0x05, 0x01, "LM4F120B2QR"},
  355. {0x05, 0x02, "LM4F120C4QR"},
  356. {0x05, 0x03, "LM4F120E5QR"},
  357. {0x05, 0x04, "LM4F120H5QR"},
  358. {0x05, 0x08, "LM4F121B2QR"},
  359. {0x05, 0x09, "LM4F121C4QR"},
  360. {0x05, 0x0A, "LM4F121E5QR"},
  361. {0x05, 0x0B, "LM4F121H5QR"},
  362. {0x05, 0xD0, "LM4F122C4QC"},
  363. {0x05, 0xD1, "LM4F122E5QC"},
  364. {0x05, 0xD2, "LM4F122H5QC"},
  365. {0x05, 0xD6, "LM4F122H5QD"},
  366. {0x05, 0x48, "LM4F130C4QR"},
  367. {0x05, 0x40, "LM4F130E5QR"},
  368. {0x05, 0x41, "LM4F130H5QR"},
  369. {0x05, 0x52, "LM4F131C4QR"},
  370. {0x05, 0x50, "LM4F131E5QR"},
  371. {0x05, 0x51, "LM4F131H5QR"},
  372. {0x05, 0x66, "LM4F132C4QC"},
  373. {0x05, 0x60, "LM4F132E5QC"},
  374. {0x05, 0x61, "LM4F132H5QC"},
  375. {0x05, 0x65, "LM4F132H5QD"},
  376. {0x05, 0x70, "LM4F210E5QR"},
  377. {0x05, 0x73, "LM4F210H5QR"},
  378. {0x05, 0x80, "LM4F211E5QR"},
  379. {0x05, 0x83, "LM4F211H5QR"},
  380. {0x05, 0xE9, "LM4F212H5BB"},
  381. {0x05, 0xC4, "LM4F212H5QC"},
  382. {0x05, 0xC6, "LM4F212H5QD"},
  383. {0x05, 0xA0, "LM4F230E5QR"},
  384. {0x05, 0xA1, "LM4F230H5QR"},
  385. {0x05, 0xB0, "LM4F231E5QR"},
  386. {0x05, 0xB1, "LM4F231H5QR"},
  387. {0x05, 0xC0, "LM4F232E5QC"},
  388. {0x05, 0xE3, "LM4F232H5BB"},
  389. {0x05, 0xC1, "LM4F232H5QC"},
  390. {0x05, 0xC5, "LM4F232H5QD"},
  391. {0x05, 0xE5, "LM4FS1AH5BB"},
  392. {0x05, 0xEA, "LM4FS1GH5BB"},
  393. {0x05, 0xE4, "LM4FS99H5BB"},
  394. {0x05, 0xE1, "LM4FSXLH5BB"},
  395. {0xFF, 0x00, "Unknown Part"}
  396. };
  397. static char *StellarisClassname[7] = {
  398. "Sandstorm",
  399. "Fury",
  400. "Unknown",
  401. "DustDevil",
  402. "Tempest",
  403. "Blizzard",
  404. "Firestorm"
  405. };
  406. /***************************************************************************
  407. * openocd command interface *
  408. ***************************************************************************/
  409. /* flash_bank stellaris <base> <size> 0 0 <target#>
  410. */
  411. FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
  412. {
  413. struct stellaris_flash_bank *stellaris_info;
  414. if (CMD_ARGC < 6)
  415. return ERROR_COMMAND_SYNTAX_ERROR;
  416. stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
  417. bank->base = 0x0;
  418. bank->driver_priv = stellaris_info;
  419. stellaris_info->target_name = "Unknown target";
  420. /* part wasn't probed for info yet */
  421. stellaris_info->did1 = 0;
  422. /* TODO Specify the main crystal speed in kHz using an optional
  423. * argument; ditto, the speed of an external oscillator used
  424. * instead of a crystal. Avoid programming flash using IOSC.
  425. */
  426. return ERROR_OK;
  427. }
  428. static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
  429. {
  430. int printed;
  431. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  432. if (stellaris_info->did1 == 0)
  433. return ERROR_FLASH_BANK_NOT_PROBED;
  434. /* Read main and master clock freqency register */
  435. stellaris_read_clock_info(bank);
  436. printed = snprintf(buf,
  437. buf_size,
  438. "\nTI/LMI Stellaris information: Chip is "
  439. "class %i (%s) %s rev %c%i\n",
  440. stellaris_info->target_class,
  441. StellarisClassname[stellaris_info->target_class],
  442. stellaris_info->target_name,
  443. (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
  444. (int)((stellaris_info->did0) & 0xFF));
  445. buf += printed;
  446. buf_size -= printed;
  447. printed = snprintf(buf,
  448. buf_size,
  449. "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
  450. ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
  451. stellaris_info->did1,
  452. stellaris_info->did1,
  453. "ARMv7M",
  454. (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
  455. (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
  456. buf += printed;
  457. buf_size -= printed;
  458. printed = snprintf(buf,
  459. buf_size,
  460. "master clock: %ikHz%s, "
  461. "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
  462. (int)(stellaris_info->mck_freq / 1000),
  463. stellaris_info->mck_desc,
  464. stellaris_info->rcc,
  465. stellaris_info->rcc2);
  466. buf += printed;
  467. buf_size -= printed;
  468. if (stellaris_info->num_lockbits > 0) {
  469. snprintf(buf,
  470. buf_size,
  471. "pagesize: %" PRIi32 ", pages: %d, "
  472. "lockbits: %i, pages per lockbit: %i\n",
  473. stellaris_info->pagesize,
  474. (unsigned) stellaris_info->num_pages,
  475. stellaris_info->num_lockbits,
  476. (unsigned) stellaris_info->pages_in_lockregion);
  477. }
  478. return ERROR_OK;
  479. }
  480. /***************************************************************************
  481. * chip identification and status *
  482. ***************************************************************************/
  483. /* Set the flash timimg register to match current clocking */
  484. static void stellaris_set_flash_timing(struct flash_bank *bank)
  485. {
  486. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  487. struct target *target = bank->target;
  488. uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
  489. /* only valid for Sandstorm and Fury class devices */
  490. if (stellaris_info->target_class > 1)
  491. return;
  492. LOG_DEBUG("usecrl = %i", (int)(usecrl));
  493. target_write_u32(target, SCB_BASE | USECRL, usecrl);
  494. }
  495. static const unsigned rcc_xtal[32] = {
  496. [0x00] = 1000000, /* no pll */
  497. [0x01] = 1843200, /* no pll */
  498. [0x02] = 2000000, /* no pll */
  499. [0x03] = 2457600, /* no pll */
  500. [0x04] = 3579545,
  501. [0x05] = 3686400,
  502. [0x06] = 4000000, /* usb */
  503. [0x07] = 4096000,
  504. [0x08] = 4915200,
  505. [0x09] = 5000000, /* usb */
  506. [0x0a] = 5120000,
  507. [0x0b] = 6000000, /* (reset) usb */
  508. [0x0c] = 6144000,
  509. [0x0d] = 7372800,
  510. [0x0e] = 8000000, /* usb */
  511. [0x0f] = 8192000,
  512. /* parts before DustDevil use just 4 bits for xtal spec */
  513. [0x10] = 10000000, /* usb */
  514. [0x11] = 12000000, /* usb */
  515. [0x12] = 12288000,
  516. [0x13] = 13560000,
  517. [0x14] = 14318180,
  518. [0x15] = 16000000, /* usb */
  519. [0x16] = 16384000,
  520. };
  521. /** Read clock configuration and set stellaris_info->usec_clocks. */
  522. static void stellaris_read_clock_info(struct flash_bank *bank)
  523. {
  524. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  525. struct target *target = bank->target;
  526. uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
  527. unsigned xtal;
  528. unsigned long mainfreq;
  529. target_read_u32(target, SCB_BASE | RCC, &rcc);
  530. LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
  531. target_read_u32(target, SCB_BASE | RCC2, &rcc2);
  532. LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
  533. target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
  534. LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
  535. stellaris_info->rcc = rcc;
  536. stellaris_info->rcc = rcc2;
  537. sysdiv = (rcc >> 23) & 0xF;
  538. usesysdiv = (rcc >> 22) & 0x1;
  539. bypass = (rcc >> 11) & 0x1;
  540. oscsrc = (rcc >> 4) & 0x3;
  541. xtal = (rcc >> 6) & stellaris_info->xtal_mask;
  542. /* NOTE: post-Sandstorm parts have RCC2 which may override
  543. * parts of RCC ... with more sysdiv options, option for
  544. * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
  545. * as zero, so the "use RCC2" flag is always clear.
  546. */
  547. if (rcc2 & (1 << 31)) {
  548. sysdiv = (rcc2 >> 23) & 0x3F;
  549. bypass = (rcc2 >> 11) & 0x1;
  550. oscsrc = (rcc2 >> 4) & 0x7;
  551. /* FIXME Tempest parts have an additional lsb for
  552. * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
  553. */
  554. }
  555. stellaris_info->mck_desc = "";
  556. switch (oscsrc) {
  557. case 0: /* MOSC */
  558. mainfreq = rcc_xtal[xtal];
  559. break;
  560. case 1: /* IOSC */
  561. mainfreq = stellaris_info->iosc_freq;
  562. stellaris_info->mck_desc = stellaris_info->iosc_desc;
  563. break;
  564. case 2: /* IOSC/4 */
  565. mainfreq = stellaris_info->iosc_freq / 4;
  566. stellaris_info->mck_desc = stellaris_info->iosc_desc;
  567. break;
  568. case 3: /* lowspeed */
  569. /* Sandstorm doesn't have this 30K +/- 30% osc */
  570. mainfreq = 30000;
  571. stellaris_info->mck_desc = " (±30%)";
  572. break;
  573. case 8: /* hibernation osc */
  574. /* not all parts support hibernation */
  575. mainfreq = 32768;
  576. break;
  577. default: /* NOTREACHED */
  578. mainfreq = 0;
  579. break;
  580. }
  581. /* PLL is used if it's not bypassed; its output is 200 MHz
  582. * even when it runs at 400 MHz (adds divide-by-two stage).
  583. */
  584. if (!bypass)
  585. mainfreq = 200000000;
  586. if (usesysdiv)
  587. stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
  588. else
  589. stellaris_info->mck_freq = mainfreq;
  590. }
  591. /* Read device id register, main clock frequency register and fill in driver info structure */
  592. static int stellaris_read_part_info(struct flash_bank *bank)
  593. {
  594. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  595. struct target *target = bank->target;
  596. uint32_t did0, did1, ver, fam;
  597. int i;
  598. /* Read and parse chip identification register */
  599. target_read_u32(target, SCB_BASE | DID0, &did0);
  600. target_read_u32(target, SCB_BASE | DID1, &did1);
  601. target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
  602. target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
  603. LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
  604. did0, did1, stellaris_info->dc0, stellaris_info->dc1);
  605. ver = did0 >> 28;
  606. if ((ver != 0) && (ver != 1)) {
  607. LOG_WARNING("Unknown did0 version, cannot identify target");
  608. return ERROR_FLASH_OPERATION_FAILED;
  609. }
  610. if (did1 == 0) {
  611. LOG_WARNING("Cannot identify target as a Stellaris");
  612. return ERROR_FLASH_OPERATION_FAILED;
  613. }
  614. ver = did1 >> 28;
  615. fam = (did1 >> 24) & 0xF;
  616. if (((ver != 0) && (ver != 1)) || (fam != 0)) {
  617. LOG_WARNING("Unknown did1 version/family.");
  618. return ERROR_FLASH_OPERATION_FAILED;
  619. }
  620. /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
  621. * is 12 MHz, but some older parts have 15 MHz. A few data sheets
  622. * even give _both_ numbers! We'll use current numbers; IOSC is
  623. * always approximate.
  624. *
  625. * For Tempest: IOSC is calibrated, 16 MHz
  626. * For Blizzard: IOSC is calibrated, 16 MHz
  627. * For Firestorm: IOSC is calibrated, 16 MHz
  628. */
  629. stellaris_info->iosc_freq = 12000000;
  630. stellaris_info->iosc_desc = " (±30%)";
  631. stellaris_info->xtal_mask = 0x0f;
  632. /* get device class */
  633. if (DID0_VER(did0) > 0) {
  634. stellaris_info->target_class = (did0 >> 16) & 0xFF;
  635. } else {
  636. /* Sandstorm class */
  637. stellaris_info->target_class = 0;
  638. }
  639. switch (stellaris_info->target_class) {
  640. case 0: /* Sandstorm */
  641. /*
  642. * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
  643. * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
  644. * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
  645. */
  646. if (((did0 >> 8) & 0xff) < 2) {
  647. stellaris_info->iosc_freq = 15000000;
  648. stellaris_info->iosc_desc = " (±50%)";
  649. }
  650. break;
  651. case 1: /* Fury */
  652. break;
  653. case 4: /* Tempest */
  654. case 5: /* Blizzard */
  655. case 6: /* Firestorm */
  656. stellaris_info->iosc_freq = 16000000; /* +/- 1% */
  657. stellaris_info->iosc_desc = " (±1%)";
  658. /* FALL THROUGH */
  659. case 3: /* DustDevil */
  660. stellaris_info->xtal_mask = 0x1f;
  661. break;
  662. default:
  663. LOG_WARNING("Unknown did0 class");
  664. }
  665. for (i = 0; StellarisParts[i].partno; i++) {
  666. if ((StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) &&
  667. (StellarisParts[i].class == stellaris_info->target_class))
  668. break;
  669. }
  670. stellaris_info->target_name = StellarisParts[i].partname;
  671. stellaris_info->did0 = did0;
  672. stellaris_info->did1 = did1;
  673. stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
  674. stellaris_info->num_pages = 2 * (1 + (stellaris_info->dc0 & 0xFFFF));
  675. stellaris_info->pagesize = 1024;
  676. stellaris_info->pages_in_lockregion = 2;
  677. /* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
  678. * That exposes a 32-word Flash Write Buffer ... enabling
  679. * writes of more than one word at a time.
  680. */
  681. return ERROR_OK;
  682. }
  683. /***************************************************************************
  684. * flash operations *
  685. ***************************************************************************/
  686. static int stellaris_protect_check(struct flash_bank *bank)
  687. {
  688. struct stellaris_flash_bank *stellaris = bank->driver_priv;
  689. int status = ERROR_OK;
  690. unsigned i;
  691. unsigned page;
  692. if (stellaris->did1 == 0)
  693. return ERROR_FLASH_BANK_NOT_PROBED;
  694. for (i = 0; i < (unsigned) bank->num_sectors; i++)
  695. bank->sectors[i].is_protected = -1;
  696. /* Read each Flash Memory Protection Program Enable (FMPPE) register
  697. * to report any pages that we can't write. Ignore the Read Enable
  698. * register (FMPRE).
  699. */
  700. for (i = 0, page = 0;
  701. i < DIV_ROUND_UP(stellaris->num_lockbits, 32u);
  702. i++) {
  703. uint32_t lockbits;
  704. status = target_read_u32(bank->target,
  705. SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE),
  706. &lockbits);
  707. LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i,
  708. (unsigned) lockbits, status);
  709. if (status != ERROR_OK)
  710. goto done;
  711. for (unsigned j = 0; j < 32; j++) {
  712. unsigned k;
  713. for (k = 0; k < stellaris->pages_in_lockregion; k++) {
  714. if (page >= (unsigned) bank->num_sectors)
  715. goto done;
  716. bank->sectors[page++].is_protected =
  717. !(lockbits & (1 << j));
  718. }
  719. }
  720. }
  721. done:
  722. return status;
  723. }
  724. static int stellaris_erase(struct flash_bank *bank, int first, int last)
  725. {
  726. int banknr;
  727. uint32_t flash_fmc, flash_cris;
  728. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  729. struct target *target = bank->target;
  730. if (bank->target->state != TARGET_HALTED) {
  731. LOG_ERROR("Target not halted");
  732. return ERROR_TARGET_NOT_HALTED;
  733. }
  734. if (stellaris_info->did1 == 0)
  735. return ERROR_FLASH_BANK_NOT_PROBED;
  736. if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
  737. return ERROR_FLASH_SECTOR_INVALID;
  738. if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
  739. return stellaris_mass_erase(bank);
  740. /* Refresh flash controller timing */
  741. stellaris_read_clock_info(bank);
  742. stellaris_set_flash_timing(bank);
  743. /* Clear and disable flash programming interrupts */
  744. target_write_u32(target, FLASH_CIM, 0);
  745. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  746. /* REVISIT this clobbers state set by any halted firmware ...
  747. * it might want to process those IRQs.
  748. */
  749. for (banknr = first; banknr <= last; banknr++) {
  750. /* Address is first word in page */
  751. target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
  752. /* Write erase command */
  753. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
  754. /* Wait until erase complete */
  755. do {
  756. target_read_u32(target, FLASH_FMC, &flash_fmc);
  757. } while (flash_fmc & FMC_ERASE);
  758. /* Check acess violations */
  759. target_read_u32(target, FLASH_CRIS, &flash_cris);
  760. if (flash_cris & (AMASK)) {
  761. LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "",
  762. banknr, flash_cris);
  763. target_write_u32(target, FLASH_CRIS, 0);
  764. return ERROR_FLASH_OPERATION_FAILED;
  765. }
  766. bank->sectors[banknr].is_erased = 1;
  767. }
  768. return ERROR_OK;
  769. }
  770. static int stellaris_protect(struct flash_bank *bank, int set, int first, int last)
  771. {
  772. uint32_t fmppe, flash_fmc, flash_cris;
  773. int lockregion;
  774. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  775. struct target *target = bank->target;
  776. if (bank->target->state != TARGET_HALTED) {
  777. LOG_ERROR("Target not halted");
  778. return ERROR_TARGET_NOT_HALTED;
  779. }
  780. if (!set) {
  781. LOG_ERROR("Hardware doesn't support page-level unprotect. "
  782. "Try the 'recover' command.");
  783. return ERROR_COMMAND_SYNTAX_ERROR;
  784. }
  785. if (stellaris_info->did1 == 0)
  786. return ERROR_FLASH_BANK_NOT_PROBED;
  787. /* lockregions are 2 pages ... must protect [even..odd] */
  788. if ((first < 0) || (first & 1)
  789. || (last < first) || !(last & 1)
  790. || (last >= 2 * stellaris_info->num_lockbits)) {
  791. LOG_ERROR("Can't protect unaligned or out-of-range pages.");
  792. return ERROR_FLASH_SECTOR_INVALID;
  793. }
  794. /* Refresh flash controller timing */
  795. stellaris_read_clock_info(bank);
  796. stellaris_set_flash_timing(bank);
  797. /* convert from pages to lockregions */
  798. first /= 2;
  799. last /= 2;
  800. /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
  801. * Current parts can be much bigger.
  802. */
  803. if (last >= 32) {
  804. LOG_ERROR("No support yet for protection > 64K");
  805. return ERROR_FLASH_OPERATION_FAILED;
  806. }
  807. target_read_u32(target, SCB_BASE | FMPPE, &fmppe);
  808. for (lockregion = first; lockregion <= last; lockregion++)
  809. fmppe &= ~(1 << lockregion);
  810. /* Clear and disable flash programming interrupts */
  811. target_write_u32(target, FLASH_CIM, 0);
  812. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  813. /* REVISIT this clobbers state set by any halted firmware ...
  814. * it might want to process those IRQs.
  815. */
  816. LOG_DEBUG("fmppe 0x%" PRIx32 "", fmppe);
  817. target_write_u32(target, SCB_BASE | FMPPE, fmppe);
  818. /* Commit FMPPE */
  819. target_write_u32(target, FLASH_FMA, 1);
  820. /* Write commit command */
  821. /* REVISIT safety check, since this cannot be undone
  822. * except by the "Recover a locked device" procedure.
  823. * REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
  824. * inadvisable ... it makes future mass erase operations fail.
  825. */
  826. LOG_WARNING("Flash protection cannot be removed once committed, commit is NOT executed !");
  827. /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
  828. /* Wait until erase complete */
  829. do {
  830. target_read_u32(target, FLASH_FMC, &flash_fmc);
  831. } while (flash_fmc & FMC_COMT);
  832. /* Check acess violations */
  833. target_read_u32(target, FLASH_CRIS, &flash_cris);
  834. if (flash_cris & (AMASK)) {
  835. LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
  836. target_write_u32(target, FLASH_CRIS, 0);
  837. return ERROR_FLASH_OPERATION_FAILED;
  838. }
  839. return ERROR_OK;
  840. }
  841. /* see contib/loaders/flash/stellaris.s for src */
  842. static const uint8_t stellaris_write_code[] = {
  843. /* write: */
  844. 0xDF, 0xF8, 0x40, 0x40, /* ldr r4, pFLASH_CTRL_BASE */
  845. 0xDF, 0xF8, 0x40, 0x50, /* ldr r5, FLASHWRITECMD */
  846. /* wait_fifo: */
  847. 0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */
  848. 0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */
  849. 0x17, 0xD0, /* beq exit */
  850. 0x47, 0x68, /* ldr r7, [r0, #4] */
  851. 0x47, 0x45, /* cmp r7, r8 */
  852. 0xF7, 0xD0, /* beq wait_fifo */
  853. /* mainloop: */
  854. 0x22, 0x60, /* str r2, [r4, #0] */
  855. 0x02, 0xF1, 0x04, 0x02, /* add r2, r2, #4 */
  856. 0x57, 0xF8, 0x04, 0x8B, /* ldr r8, [r7], #4 */
  857. 0xC4, 0xF8, 0x04, 0x80, /* str r8, [r4, #4] */
  858. 0xA5, 0x60, /* str r5, [r4, #8] */
  859. /* busy: */
  860. 0xD4, 0xF8, 0x08, 0x80, /* ldr r8, [r4, #8] */
  861. 0x18, 0xF0, 0x01, 0x0F, /* tst r8, #1 */
  862. 0xFA, 0xD1, /* bne busy */
  863. 0x8F, 0x42, /* cmp r7, r1 */
  864. 0x28, 0xBF, /* it cs */
  865. 0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */
  866. 0x47, 0x60, /* str r7, [r0, #4] */
  867. 0x01, 0x3B, /* subs r3, r3, #1 */
  868. 0x03, 0xB1, /* cbz r3, exit */
  869. 0xE2, 0xE7, /* b wait_fifo */
  870. /* exit: */
  871. 0x00, 0xBE, /* bkpt #0 */
  872. /* pFLASH_CTRL_BASE: */
  873. 0x00, 0xD0, 0x0F, 0x40, /* .word 0x400FD000 */
  874. /* FLASHWRITECMD: */
  875. 0x01, 0x00, 0x42, 0xA4 /* .word 0xA4420001 */
  876. };
  877. static int stellaris_write_block(struct flash_bank *bank,
  878. uint8_t *buffer, uint32_t offset, uint32_t wcount)
  879. {
  880. struct target *target = bank->target;
  881. uint32_t buffer_size = 16384;
  882. struct working_area *source;
  883. struct working_area *write_algorithm;
  884. uint32_t address = bank->base + offset;
  885. struct reg_param reg_params[4];
  886. struct armv7m_algorithm armv7m_info;
  887. int retval = ERROR_OK;
  888. /* power of two, and multiple of word size */
  889. static const unsigned buf_min = 128;
  890. /* for small buffers it's faster not to download an algorithm */
  891. if (wcount * 4 < buf_min)
  892. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  893. LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
  894. bank, buffer, offset, wcount);
  895. /* flash write code */
  896. if (target_alloc_working_area(target, sizeof(stellaris_write_code),
  897. &write_algorithm) != ERROR_OK) {
  898. LOG_DEBUG("no working area for block memory writes");
  899. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  900. };
  901. /* plus a buffer big enough for this data */
  902. if (wcount * 4 < buffer_size)
  903. buffer_size = wcount * 4;
  904. /* memory buffer */
  905. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  906. buffer_size /= 2;
  907. if (buffer_size <= buf_min) {
  908. target_free_working_area(target, write_algorithm);
  909. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  910. }
  911. LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
  912. target_name(target), (unsigned) buffer_size);
  913. };
  914. target_write_buffer(target, write_algorithm->address,
  915. sizeof(stellaris_write_code),
  916. (uint8_t *) stellaris_write_code);
  917. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  918. armv7m_info.core_mode = ARM_MODE_THREAD;
  919. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  920. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  921. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  922. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  923. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  924. buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
  925. buf_set_u32(reg_params[2].value, 0, 32, address);
  926. buf_set_u32(reg_params[3].value, 0, 32, wcount);
  927. retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
  928. 0, NULL,
  929. 4, reg_params,
  930. source->address, source->size,
  931. write_algorithm->address, 0,
  932. &armv7m_info);
  933. if (retval == ERROR_FLASH_OPERATION_FAILED)
  934. LOG_ERROR("error %d executing stellaris flash write algorithm", retval);
  935. target_free_working_area(target, write_algorithm);
  936. target_free_working_area(target, source);
  937. destroy_reg_param(&reg_params[0]);
  938. destroy_reg_param(&reg_params[1]);
  939. destroy_reg_param(&reg_params[2]);
  940. destroy_reg_param(&reg_params[3]);
  941. return retval;
  942. }
  943. static int stellaris_write(struct flash_bank *bank, uint8_t *buffer,
  944. uint32_t offset, uint32_t count)
  945. {
  946. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  947. struct target *target = bank->target;
  948. uint32_t address = offset;
  949. uint32_t flash_cris, flash_fmc;
  950. uint32_t words_remaining = (count / 4);
  951. uint32_t bytes_remaining = (count & 0x00000003);
  952. uint32_t bytes_written = 0;
  953. int retval;
  954. if (bank->target->state != TARGET_HALTED) {
  955. LOG_ERROR("Target not halted");
  956. return ERROR_TARGET_NOT_HALTED;
  957. }
  958. LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
  959. bank, buffer, offset, count);
  960. if (stellaris_info->did1 == 0)
  961. return ERROR_FLASH_BANK_NOT_PROBED;
  962. if (offset & 0x3) {
  963. LOG_WARNING("offset size must be word aligned");
  964. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  965. }
  966. if (offset + count > bank->size)
  967. return ERROR_FLASH_DST_OUT_OF_BANK;
  968. /* Refresh flash controller timing */
  969. stellaris_read_clock_info(bank);
  970. stellaris_set_flash_timing(bank);
  971. /* Clear and disable flash programming interrupts */
  972. target_write_u32(target, FLASH_CIM, 0);
  973. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  974. /* REVISIT this clobbers state set by any halted firmware ...
  975. * it might want to process those IRQs.
  976. */
  977. /* multiple words to be programmed? */
  978. if (words_remaining > 0) {
  979. /* try using a block write */
  980. retval = stellaris_write_block(bank, buffer, offset,
  981. words_remaining);
  982. if (retval != ERROR_OK) {
  983. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  984. LOG_DEBUG("writing flash word-at-a-time");
  985. } else if (retval == ERROR_FLASH_OPERATION_FAILED) {
  986. /* if an error occured, we examine the reason, and quit */
  987. target_read_u32(target, FLASH_CRIS, &flash_cris);
  988. LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
  989. return ERROR_FLASH_OPERATION_FAILED;
  990. }
  991. } else {
  992. buffer += words_remaining * 4;
  993. address += words_remaining * 4;
  994. words_remaining = 0;
  995. }
  996. }
  997. while (words_remaining > 0) {
  998. if (!(address & 0xff))
  999. LOG_DEBUG("0x%" PRIx32 "", address);
  1000. /* Program one word */
  1001. target_write_u32(target, FLASH_FMA, address);
  1002. target_write_buffer(target, FLASH_FMD, 4, buffer);
  1003. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
  1004. /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
  1005. /* Wait until write complete */
  1006. do {
  1007. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1008. } while (flash_fmc & FMC_WRITE);
  1009. buffer += 4;
  1010. address += 4;
  1011. words_remaining--;
  1012. }
  1013. if (bytes_remaining) {
  1014. uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
  1015. /* copy the last remaining bytes into the write buffer */
  1016. memcpy(last_word, buffer+bytes_written, bytes_remaining);
  1017. if (!(address & 0xff))
  1018. LOG_DEBUG("0x%" PRIx32 "", address);
  1019. /* Program one word */
  1020. target_write_u32(target, FLASH_FMA, address);
  1021. target_write_buffer(target, FLASH_FMD, 4, last_word);
  1022. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
  1023. /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
  1024. /* Wait until write complete */
  1025. do {
  1026. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1027. } while (flash_fmc & FMC_WRITE);
  1028. }
  1029. /* Check access violations */
  1030. target_read_u32(target, FLASH_CRIS, &flash_cris);
  1031. if (flash_cris & (AMASK)) {
  1032. LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
  1033. return ERROR_FLASH_OPERATION_FAILED;
  1034. }
  1035. return ERROR_OK;
  1036. }
  1037. static int stellaris_probe(struct flash_bank *bank)
  1038. {
  1039. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  1040. int retval;
  1041. /* If this is a stellaris chip, it has flash; probe() is just
  1042. * to figure out how much is present. Only do it once.
  1043. */
  1044. if (stellaris_info->did1 != 0)
  1045. return ERROR_OK;
  1046. /* stellaris_read_part_info() already handled error checking and
  1047. * reporting. Note that it doesn't write, so we don't care about
  1048. * whether the target is halted or not.
  1049. */
  1050. retval = stellaris_read_part_info(bank);
  1051. if (retval != ERROR_OK)
  1052. return retval;
  1053. if (bank->sectors) {
  1054. free(bank->sectors);
  1055. bank->sectors = NULL;
  1056. }
  1057. /* provide this for the benefit of the NOR flash framework */
  1058. bank->size = 1024 * stellaris_info->num_pages;
  1059. bank->num_sectors = stellaris_info->num_pages;
  1060. bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
  1061. for (int i = 0; i < bank->num_sectors; i++) {
  1062. bank->sectors[i].offset = i * stellaris_info->pagesize;
  1063. bank->sectors[i].size = stellaris_info->pagesize;
  1064. bank->sectors[i].is_erased = -1;
  1065. bank->sectors[i].is_protected = -1;
  1066. }
  1067. return retval;
  1068. }
  1069. static int stellaris_mass_erase(struct flash_bank *bank)
  1070. {
  1071. struct target *target = NULL;
  1072. struct stellaris_flash_bank *stellaris_info = NULL;
  1073. uint32_t flash_fmc;
  1074. stellaris_info = bank->driver_priv;
  1075. target = bank->target;
  1076. if (target->state != TARGET_HALTED) {
  1077. LOG_ERROR("Target not halted");
  1078. return ERROR_TARGET_NOT_HALTED;
  1079. }
  1080. if (stellaris_info->did1 == 0)
  1081. return ERROR_FLASH_BANK_NOT_PROBED;
  1082. /* Refresh flash controller timing */
  1083. stellaris_read_clock_info(bank);
  1084. stellaris_set_flash_timing(bank);
  1085. /* Clear and disable flash programming interrupts */
  1086. target_write_u32(target, FLASH_CIM, 0);
  1087. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  1088. /* REVISIT this clobbers state set by any halted firmware ...
  1089. * it might want to process those IRQs.
  1090. */
  1091. target_write_u32(target, FLASH_FMA, 0);
  1092. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
  1093. /* Wait until erase complete */
  1094. do {
  1095. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1096. } while (flash_fmc & FMC_MERASE);
  1097. /* if device has > 128k, then second erase cycle is needed
  1098. * this is only valid for older devices, but will not hurt */
  1099. if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000) {
  1100. target_write_u32(target, FLASH_FMA, 0x20000);
  1101. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
  1102. /* Wait until erase complete */
  1103. do {
  1104. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1105. } while (flash_fmc & FMC_MERASE);
  1106. }
  1107. return ERROR_OK;
  1108. }
  1109. COMMAND_HANDLER(stellaris_handle_mass_erase_command)
  1110. {
  1111. int i;
  1112. if (CMD_ARGC < 1)
  1113. return ERROR_COMMAND_SYNTAX_ERROR;
  1114. struct flash_bank *bank;
  1115. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1116. if (ERROR_OK != retval)
  1117. return retval;
  1118. if (stellaris_mass_erase(bank) == ERROR_OK) {
  1119. /* set all sectors as erased */
  1120. for (i = 0; i < bank->num_sectors; i++)
  1121. bank->sectors[i].is_erased = 1;
  1122. command_print(CMD_CTX, "stellaris mass erase complete");
  1123. } else
  1124. command_print(CMD_CTX, "stellaris mass erase failed");
  1125. return ERROR_OK;
  1126. }
  1127. /**
  1128. * Perform the Stellaris "Recovering a 'Locked' Device procedure.
  1129. * This performs a mass erase and then restores all nonvolatile registers
  1130. * (including USER_* registers and flash lock bits) to their defaults.
  1131. * Accordingly, flash can be reprogrammed, and JTAG can be used.
  1132. *
  1133. * NOTE that DustDevil parts (at least rev A0 silicon) have errata which
  1134. * can affect this operation if flash protection has been enabled.
  1135. */
  1136. COMMAND_HANDLER(stellaris_handle_recover_command)
  1137. {
  1138. struct flash_bank *bank;
  1139. int retval;
  1140. retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1141. if (retval != ERROR_OK)
  1142. return retval;
  1143. /* REVISIT ... it may be worth sanity checking that the AP is
  1144. * inactive before we start. ARM documents that switching a DP's
  1145. * mode while it's active can cause fault modes that need a power
  1146. * cycle to recover.
  1147. */
  1148. /* assert SRST */
  1149. if (!(jtag_get_reset_config() & RESET_HAS_SRST)) {
  1150. LOG_ERROR("Can't recover Stellaris flash without SRST");
  1151. return ERROR_FAIL;
  1152. }
  1153. adapter_assert_reset();
  1154. for (int i = 0; i < 5; i++) {
  1155. retval = dap_to_swd(bank->target);
  1156. if (retval != ERROR_OK)
  1157. goto done;
  1158. retval = dap_to_jtag(bank->target);
  1159. if (retval != ERROR_OK)
  1160. goto done;
  1161. }
  1162. /* de-assert SRST */
  1163. adapter_deassert_reset();
  1164. retval = jtag_execute_queue();
  1165. /* wait 400+ msec ... OK, "1+ second" is simpler */
  1166. usleep(1000);
  1167. /* USER INTERVENTION required for the power cycle
  1168. * Restarting OpenOCD is likely needed because of mode switching.
  1169. */
  1170. LOG_INFO("USER ACTION: "
  1171. "power cycle Stellaris chip, then restart OpenOCD.");
  1172. done:
  1173. return retval;
  1174. }
  1175. static const struct command_registration stellaris_exec_command_handlers[] = {
  1176. {
  1177. .name = "mass_erase",
  1178. .usage = "<bank>",
  1179. .handler = stellaris_handle_mass_erase_command,
  1180. .mode = COMMAND_EXEC,
  1181. .help = "erase entire device",
  1182. },
  1183. {
  1184. .name = "recover",
  1185. .handler = stellaris_handle_recover_command,
  1186. .mode = COMMAND_EXEC,
  1187. .usage = "bank_id",
  1188. .help = "recover (and erase) locked device",
  1189. },
  1190. COMMAND_REGISTRATION_DONE
  1191. };
  1192. static const struct command_registration stellaris_command_handlers[] = {
  1193. {
  1194. .name = "stellaris",
  1195. .mode = COMMAND_EXEC,
  1196. .help = "Stellaris flash command group",
  1197. .usage = "",
  1198. .chain = stellaris_exec_command_handlers,
  1199. },
  1200. COMMAND_REGISTRATION_DONE
  1201. };
  1202. struct flash_driver stellaris_flash = {
  1203. .name = "stellaris",
  1204. .commands = stellaris_command_handlers,
  1205. .flash_bank_command = stellaris_flash_bank_command,
  1206. .erase = stellaris_erase,
  1207. .protect = stellaris_protect,
  1208. .write = stellaris_write,
  1209. .read = default_flash_read,
  1210. .probe = stellaris_probe,
  1211. .auto_probe = stellaris_probe,
  1212. .erase_check = default_flash_blank_check,
  1213. .protect_check = stellaris_protect_check,
  1214. .info = get_stellaris_info,
  1215. };