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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Andreas Fritiofson *
  9. * andreas.fritiofson@gmail.com *
  10. *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <helper/binarybuffer.h>
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. /* stm32x register locations */
  34. #define FLASH_REG_BASE_B0 0x40022000
  35. #define FLASH_REG_BASE_B1 0x40022040
  36. #define STM32_FLASH_ACR 0x00
  37. #define STM32_FLASH_KEYR 0x04
  38. #define STM32_FLASH_OPTKEYR 0x08
  39. #define STM32_FLASH_SR 0x0C
  40. #define STM32_FLASH_CR 0x10
  41. #define STM32_FLASH_AR 0x14
  42. #define STM32_FLASH_OBR 0x1C
  43. #define STM32_FLASH_WRPR 0x20
  44. /* TODO: Check if code using these really should be hard coded to bank 0.
  45. * There are valid cases, on dual flash devices the protection of the
  46. * second bank is done on the bank0 reg's. */
  47. #define STM32_FLASH_ACR_B0 0x40022000
  48. #define STM32_FLASH_KEYR_B0 0x40022004
  49. #define STM32_FLASH_OPTKEYR_B0 0x40022008
  50. #define STM32_FLASH_SR_B0 0x4002200C
  51. #define STM32_FLASH_CR_B0 0x40022010
  52. #define STM32_FLASH_AR_B0 0x40022014
  53. #define STM32_FLASH_OBR_B0 0x4002201C
  54. #define STM32_FLASH_WRPR_B0 0x40022020
  55. /* option byte location */
  56. #define STM32_OB_RDP 0x1FFFF800
  57. #define STM32_OB_USER 0x1FFFF802
  58. #define STM32_OB_DATA0 0x1FFFF804
  59. #define STM32_OB_DATA1 0x1FFFF806
  60. #define STM32_OB_WRP0 0x1FFFF808
  61. #define STM32_OB_WRP1 0x1FFFF80A
  62. #define STM32_OB_WRP2 0x1FFFF80C
  63. #define STM32_OB_WRP3 0x1FFFF80E
  64. /* FLASH_CR register bits */
  65. #define FLASH_PG (1 << 0)
  66. #define FLASH_PER (1 << 1)
  67. #define FLASH_MER (1 << 2)
  68. #define FLASH_OPTPG (1 << 4)
  69. #define FLASH_OPTER (1 << 5)
  70. #define FLASH_STRT (1 << 6)
  71. #define FLASH_LOCK (1 << 7)
  72. #define FLASH_OPTWRE (1 << 9)
  73. /* FLASH_SR register bits */
  74. #define FLASH_BSY (1 << 0)
  75. #define FLASH_PGERR (1 << 2)
  76. #define FLASH_WRPRTERR (1 << 4)
  77. #define FLASH_EOP (1 << 5)
  78. /* STM32_FLASH_OBR bit definitions (reading) */
  79. #define OPT_ERROR 0
  80. #define OPT_READOUT 1
  81. #define OPT_RDWDGSW 2
  82. #define OPT_RDRSTSTOP 3
  83. #define OPT_RDRSTSTDBY 4
  84. #define OPT_BFB2 5 /* dual flash bank only */
  85. /* register unlock keys */
  86. #define KEY1 0x45670123
  87. #define KEY2 0xCDEF89AB
  88. /* timeout values */
  89. #define FLASH_WRITE_TIMEOUT 10
  90. #define FLASH_ERASE_TIMEOUT 100
  91. struct stm32x_options {
  92. uint16_t RDP;
  93. uint16_t user_options;
  94. uint16_t user_data;
  95. uint16_t protection[4];
  96. };
  97. struct stm32x_flash_bank {
  98. struct stm32x_options option_bytes;
  99. int ppage_size;
  100. int probed;
  101. bool has_dual_banks;
  102. /* used to access dual flash bank stm32xl */
  103. uint32_t register_base;
  104. uint16_t default_rdp;
  105. int user_data_offset;
  106. int option_offset;
  107. uint32_t user_bank_size;
  108. };
  109. static int stm32x_mass_erase(struct flash_bank *bank);
  110. static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
  111. static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
  112. uint32_t offset, uint32_t count);
  113. /* flash bank stm32x <base> <size> 0 0 <target#>
  114. */
  115. FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
  116. {
  117. struct stm32x_flash_bank *stm32x_info;
  118. if (CMD_ARGC < 6)
  119. return ERROR_COMMAND_SYNTAX_ERROR;
  120. stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
  121. bank->driver_priv = stm32x_info;
  122. stm32x_info->probed = 0;
  123. stm32x_info->has_dual_banks = false;
  124. stm32x_info->register_base = FLASH_REG_BASE_B0;
  125. stm32x_info->user_bank_size = bank->size;
  126. return ERROR_OK;
  127. }
  128. static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
  129. {
  130. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  131. return reg + stm32x_info->register_base;
  132. }
  133. static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
  134. {
  135. struct target *target = bank->target;
  136. return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
  137. }
  138. static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
  139. {
  140. struct target *target = bank->target;
  141. uint32_t status;
  142. int retval = ERROR_OK;
  143. /* wait for busy to clear */
  144. for (;;) {
  145. retval = stm32x_get_flash_status(bank, &status);
  146. if (retval != ERROR_OK)
  147. return retval;
  148. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  149. if ((status & FLASH_BSY) == 0)
  150. break;
  151. if (timeout-- <= 0) {
  152. LOG_ERROR("timed out waiting for flash");
  153. return ERROR_FAIL;
  154. }
  155. alive_sleep(1);
  156. }
  157. if (status & FLASH_WRPRTERR) {
  158. LOG_ERROR("stm32x device protected");
  159. retval = ERROR_FAIL;
  160. }
  161. if (status & FLASH_PGERR) {
  162. LOG_ERROR("stm32x device programming failed");
  163. retval = ERROR_FAIL;
  164. }
  165. /* Clear but report errors */
  166. if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
  167. /* If this operation fails, we ignore it and report the original
  168. * retval
  169. */
  170. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
  171. FLASH_WRPRTERR | FLASH_PGERR);
  172. }
  173. return retval;
  174. }
  175. static int stm32x_check_operation_supported(struct flash_bank *bank)
  176. {
  177. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  178. /* if we have a dual flash bank device then
  179. * we need to perform option byte stuff on bank0 only */
  180. if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
  181. LOG_ERROR("Option Byte Operation's must use bank0");
  182. return ERROR_FLASH_OPERATION_FAILED;
  183. }
  184. return ERROR_OK;
  185. }
  186. static int stm32x_read_options(struct flash_bank *bank)
  187. {
  188. uint32_t optiondata;
  189. struct stm32x_flash_bank *stm32x_info = NULL;
  190. struct target *target = bank->target;
  191. stm32x_info = bank->driver_priv;
  192. /* read current option bytes */
  193. int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
  194. if (retval != ERROR_OK)
  195. return retval;
  196. stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
  197. stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
  198. stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
  199. if (optiondata & (1 << OPT_READOUT))
  200. LOG_INFO("Device Security Bit Set");
  201. /* each bit refers to a 4bank protection */
  202. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
  203. if (retval != ERROR_OK)
  204. return retval;
  205. stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
  206. stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
  207. stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
  208. stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
  209. return ERROR_OK;
  210. }
  211. static int stm32x_erase_options(struct flash_bank *bank)
  212. {
  213. struct stm32x_flash_bank *stm32x_info = NULL;
  214. struct target *target = bank->target;
  215. stm32x_info = bank->driver_priv;
  216. /* read current options */
  217. stm32x_read_options(bank);
  218. /* unlock flash registers */
  219. int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
  223. if (retval != ERROR_OK)
  224. return retval;
  225. /* unlock option flash registers */
  226. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
  227. if (retval != ERROR_OK)
  228. return retval;
  229. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
  230. if (retval != ERROR_OK)
  231. return retval;
  232. /* erase option bytes */
  233. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
  234. if (retval != ERROR_OK)
  235. return retval;
  236. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
  237. if (retval != ERROR_OK)
  238. return retval;
  239. retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
  240. if (retval != ERROR_OK)
  241. return retval;
  242. /* clear readout protection and complementary option bytes
  243. * this will also force a device unlock if set */
  244. stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
  245. return ERROR_OK;
  246. }
  247. static int stm32x_write_options(struct flash_bank *bank)
  248. {
  249. struct stm32x_flash_bank *stm32x_info = NULL;
  250. struct target *target = bank->target;
  251. stm32x_info = bank->driver_priv;
  252. /* unlock flash registers */
  253. int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
  254. if (retval != ERROR_OK)
  255. return retval;
  256. retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
  257. if (retval != ERROR_OK)
  258. return retval;
  259. /* unlock option flash registers */
  260. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
  261. if (retval != ERROR_OK)
  262. return retval;
  263. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
  264. if (retval != ERROR_OK)
  265. return retval;
  266. /* program option bytes */
  267. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
  268. if (retval != ERROR_OK)
  269. return retval;
  270. uint8_t opt_bytes[16];
  271. target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
  272. target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
  273. target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
  274. target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
  275. target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
  276. target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
  277. target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
  278. target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
  279. uint32_t offset = STM32_OB_RDP - bank->base;
  280. retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
  281. if (retval != ERROR_OK) {
  282. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  283. LOG_ERROR("working area required to erase options bytes");
  284. return retval;
  285. }
  286. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
  287. if (retval != ERROR_OK)
  288. return retval;
  289. return ERROR_OK;
  290. }
  291. static int stm32x_protect_check(struct flash_bank *bank)
  292. {
  293. struct target *target = bank->target;
  294. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  295. uint32_t protection;
  296. int i, s;
  297. int num_bits;
  298. int set;
  299. if (target->state != TARGET_HALTED) {
  300. LOG_ERROR("Target not halted");
  301. return ERROR_TARGET_NOT_HALTED;
  302. }
  303. int retval = stm32x_check_operation_supported(bank);
  304. if (ERROR_OK != retval)
  305. return retval;
  306. /* medium density - each bit refers to a 4bank protection
  307. * high density - each bit refers to a 2bank protection */
  308. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
  309. if (retval != ERROR_OK)
  310. return retval;
  311. /* medium density - each protection bit is for 4 * 1K pages
  312. * high density - each protection bit is for 2 * 2K pages */
  313. num_bits = (bank->num_sectors / stm32x_info->ppage_size);
  314. if (stm32x_info->ppage_size == 2) {
  315. /* high density flash/connectivity line protection */
  316. set = 1;
  317. if (protection & (1 << 31))
  318. set = 0;
  319. /* bit 31 controls sector 62 - 255 protection for high density
  320. * bit 31 controls sector 62 - 127 protection for connectivity line */
  321. for (s = 62; s < bank->num_sectors; s++)
  322. bank->sectors[s].is_protected = set;
  323. if (bank->num_sectors > 61)
  324. num_bits = 31;
  325. for (i = 0; i < num_bits; i++) {
  326. set = 1;
  327. if (protection & (1 << i))
  328. set = 0;
  329. for (s = 0; s < stm32x_info->ppage_size; s++)
  330. bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
  331. }
  332. } else {
  333. /* low/medium density flash protection */
  334. for (i = 0; i < num_bits; i++) {
  335. set = 1;
  336. if (protection & (1 << i))
  337. set = 0;
  338. for (s = 0; s < stm32x_info->ppage_size; s++)
  339. bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
  340. }
  341. }
  342. return ERROR_OK;
  343. }
  344. static int stm32x_erase(struct flash_bank *bank, int first, int last)
  345. {
  346. struct target *target = bank->target;
  347. int i;
  348. if (bank->target->state != TARGET_HALTED) {
  349. LOG_ERROR("Target not halted");
  350. return ERROR_TARGET_NOT_HALTED;
  351. }
  352. if ((first == 0) && (last == (bank->num_sectors - 1)))
  353. return stm32x_mass_erase(bank);
  354. /* unlock flash registers */
  355. int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  356. if (retval != ERROR_OK)
  357. return retval;
  358. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  359. if (retval != ERROR_OK)
  360. return retval;
  361. for (i = first; i <= last; i++) {
  362. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
  363. if (retval != ERROR_OK)
  364. return retval;
  365. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
  366. bank->base + bank->sectors[i].offset);
  367. if (retval != ERROR_OK)
  368. return retval;
  369. retval = target_write_u32(target,
  370. stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
  371. if (retval != ERROR_OK)
  372. return retval;
  373. retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
  374. if (retval != ERROR_OK)
  375. return retval;
  376. bank->sectors[i].is_erased = 1;
  377. }
  378. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  379. if (retval != ERROR_OK)
  380. return retval;
  381. return ERROR_OK;
  382. }
  383. static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
  384. {
  385. struct stm32x_flash_bank *stm32x_info = NULL;
  386. struct target *target = bank->target;
  387. uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
  388. int i, reg, bit;
  389. int status;
  390. uint32_t protection;
  391. stm32x_info = bank->driver_priv;
  392. if (target->state != TARGET_HALTED) {
  393. LOG_ERROR("Target not halted");
  394. return ERROR_TARGET_NOT_HALTED;
  395. }
  396. int retval = stm32x_check_operation_supported(bank);
  397. if (ERROR_OK != retval)
  398. return retval;
  399. if ((first % stm32x_info->ppage_size) != 0) {
  400. LOG_WARNING("aligned start protect sector to a %d sector boundary",
  401. stm32x_info->ppage_size);
  402. first = first - (first % stm32x_info->ppage_size);
  403. }
  404. if (((last + 1) % stm32x_info->ppage_size) != 0) {
  405. LOG_WARNING("aligned end protect sector to a %d sector boundary",
  406. stm32x_info->ppage_size);
  407. last++;
  408. last = last - (last % stm32x_info->ppage_size);
  409. last--;
  410. }
  411. /* medium density - each bit refers to a 4bank protection
  412. * high density - each bit refers to a 2bank protection */
  413. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
  414. if (retval != ERROR_OK)
  415. return retval;
  416. prot_reg[0] = (uint16_t)protection;
  417. prot_reg[1] = (uint16_t)(protection >> 8);
  418. prot_reg[2] = (uint16_t)(protection >> 16);
  419. prot_reg[3] = (uint16_t)(protection >> 24);
  420. if (stm32x_info->ppage_size == 2) {
  421. /* high density flash */
  422. /* bit 7 controls sector 62 - 255 protection */
  423. if (last > 61) {
  424. if (set)
  425. prot_reg[3] &= ~(1 << 7);
  426. else
  427. prot_reg[3] |= (1 << 7);
  428. }
  429. if (first > 61)
  430. first = 62;
  431. if (last > 61)
  432. last = 61;
  433. for (i = first; i <= last; i++) {
  434. reg = (i / stm32x_info->ppage_size) / 8;
  435. bit = (i / stm32x_info->ppage_size) - (reg * 8);
  436. if (set)
  437. prot_reg[reg] &= ~(1 << bit);
  438. else
  439. prot_reg[reg] |= (1 << bit);
  440. }
  441. } else {
  442. /* medium density flash */
  443. for (i = first; i <= last; i++) {
  444. reg = (i / stm32x_info->ppage_size) / 8;
  445. bit = (i / stm32x_info->ppage_size) - (reg * 8);
  446. if (set)
  447. prot_reg[reg] &= ~(1 << bit);
  448. else
  449. prot_reg[reg] |= (1 << bit);
  450. }
  451. }
  452. status = stm32x_erase_options(bank);
  453. if (status != ERROR_OK)
  454. return status;
  455. stm32x_info->option_bytes.protection[0] = prot_reg[0];
  456. stm32x_info->option_bytes.protection[1] = prot_reg[1];
  457. stm32x_info->option_bytes.protection[2] = prot_reg[2];
  458. stm32x_info->option_bytes.protection[3] = prot_reg[3];
  459. return stm32x_write_options(bank);
  460. }
  461. static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
  462. uint32_t offset, uint32_t count)
  463. {
  464. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  465. struct target *target = bank->target;
  466. uint32_t buffer_size = 16384;
  467. struct working_area *write_algorithm;
  468. struct working_area *source;
  469. uint32_t address = bank->base + offset;
  470. struct reg_param reg_params[5];
  471. struct armv7m_algorithm armv7m_info;
  472. int retval = ERROR_OK;
  473. /* see contrib/loaders/flash/stm32f1x.S for src */
  474. static const uint8_t stm32x_flash_write_code[] = {
  475. /* #define STM32_FLASH_SR_OFFSET 0x0C */
  476. /* wait_fifo: */
  477. 0x16, 0x68, /* ldr r6, [r2, #0] */
  478. 0x00, 0x2e, /* cmp r6, #0 */
  479. 0x18, 0xd0, /* beq exit */
  480. 0x55, 0x68, /* ldr r5, [r2, #4] */
  481. 0xb5, 0x42, /* cmp r5, r6 */
  482. 0xf9, 0xd0, /* beq wait_fifo */
  483. 0x2e, 0x88, /* ldrh r6, [r5, #0] */
  484. 0x26, 0x80, /* strh r6, [r4, #0] */
  485. 0x02, 0x35, /* adds r5, #2 */
  486. 0x02, 0x34, /* adds r4, #2 */
  487. /* busy: */
  488. 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
  489. 0x01, 0x27, /* movs r7, #1 */
  490. 0x3e, 0x42, /* tst r6, r7 */
  491. 0xfb, 0xd1, /* bne busy */
  492. 0x14, 0x27, /* movs r7, #0x14 */
  493. 0x3e, 0x42, /* tst r6, r7 */
  494. 0x08, 0xd1, /* bne error */
  495. 0x9d, 0x42, /* cmp r5, r3 */
  496. 0x01, 0xd3, /* bcc no_wrap */
  497. 0x15, 0x46, /* mov r5, r2 */
  498. 0x08, 0x35, /* adds r5, #8 */
  499. /* no_wrap: */
  500. 0x55, 0x60, /* str r5, [r2, #4] */
  501. 0x01, 0x39, /* subs r1, r1, #1 */
  502. 0x00, 0x29, /* cmp r1, #0 */
  503. 0x02, 0xd0, /* beq exit */
  504. 0xe5, 0xe7, /* b wait_fifo */
  505. /* error: */
  506. 0x00, 0x20, /* movs r0, #0 */
  507. 0x50, 0x60, /* str r0, [r2, #4] */
  508. /* exit: */
  509. 0x30, 0x46, /* mov r0, r6 */
  510. 0x00, 0xbe, /* bkpt #0 */
  511. };
  512. /* flash write code */
  513. if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
  514. &write_algorithm) != ERROR_OK) {
  515. LOG_WARNING("no working area available, can't do block memory writes");
  516. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  517. };
  518. retval = target_write_buffer(target, write_algorithm->address,
  519. sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
  520. if (retval != ERROR_OK)
  521. return retval;
  522. /* memory buffer */
  523. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  524. buffer_size /= 2;
  525. buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
  526. if (buffer_size <= 256) {
  527. /* we already allocated the writing code, but failed to get a
  528. * buffer, free the algorithm */
  529. target_free_working_area(target, write_algorithm);
  530. LOG_WARNING("no large enough working area available, can't do block memory writes");
  531. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  532. }
  533. };
  534. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
  535. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
  536. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
  537. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
  538. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
  539. buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
  540. buf_set_u32(reg_params[1].value, 0, 32, count);
  541. buf_set_u32(reg_params[2].value, 0, 32, source->address);
  542. buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
  543. buf_set_u32(reg_params[4].value, 0, 32, address);
  544. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  545. armv7m_info.core_mode = ARM_MODE_THREAD;
  546. retval = target_run_flash_async_algorithm(target, buffer, count, 2,
  547. 0, NULL,
  548. 5, reg_params,
  549. source->address, source->size,
  550. write_algorithm->address, 0,
  551. &armv7m_info);
  552. if (retval == ERROR_FLASH_OPERATION_FAILED) {
  553. LOG_ERROR("flash write failed at address 0x%"PRIx32,
  554. buf_get_u32(reg_params[4].value, 0, 32));
  555. if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
  556. LOG_ERROR("flash memory not erased before writing");
  557. /* Clear but report errors */
  558. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
  559. }
  560. if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
  561. LOG_ERROR("flash memory write protected");
  562. /* Clear but report errors */
  563. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
  564. }
  565. }
  566. target_free_working_area(target, source);
  567. target_free_working_area(target, write_algorithm);
  568. destroy_reg_param(&reg_params[0]);
  569. destroy_reg_param(&reg_params[1]);
  570. destroy_reg_param(&reg_params[2]);
  571. destroy_reg_param(&reg_params[3]);
  572. destroy_reg_param(&reg_params[4]);
  573. return retval;
  574. }
  575. static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
  576. uint32_t offset, uint32_t count)
  577. {
  578. struct target *target = bank->target;
  579. uint8_t *new_buffer = NULL;
  580. if (bank->target->state != TARGET_HALTED) {
  581. LOG_ERROR("Target not halted");
  582. return ERROR_TARGET_NOT_HALTED;
  583. }
  584. if (offset & 0x1) {
  585. LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
  586. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  587. }
  588. /* If there's an odd number of bytes, the data has to be padded. Duplicate
  589. * the buffer and use the normal code path with a single block write since
  590. * it's probably cheaper than to special case the last odd write using
  591. * discrete accesses. */
  592. if (count & 1) {
  593. new_buffer = malloc(count + 1);
  594. if (new_buffer == NULL) {
  595. LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
  596. return ERROR_FAIL;
  597. }
  598. LOG_INFO("odd number of bytes to write, padding with 0xff");
  599. buffer = memcpy(new_buffer, buffer, count);
  600. buffer[count++] = 0xff;
  601. }
  602. uint32_t words_remaining = count / 2;
  603. int retval, retval2;
  604. /* unlock flash registers */
  605. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  606. if (retval != ERROR_OK)
  607. goto cleanup;
  608. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  609. if (retval != ERROR_OK)
  610. goto cleanup;
  611. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
  612. if (retval != ERROR_OK)
  613. goto cleanup;
  614. /* try using a block write */
  615. retval = stm32x_write_block(bank, buffer, offset, words_remaining);
  616. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  617. /* if block write failed (no sufficient working area),
  618. * we use normal (slow) single halfword accesses */
  619. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  620. while (words_remaining > 0) {
  621. uint16_t value;
  622. memcpy(&value, buffer, sizeof(uint16_t));
  623. retval = target_write_u16(target, bank->base + offset, value);
  624. if (retval != ERROR_OK)
  625. goto reset_pg_and_lock;
  626. retval = stm32x_wait_status_busy(bank, 5);
  627. if (retval != ERROR_OK)
  628. goto reset_pg_and_lock;
  629. words_remaining--;
  630. buffer += 2;
  631. offset += 2;
  632. }
  633. }
  634. reset_pg_and_lock:
  635. retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  636. if (retval == ERROR_OK)
  637. retval = retval2;
  638. cleanup:
  639. if (new_buffer)
  640. free(new_buffer);
  641. return retval;
  642. }
  643. static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
  644. {
  645. /* This check the device CPUID core register to detect
  646. * the M0 from the M3 devices. */
  647. struct target *target = bank->target;
  648. uint32_t cpuid, device_id_register = 0;
  649. /* Get the CPUID from the ARM Core
  650. * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
  651. int retval = target_read_u32(target, 0xE000ED00, &cpuid);
  652. if (retval != ERROR_OK)
  653. return retval;
  654. if (((cpuid >> 4) & 0xFFF) == 0xC20) {
  655. /* 0xC20 is M0 devices */
  656. device_id_register = 0x40015800;
  657. } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
  658. /* 0xC23 is M3 devices */
  659. device_id_register = 0xE0042000;
  660. } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
  661. /* 0xC24 is M4 devices */
  662. device_id_register = 0xE0042000;
  663. } else {
  664. LOG_ERROR("Cannot identify target as a stm32x");
  665. return ERROR_FAIL;
  666. }
  667. /* read stm32 device id register */
  668. retval = target_read_u32(target, device_id_register, device_id);
  669. if (retval != ERROR_OK)
  670. return retval;
  671. return retval;
  672. }
  673. static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
  674. {
  675. struct target *target = bank->target;
  676. uint32_t cpuid, flash_size_reg;
  677. int retval = target_read_u32(target, 0xE000ED00, &cpuid);
  678. if (retval != ERROR_OK)
  679. return retval;
  680. if (((cpuid >> 4) & 0xFFF) == 0xC20) {
  681. /* 0xC20 is M0 devices */
  682. flash_size_reg = 0x1FFFF7CC;
  683. } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
  684. /* 0xC23 is M3 devices */
  685. flash_size_reg = 0x1FFFF7E0;
  686. } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
  687. /* 0xC24 is M4 devices */
  688. flash_size_reg = 0x1FFFF7CC;
  689. } else {
  690. LOG_ERROR("Cannot identify target as a stm32x");
  691. return ERROR_FAIL;
  692. }
  693. retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
  694. if (retval != ERROR_OK)
  695. return retval;
  696. return retval;
  697. }
  698. static int stm32x_probe(struct flash_bank *bank)
  699. {
  700. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  701. int i;
  702. uint16_t flash_size_in_kb;
  703. uint16_t max_flash_size_in_kb;
  704. uint32_t device_id;
  705. int page_size;
  706. uint32_t base_address = 0x08000000;
  707. stm32x_info->probed = 0;
  708. stm32x_info->register_base = FLASH_REG_BASE_B0;
  709. stm32x_info->user_data_offset = 10;
  710. stm32x_info->option_offset = 0;
  711. /* default factory protection level */
  712. stm32x_info->default_rdp = 0x5AA5;
  713. /* read stm32 device id register */
  714. int retval = stm32x_get_device_id(bank, &device_id);
  715. if (retval != ERROR_OK)
  716. return retval;
  717. LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
  718. /* set page size, protection granularity and max flash size depending on family */
  719. switch (device_id & 0xfff) {
  720. case 0x410: /* medium density */
  721. page_size = 1024;
  722. stm32x_info->ppage_size = 4;
  723. max_flash_size_in_kb = 128;
  724. break;
  725. case 0x412: /* low density */
  726. page_size = 1024;
  727. stm32x_info->ppage_size = 4;
  728. max_flash_size_in_kb = 32;
  729. break;
  730. case 0x414: /* high density */
  731. page_size = 2048;
  732. stm32x_info->ppage_size = 2;
  733. max_flash_size_in_kb = 512;
  734. break;
  735. case 0x418: /* connectivity line density */
  736. page_size = 2048;
  737. stm32x_info->ppage_size = 2;
  738. max_flash_size_in_kb = 256;
  739. break;
  740. case 0x420: /* value line density */
  741. page_size = 1024;
  742. stm32x_info->ppage_size = 4;
  743. max_flash_size_in_kb = 128;
  744. break;
  745. case 0x422: /* stm32f30x */
  746. page_size = 2048;
  747. stm32x_info->ppage_size = 2;
  748. max_flash_size_in_kb = 256;
  749. stm32x_info->user_data_offset = 16;
  750. stm32x_info->option_offset = 6;
  751. stm32x_info->default_rdp = 0x55AA;
  752. break;
  753. case 0x428: /* value line High density */
  754. page_size = 2048;
  755. stm32x_info->ppage_size = 4;
  756. max_flash_size_in_kb = 128;
  757. break;
  758. case 0x430: /* xl line density (dual flash banks) */
  759. page_size = 2048;
  760. stm32x_info->ppage_size = 2;
  761. max_flash_size_in_kb = 1024;
  762. stm32x_info->has_dual_banks = true;
  763. break;
  764. case 0x432: /* stm32f37x */
  765. page_size = 2048;
  766. stm32x_info->ppage_size = 2;
  767. max_flash_size_in_kb = 256;
  768. stm32x_info->user_data_offset = 16;
  769. stm32x_info->option_offset = 6;
  770. stm32x_info->default_rdp = 0x55AA;
  771. break;
  772. case 0x440: /* stm32f0x */
  773. page_size = 1024;
  774. stm32x_info->ppage_size = 4;
  775. max_flash_size_in_kb = 64;
  776. stm32x_info->user_data_offset = 16;
  777. stm32x_info->option_offset = 6;
  778. stm32x_info->default_rdp = 0x55AA;
  779. break;
  780. default:
  781. LOG_WARNING("Cannot identify target as a STM32 family.");
  782. return ERROR_FAIL;
  783. }
  784. /* get flash size from target. */
  785. retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
  786. /* failed reading flash size or flash size invalid (early silicon),
  787. * default to max target family */
  788. if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
  789. LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
  790. max_flash_size_in_kb);
  791. flash_size_in_kb = max_flash_size_in_kb;
  792. }
  793. if (stm32x_info->has_dual_banks) {
  794. /* split reported size into matching bank */
  795. if (bank->base != 0x08080000) {
  796. /* bank 0 will be fixed 512k */
  797. flash_size_in_kb = 512;
  798. } else {
  799. flash_size_in_kb -= 512;
  800. /* bank1 also uses a register offset */
  801. stm32x_info->register_base = FLASH_REG_BASE_B1;
  802. base_address = 0x08080000;
  803. }
  804. }
  805. /* if the user sets the size manually then ignore the probed value
  806. * this allows us to work around devices that have a invalid flash size register value */
  807. if (stm32x_info->user_bank_size) {
  808. LOG_INFO("ignoring flash probed value, using configured bank size");
  809. flash_size_in_kb = stm32x_info->user_bank_size / 1024;
  810. }
  811. LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
  812. /* did we assign flash size? */
  813. assert(flash_size_in_kb != 0xffff);
  814. /* calculate numbers of pages */
  815. int num_pages = flash_size_in_kb * 1024 / page_size;
  816. /* check that calculation result makes sense */
  817. assert(num_pages > 0);
  818. if (bank->sectors) {
  819. free(bank->sectors);
  820. bank->sectors = NULL;
  821. }
  822. bank->base = base_address;
  823. bank->size = (num_pages * page_size);
  824. bank->num_sectors = num_pages;
  825. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  826. for (i = 0; i < num_pages; i++) {
  827. bank->sectors[i].offset = i * page_size;
  828. bank->sectors[i].size = page_size;
  829. bank->sectors[i].is_erased = -1;
  830. bank->sectors[i].is_protected = 1;
  831. }
  832. stm32x_info->probed = 1;
  833. return ERROR_OK;
  834. }
  835. static int stm32x_auto_probe(struct flash_bank *bank)
  836. {
  837. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  838. if (stm32x_info->probed)
  839. return ERROR_OK;
  840. return stm32x_probe(bank);
  841. }
  842. #if 0
  843. COMMAND_HANDLER(stm32x_handle_part_id_command)
  844. {
  845. return ERROR_OK;
  846. }
  847. #endif
  848. static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
  849. {
  850. uint32_t device_id;
  851. int printed;
  852. /* read stm32 device id register */
  853. int retval = stm32x_get_device_id(bank, &device_id);
  854. if (retval != ERROR_OK)
  855. return retval;
  856. if ((device_id & 0xfff) == 0x410) {
  857. printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
  858. buf += printed;
  859. buf_size -= printed;
  860. switch (device_id >> 16) {
  861. case 0x0000:
  862. snprintf(buf, buf_size, "A");
  863. break;
  864. case 0x2000:
  865. snprintf(buf, buf_size, "B");
  866. break;
  867. case 0x2001:
  868. snprintf(buf, buf_size, "Z");
  869. break;
  870. case 0x2003:
  871. snprintf(buf, buf_size, "Y");
  872. break;
  873. default:
  874. snprintf(buf, buf_size, "unknown");
  875. break;
  876. }
  877. } else if ((device_id & 0xfff) == 0x412) {
  878. printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
  879. buf += printed;
  880. buf_size -= printed;
  881. switch (device_id >> 16) {
  882. case 0x1000:
  883. snprintf(buf, buf_size, "A");
  884. break;
  885. default:
  886. snprintf(buf, buf_size, "unknown");
  887. break;
  888. }
  889. } else if ((device_id & 0xfff) == 0x414) {
  890. printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
  891. buf += printed;
  892. buf_size -= printed;
  893. switch (device_id >> 16) {
  894. case 0x1000:
  895. snprintf(buf, buf_size, "A");
  896. break;
  897. case 0x1001:
  898. snprintf(buf, buf_size, "Z");
  899. break;
  900. default:
  901. snprintf(buf, buf_size, "unknown");
  902. break;
  903. }
  904. } else if ((device_id & 0xfff) == 0x418) {
  905. printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
  906. buf += printed;
  907. buf_size -= printed;
  908. switch (device_id >> 16) {
  909. case 0x1000:
  910. snprintf(buf, buf_size, "A");
  911. break;
  912. case 0x1001:
  913. snprintf(buf, buf_size, "Z");
  914. break;
  915. default:
  916. snprintf(buf, buf_size, "unknown");
  917. break;
  918. }
  919. } else if ((device_id & 0xfff) == 0x420) {
  920. printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
  921. buf += printed;
  922. buf_size -= printed;
  923. switch (device_id >> 16) {
  924. case 0x1000:
  925. snprintf(buf, buf_size, "A");
  926. break;
  927. case 0x1001:
  928. snprintf(buf, buf_size, "Z");
  929. break;
  930. default:
  931. snprintf(buf, buf_size, "unknown");
  932. break;
  933. }
  934. } else if ((device_id & 0xfff) == 0x422) {
  935. printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
  936. buf += printed;
  937. buf_size -= printed;
  938. switch (device_id >> 16) {
  939. case 0x1000:
  940. snprintf(buf, buf_size, "A");
  941. break;
  942. case 0x1001:
  943. snprintf(buf, buf_size, "Z");
  944. break;
  945. case 0x2000:
  946. snprintf(buf, buf_size, "B");
  947. break;
  948. default:
  949. snprintf(buf, buf_size, "unknown");
  950. break;
  951. }
  952. } else if ((device_id & 0xfff) == 0x428) {
  953. printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
  954. buf += printed;
  955. buf_size -= printed;
  956. switch (device_id >> 16) {
  957. case 0x1000:
  958. snprintf(buf, buf_size, "A");
  959. break;
  960. case 0x1001:
  961. snprintf(buf, buf_size, "Z");
  962. break;
  963. default:
  964. snprintf(buf, buf_size, "unknown");
  965. break;
  966. }
  967. } else if ((device_id & 0xfff) == 0x430) {
  968. printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
  969. buf += printed;
  970. buf_size -= printed;
  971. switch (device_id >> 16) {
  972. case 0x1000:
  973. snprintf(buf, buf_size, "A");
  974. break;
  975. default:
  976. snprintf(buf, buf_size, "unknown");
  977. break;
  978. }
  979. } else if ((device_id & 0xfff) == 0x432) {
  980. printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
  981. buf += printed;
  982. buf_size -= printed;
  983. switch (device_id >> 16) {
  984. case 0x1000:
  985. snprintf(buf, buf_size, "A");
  986. break;
  987. case 0x2000:
  988. snprintf(buf, buf_size, "B");
  989. break;
  990. default:
  991. snprintf(buf, buf_size, "unknown");
  992. break;
  993. }
  994. } else if ((device_id & 0xfff) == 0x440) {
  995. printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
  996. buf += printed;
  997. buf_size -= printed;
  998. switch (device_id >> 16) {
  999. case 0x1000:
  1000. snprintf(buf, buf_size, "1.0");
  1001. break;
  1002. case 0x2000:
  1003. snprintf(buf, buf_size, "2.0");
  1004. break;
  1005. default:
  1006. snprintf(buf, buf_size, "unknown");
  1007. break;
  1008. }
  1009. } else {
  1010. snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
  1011. return ERROR_FAIL;
  1012. }
  1013. return ERROR_OK;
  1014. }
  1015. COMMAND_HANDLER(stm32x_handle_lock_command)
  1016. {
  1017. struct target *target = NULL;
  1018. struct stm32x_flash_bank *stm32x_info = NULL;
  1019. if (CMD_ARGC < 1)
  1020. return ERROR_COMMAND_SYNTAX_ERROR;
  1021. struct flash_bank *bank;
  1022. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1023. if (ERROR_OK != retval)
  1024. return retval;
  1025. stm32x_info = bank->driver_priv;
  1026. target = bank->target;
  1027. if (target->state != TARGET_HALTED) {
  1028. LOG_ERROR("Target not halted");
  1029. return ERROR_TARGET_NOT_HALTED;
  1030. }
  1031. retval = stm32x_check_operation_supported(bank);
  1032. if (ERROR_OK != retval)
  1033. return retval;
  1034. if (stm32x_erase_options(bank) != ERROR_OK) {
  1035. command_print(CMD_CTX, "stm32x failed to erase options");
  1036. return ERROR_OK;
  1037. }
  1038. /* set readout protection */
  1039. stm32x_info->option_bytes.RDP = 0;
  1040. if (stm32x_write_options(bank) != ERROR_OK) {
  1041. command_print(CMD_CTX, "stm32x failed to lock device");
  1042. return ERROR_OK;
  1043. }
  1044. command_print(CMD_CTX, "stm32x locked");
  1045. return ERROR_OK;
  1046. }
  1047. COMMAND_HANDLER(stm32x_handle_unlock_command)
  1048. {
  1049. struct target *target = NULL;
  1050. if (CMD_ARGC < 1)
  1051. return ERROR_COMMAND_SYNTAX_ERROR;
  1052. struct flash_bank *bank;
  1053. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1054. if (ERROR_OK != retval)
  1055. return retval;
  1056. target = bank->target;
  1057. if (target->state != TARGET_HALTED) {
  1058. LOG_ERROR("Target not halted");
  1059. return ERROR_TARGET_NOT_HALTED;
  1060. }
  1061. retval = stm32x_check_operation_supported(bank);
  1062. if (ERROR_OK != retval)
  1063. return retval;
  1064. if (stm32x_erase_options(bank) != ERROR_OK) {
  1065. command_print(CMD_CTX, "stm32x failed to unlock device");
  1066. return ERROR_OK;
  1067. }
  1068. if (stm32x_write_options(bank) != ERROR_OK) {
  1069. command_print(CMD_CTX, "stm32x failed to lock device");
  1070. return ERROR_OK;
  1071. }
  1072. command_print(CMD_CTX, "stm32x unlocked.\n"
  1073. "INFO: a reset or power cycle is required "
  1074. "for the new settings to take effect.");
  1075. return ERROR_OK;
  1076. }
  1077. COMMAND_HANDLER(stm32x_handle_options_read_command)
  1078. {
  1079. uint32_t optionbyte;
  1080. struct target *target = NULL;
  1081. struct stm32x_flash_bank *stm32x_info = NULL;
  1082. if (CMD_ARGC < 1)
  1083. return ERROR_COMMAND_SYNTAX_ERROR;
  1084. struct flash_bank *bank;
  1085. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1086. if (ERROR_OK != retval)
  1087. return retval;
  1088. stm32x_info = bank->driver_priv;
  1089. target = bank->target;
  1090. if (target->state != TARGET_HALTED) {
  1091. LOG_ERROR("Target not halted");
  1092. return ERROR_TARGET_NOT_HALTED;
  1093. }
  1094. retval = stm32x_check_operation_supported(bank);
  1095. if (ERROR_OK != retval)
  1096. return retval;
  1097. retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
  1098. if (retval != ERROR_OK)
  1099. return retval;
  1100. command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
  1101. int user_data = optionbyte;
  1102. if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
  1103. command_print(CMD_CTX, "Option Byte Complement Error");
  1104. if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
  1105. command_print(CMD_CTX, "Readout Protection On");
  1106. else
  1107. command_print(CMD_CTX, "Readout Protection Off");
  1108. /* user option bytes are offset depending on variant */
  1109. optionbyte >>= stm32x_info->option_offset;
  1110. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
  1111. command_print(CMD_CTX, "Software Watchdog");
  1112. else
  1113. command_print(CMD_CTX, "Hardware Watchdog");
  1114. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
  1115. command_print(CMD_CTX, "Stop: No reset generated");
  1116. else
  1117. command_print(CMD_CTX, "Stop: Reset generated");
  1118. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
  1119. command_print(CMD_CTX, "Standby: No reset generated");
  1120. else
  1121. command_print(CMD_CTX, "Standby: Reset generated");
  1122. if (stm32x_info->has_dual_banks) {
  1123. if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
  1124. command_print(CMD_CTX, "Boot: Bank 0");
  1125. else
  1126. command_print(CMD_CTX, "Boot: Bank 1");
  1127. }
  1128. command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
  1129. (user_data >> stm32x_info->user_data_offset) & 0xff);
  1130. command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
  1131. (user_data >> (stm32x_info->user_data_offset + 8)) & 0xff);
  1132. return ERROR_OK;
  1133. }
  1134. COMMAND_HANDLER(stm32x_handle_options_write_command)
  1135. {
  1136. struct target *target = NULL;
  1137. struct stm32x_flash_bank *stm32x_info = NULL;
  1138. uint16_t optionbyte;
  1139. if (CMD_ARGC < 2)
  1140. return ERROR_COMMAND_SYNTAX_ERROR;
  1141. struct flash_bank *bank;
  1142. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1143. if (ERROR_OK != retval)
  1144. return retval;
  1145. stm32x_info = bank->driver_priv;
  1146. target = bank->target;
  1147. if (target->state != TARGET_HALTED) {
  1148. LOG_ERROR("Target not halted");
  1149. return ERROR_TARGET_NOT_HALTED;
  1150. }
  1151. retval = stm32x_check_operation_supported(bank);
  1152. if (ERROR_OK != retval)
  1153. return retval;
  1154. retval = stm32x_read_options(bank);
  1155. if (ERROR_OK != retval)
  1156. return retval;
  1157. /* start with current options */
  1158. optionbyte = stm32x_info->option_bytes.user_options;
  1159. /* skip over flash bank */
  1160. CMD_ARGC--;
  1161. CMD_ARGV++;
  1162. while (CMD_ARGC) {
  1163. if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
  1164. optionbyte |= (1 << 0);
  1165. else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
  1166. optionbyte &= ~(1 << 0);
  1167. else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
  1168. optionbyte &= ~(1 << 1);
  1169. else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
  1170. optionbyte &= ~(1 << 1);
  1171. else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
  1172. optionbyte &= ~(1 << 2);
  1173. else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
  1174. optionbyte &= ~(1 << 2);
  1175. else if (stm32x_info->has_dual_banks) {
  1176. if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
  1177. optionbyte |= (1 << 3);
  1178. else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
  1179. optionbyte &= ~(1 << 3);
  1180. else
  1181. return ERROR_COMMAND_SYNTAX_ERROR;
  1182. } else
  1183. return ERROR_COMMAND_SYNTAX_ERROR;
  1184. CMD_ARGC--;
  1185. CMD_ARGV++;
  1186. }
  1187. if (stm32x_erase_options(bank) != ERROR_OK) {
  1188. command_print(CMD_CTX, "stm32x failed to erase options");
  1189. return ERROR_OK;
  1190. }
  1191. stm32x_info->option_bytes.user_options = optionbyte;
  1192. if (stm32x_write_options(bank) != ERROR_OK) {
  1193. command_print(CMD_CTX, "stm32x failed to write options");
  1194. return ERROR_OK;
  1195. }
  1196. command_print(CMD_CTX, "stm32x write options complete.\n"
  1197. "INFO: a reset or power cycle is required "
  1198. "for the new settings to take effect.");
  1199. return ERROR_OK;
  1200. }
  1201. static int stm32x_mass_erase(struct flash_bank *bank)
  1202. {
  1203. struct target *target = bank->target;
  1204. if (target->state != TARGET_HALTED) {
  1205. LOG_ERROR("Target not halted");
  1206. return ERROR_TARGET_NOT_HALTED;
  1207. }
  1208. /* unlock option flash registers */
  1209. int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  1210. if (retval != ERROR_OK)
  1211. return retval;
  1212. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  1213. if (retval != ERROR_OK)
  1214. return retval;
  1215. /* mass erase flash memory */
  1216. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
  1217. if (retval != ERROR_OK)
  1218. return retval;
  1219. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
  1220. FLASH_MER | FLASH_STRT);
  1221. if (retval != ERROR_OK)
  1222. return retval;
  1223. retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
  1224. if (retval != ERROR_OK)
  1225. return retval;
  1226. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  1227. if (retval != ERROR_OK)
  1228. return retval;
  1229. return ERROR_OK;
  1230. }
  1231. COMMAND_HANDLER(stm32x_handle_mass_erase_command)
  1232. {
  1233. int i;
  1234. if (CMD_ARGC < 1)
  1235. return ERROR_COMMAND_SYNTAX_ERROR;
  1236. struct flash_bank *bank;
  1237. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1238. if (ERROR_OK != retval)
  1239. return retval;
  1240. retval = stm32x_mass_erase(bank);
  1241. if (retval == ERROR_OK) {
  1242. /* set all sectors as erased */
  1243. for (i = 0; i < bank->num_sectors; i++)
  1244. bank->sectors[i].is_erased = 1;
  1245. command_print(CMD_CTX, "stm32x mass erase complete");
  1246. } else
  1247. command_print(CMD_CTX, "stm32x mass erase failed");
  1248. return retval;
  1249. }
  1250. static const struct command_registration stm32x_exec_command_handlers[] = {
  1251. {
  1252. .name = "lock",
  1253. .handler = stm32x_handle_lock_command,
  1254. .mode = COMMAND_EXEC,
  1255. .usage = "bank_id",
  1256. .help = "Lock entire flash device.",
  1257. },
  1258. {
  1259. .name = "unlock",
  1260. .handler = stm32x_handle_unlock_command,
  1261. .mode = COMMAND_EXEC,
  1262. .usage = "bank_id",
  1263. .help = "Unlock entire protected flash device.",
  1264. },
  1265. {
  1266. .name = "mass_erase",
  1267. .handler = stm32x_handle_mass_erase_command,
  1268. .mode = COMMAND_EXEC,
  1269. .usage = "bank_id",
  1270. .help = "Erase entire flash device.",
  1271. },
  1272. {
  1273. .name = "options_read",
  1274. .handler = stm32x_handle_options_read_command,
  1275. .mode = COMMAND_EXEC,
  1276. .usage = "bank_id",
  1277. .help = "Read and display device option byte.",
  1278. },
  1279. {
  1280. .name = "options_write",
  1281. .handler = stm32x_handle_options_write_command,
  1282. .mode = COMMAND_EXEC,
  1283. .usage = "bank_id ('SWWDG'|'HWWDG') "
  1284. "('RSTSTNDBY'|'NORSTSTNDBY') "
  1285. "('RSTSTOP'|'NORSTSTOP')",
  1286. .help = "Replace bits in device option byte.",
  1287. },
  1288. COMMAND_REGISTRATION_DONE
  1289. };
  1290. static const struct command_registration stm32x_command_handlers[] = {
  1291. {
  1292. .name = "stm32f1x",
  1293. .mode = COMMAND_ANY,
  1294. .help = "stm32f1x flash command group",
  1295. .usage = "",
  1296. .chain = stm32x_exec_command_handlers,
  1297. },
  1298. COMMAND_REGISTRATION_DONE
  1299. };
  1300. struct flash_driver stm32f1x_flash = {
  1301. .name = "stm32f1x",
  1302. .commands = stm32x_command_handlers,
  1303. .flash_bank_command = stm32x_flash_bank_command,
  1304. .erase = stm32x_erase,
  1305. .protect = stm32x_protect,
  1306. .write = stm32x_write,
  1307. .read = default_flash_read,
  1308. .probe = stm32x_probe,
  1309. .auto_probe = stm32x_auto_probe,
  1310. .erase_check = default_flash_blank_check,
  1311. .protect_check = stm32x_protect_check,
  1312. .info = get_stm32x_info,
  1313. };