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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Clement Burin des Roziers *
  9. * clement.burin-des-roziers@hikob.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <helper/binarybuffer.h>
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. #include <target/cortex_m.h>
  34. /* stm32lx flash register locations */
  35. #define FLASH_BASE 0x40023C00
  36. #define FLASH_ACR 0x40023C00
  37. #define FLASH_PECR 0x40023C04
  38. #define FLASH_PDKEYR 0x40023C08
  39. #define FLASH_PEKEYR 0x40023C0C
  40. #define FLASH_PRGKEYR 0x40023C10
  41. #define FLASH_OPTKEYR 0x40023C14
  42. #define FLASH_SR 0x40023C18
  43. #define FLASH_OBR 0x40023C1C
  44. #define FLASH_WRPR 0x40023C20
  45. /* FLASH_ACR bites */
  46. #define FLASH_ACR__LATENCY (1<<0)
  47. #define FLASH_ACR__PRFTEN (1<<1)
  48. #define FLASH_ACR__ACC64 (1<<2)
  49. #define FLASH_ACR__SLEEP_PD (1<<3)
  50. #define FLASH_ACR__RUN_PD (1<<4)
  51. /* FLASH_PECR bits */
  52. #define FLASH_PECR__PELOCK (1<<0)
  53. #define FLASH_PECR__PRGLOCK (1<<1)
  54. #define FLASH_PECR__OPTLOCK (1<<2)
  55. #define FLASH_PECR__PROG (1<<3)
  56. #define FLASH_PECR__DATA (1<<4)
  57. #define FLASH_PECR__FTDW (1<<8)
  58. #define FLASH_PECR__ERASE (1<<9)
  59. #define FLASH_PECR__FPRG (1<<10)
  60. #define FLASH_PECR__EOPIE (1<<16)
  61. #define FLASH_PECR__ERRIE (1<<17)
  62. #define FLASH_PECR__OBL_LAUNCH (1<<18)
  63. /* FLASH_SR bits */
  64. #define FLASH_SR__BSY (1<<0)
  65. #define FLASH_SR__EOP (1<<1)
  66. #define FLASH_SR__ENDHV (1<<2)
  67. #define FLASH_SR__READY (1<<3)
  68. #define FLASH_SR__WRPERR (1<<8)
  69. #define FLASH_SR__PGAERR (1<<9)
  70. #define FLASH_SR__SIZERR (1<<10)
  71. #define FLASH_SR__OPTVERR (1<<11)
  72. /* Unlock keys */
  73. #define PEKEY1 0x89ABCDEF
  74. #define PEKEY2 0x02030405
  75. #define PRGKEY1 0x8C9DAEBF
  76. #define PRGKEY2 0x13141516
  77. #define OPTKEY1 0xFBEAD9C8
  78. #define OPTKEY2 0x24252627
  79. /* other registers */
  80. #define DBGMCU_IDCODE 0xE0042000
  81. #define F_SIZE 0x1FF8004C
  82. /* Constants */
  83. #define FLASH_PAGE_SIZE 256
  84. #define FLASH_SECTOR_SIZE 4096
  85. #define FLASH_PAGES_PER_SECTOR 16
  86. #define FLASH_BANK0_ADDRESS 0x08000000
  87. /* stm32lx option byte register location */
  88. #define OB_RDP 0x1FF80000
  89. #define OB_USER 0x1FF80004
  90. #define OB_WRP0_1 0x1FF80008
  91. #define OB_WRP2_3 0x1FF8000C
  92. /* OB_RDP values */
  93. #define OB_RDP__LEVEL0 0xFF5500AA
  94. #define OB_RDP__LEVEL1 0xFFFF0000
  95. /* stm32lx RCC register locations */
  96. #define RCC_CR 0x40023800
  97. #define RCC_ICSCR 0x40023804
  98. #define RCC_CFGR 0x40023808
  99. /* RCC_ICSCR bits */
  100. #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
  101. static int stm32lx_unlock_program_memory(struct flash_bank *bank);
  102. static int stm32lx_lock_program_memory(struct flash_bank *bank);
  103. static int stm32lx_enable_write_half_page(struct flash_bank *bank);
  104. static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
  105. static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
  106. struct stm32lx_flash_bank {
  107. int probed;
  108. bool has_dual_banks;
  109. uint32_t user_bank_size;
  110. };
  111. /* flash bank stm32lx <base> <size> 0 0 <target#>
  112. */
  113. FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
  114. {
  115. struct stm32lx_flash_bank *stm32lx_info;
  116. if (CMD_ARGC < 6)
  117. return ERROR_COMMAND_SYNTAX_ERROR;
  118. /* Create the bank structure */
  119. stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
  120. /* Check allocation */
  121. if (stm32lx_info == NULL) {
  122. LOG_ERROR("failed to allocate bank structure");
  123. return ERROR_FAIL;
  124. }
  125. bank->driver_priv = stm32lx_info;
  126. stm32lx_info->probed = 0;
  127. stm32lx_info->has_dual_banks = false;
  128. stm32lx_info->user_bank_size = bank->size;
  129. return ERROR_OK;
  130. }
  131. static int stm32lx_protect_check(struct flash_bank *bank)
  132. {
  133. int retval;
  134. struct target *target = bank->target;
  135. uint32_t wrpr;
  136. if (target->state != TARGET_HALTED) {
  137. LOG_ERROR("Target not halted");
  138. return ERROR_TARGET_NOT_HALTED;
  139. }
  140. /*
  141. * Read the WRPR word, and check each bit (corresponding to each
  142. * flash sector
  143. */
  144. retval = target_read_u32(target, FLASH_WRPR, &wrpr);
  145. if (retval != ERROR_OK)
  146. return retval;
  147. for (int i = 0; i < 32; i++) {
  148. if (wrpr & (1 << i))
  149. bank->sectors[i].is_protected = 1;
  150. else
  151. bank->sectors[i].is_protected = 0;
  152. }
  153. return ERROR_OK;
  154. }
  155. static int stm32lx_erase(struct flash_bank *bank, int first, int last)
  156. {
  157. int retval;
  158. /*
  159. * It could be possible to do a mass erase if all sectors must be
  160. * erased, but it is not implemented yet.
  161. */
  162. if (bank->target->state != TARGET_HALTED) {
  163. LOG_ERROR("Target not halted");
  164. return ERROR_TARGET_NOT_HALTED;
  165. }
  166. /*
  167. * Loop over the selected sectors and erase them
  168. */
  169. for (int i = first; i <= last; i++) {
  170. retval = stm32lx_erase_sector(bank, i);
  171. if (retval != ERROR_OK)
  172. return retval;
  173. bank->sectors[i].is_erased = 1;
  174. }
  175. return ERROR_OK;
  176. }
  177. static int stm32lx_protect(struct flash_bank *bank, int set, int first,
  178. int last)
  179. {
  180. LOG_WARNING("protection of the STM32L flash is not implemented");
  181. return ERROR_OK;
  182. }
  183. static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
  184. uint32_t offset, uint32_t count)
  185. {
  186. struct target *target = bank->target;
  187. uint32_t buffer_size = 16384;
  188. struct working_area *write_algorithm;
  189. struct working_area *source;
  190. uint32_t address = bank->base + offset;
  191. struct reg_param reg_params[3];
  192. struct armv7m_algorithm armv7m_info;
  193. int retval = ERROR_OK;
  194. /* see contib/loaders/flash/stm32lx.S for src */
  195. static const uint8_t stm32lx_flash_write_code[] = {
  196. /* write_word: */
  197. 0x00, 0x23, /* movs r3, #0 */
  198. 0x04, 0xe0, /* b test_done */
  199. /* write_word: */
  200. 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
  201. 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
  202. 0x01, 0x33, /* adds r3, #1 */
  203. /* test_done: */
  204. 0x93, 0x42, /* cmp r3, r2 */
  205. 0xf8, 0xd3, /* bcc write_word */
  206. 0x00, 0xbe, /* bkpt 0 */
  207. };
  208. /* Check if there is an even number of half pages (128bytes) */
  209. if (count % 128) {
  210. LOG_ERROR("there should be an even number "
  211. "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
  212. return ERROR_FAIL;
  213. }
  214. /* flash write code */
  215. if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
  216. &write_algorithm) != ERROR_OK) {
  217. LOG_DEBUG("no working area for block memory writes");
  218. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  219. };
  220. /* Write the flashing code */
  221. retval = target_write_buffer(target,
  222. write_algorithm->address,
  223. sizeof(stm32lx_flash_write_code),
  224. (uint8_t *)stm32lx_flash_write_code);
  225. if (retval != ERROR_OK) {
  226. target_free_working_area(target, write_algorithm);
  227. return retval;
  228. }
  229. /* Allocate half pages memory */
  230. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  231. if (buffer_size > 1024)
  232. buffer_size -= 1024;
  233. else
  234. buffer_size /= 2;
  235. if (buffer_size <= 256) {
  236. /* we already allocated the writing code, but failed to get a
  237. * buffer, free the algorithm */
  238. target_free_working_area(target, write_algorithm);
  239. LOG_WARNING("no large enough working area available, can't do block memory writes");
  240. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  241. }
  242. }
  243. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  244. armv7m_info.core_mode = ARM_MODE_THREAD;
  245. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  246. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  247. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  248. /* Enable half-page write */
  249. retval = stm32lx_enable_write_half_page(bank);
  250. if (retval != ERROR_OK) {
  251. target_free_working_area(target, source);
  252. target_free_working_area(target, write_algorithm);
  253. destroy_reg_param(&reg_params[0]);
  254. destroy_reg_param(&reg_params[1]);
  255. destroy_reg_param(&reg_params[2]);
  256. return retval;
  257. }
  258. struct armv7m_common *armv7m = target_to_armv7m(target);
  259. if (armv7m == NULL) {
  260. /* something is very wrong if armv7m is NULL */
  261. LOG_ERROR("unable to get armv7m target");
  262. return retval;
  263. }
  264. /* save any DEMCR flags and configure target to catch any Hard Faults */
  265. uint32_t demcr_save = armv7m->demcr;
  266. armv7m->demcr = VC_HARDERR;
  267. /* Loop while there are bytes to write */
  268. while (count > 0) {
  269. uint32_t this_count;
  270. this_count = (count > buffer_size) ? buffer_size : count;
  271. /* Write the next half pages */
  272. retval = target_write_buffer(target, source->address, this_count, buffer);
  273. if (retval != ERROR_OK)
  274. break;
  275. /* 4: Store useful information in the registers */
  276. /* the destination address of the copy (R0) */
  277. buf_set_u32(reg_params[0].value, 0, 32, address);
  278. /* The source address of the copy (R1) */
  279. buf_set_u32(reg_params[1].value, 0, 32, source->address);
  280. /* The length of the copy (R2) */
  281. buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
  282. /* 5: Execute the bunch of code */
  283. retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
  284. / sizeof(*reg_params), reg_params,
  285. write_algorithm->address, 0, 10000, &armv7m_info);
  286. if (retval != ERROR_OK)
  287. break;
  288. /* check for Hard Fault */
  289. if (armv7m->exception_number == 3)
  290. break;
  291. /* 6: Wait while busy */
  292. retval = stm32lx_wait_until_bsy_clear(bank);
  293. if (retval != ERROR_OK)
  294. break;
  295. buffer += this_count;
  296. address += this_count;
  297. count -= this_count;
  298. }
  299. /* restore previous flags */
  300. armv7m->demcr = demcr_save;
  301. if (armv7m->exception_number == 3) {
  302. /* the stm32l15x devices seem to have an issue when blank.
  303. * if a ram loader is executed on a blank device it will
  304. * Hard Fault, this issue does not happen for a already programmed device.
  305. * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
  306. * The workaround of handling the Hard Fault exception does work, but makes the
  307. * loader more complicated, as a compromise we manually write the pages, programming time
  308. * is reduced by 50% using this slower method.
  309. */
  310. LOG_WARNING("couldn't use loader, falling back to page memory writes");
  311. while (count > 0) {
  312. uint32_t this_count;
  313. this_count = (count > 128) ? 128 : count;
  314. /* Write the next half pages */
  315. retval = target_write_buffer(target, address, this_count, buffer);
  316. if (retval != ERROR_OK)
  317. break;
  318. /* Wait while busy */
  319. retval = stm32lx_wait_until_bsy_clear(bank);
  320. if (retval != ERROR_OK)
  321. break;
  322. buffer += this_count;
  323. address += this_count;
  324. count -= this_count;
  325. }
  326. }
  327. if (retval == ERROR_OK)
  328. retval = stm32lx_lock_program_memory(bank);
  329. target_free_working_area(target, source);
  330. target_free_working_area(target, write_algorithm);
  331. destroy_reg_param(&reg_params[0]);
  332. destroy_reg_param(&reg_params[1]);
  333. destroy_reg_param(&reg_params[2]);
  334. return retval;
  335. }
  336. static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
  337. uint32_t offset, uint32_t count)
  338. {
  339. struct target *target = bank->target;
  340. uint32_t halfpages_number;
  341. uint32_t bytes_remaining = 0;
  342. uint32_t address = bank->base + offset;
  343. uint32_t bytes_written = 0;
  344. int retval, retval2;
  345. if (bank->target->state != TARGET_HALTED) {
  346. LOG_ERROR("Target not halted");
  347. return ERROR_TARGET_NOT_HALTED;
  348. }
  349. if (offset & 0x3) {
  350. LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
  351. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  352. }
  353. retval = stm32lx_unlock_program_memory(bank);
  354. if (retval != ERROR_OK)
  355. return retval;
  356. /* first we need to write any unaligned head bytes upto
  357. * the next 128 byte page */
  358. if (offset % 128)
  359. bytes_remaining = MIN(count, 128 - (offset % 128));
  360. while (bytes_remaining > 0) {
  361. uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
  362. /* copy remaining bytes into the write buffer */
  363. uint32_t bytes_to_write = MIN(4, bytes_remaining);
  364. memcpy(value, buffer + bytes_written, bytes_to_write);
  365. retval = target_write_buffer(target, address, 4, value);
  366. if (retval != ERROR_OK)
  367. goto reset_pg_and_lock;
  368. bytes_written += bytes_to_write;
  369. bytes_remaining -= bytes_to_write;
  370. address += 4;
  371. retval = stm32lx_wait_until_bsy_clear(bank);
  372. if (retval != ERROR_OK)
  373. goto reset_pg_and_lock;
  374. }
  375. offset += bytes_written;
  376. count -= bytes_written;
  377. /* this should always pass this check here */
  378. assert((offset % 128) == 0);
  379. /* calculate half pages */
  380. halfpages_number = count / 128;
  381. if (halfpages_number) {
  382. retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, 128 * halfpages_number);
  383. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  384. /* attempt slow memory writes */
  385. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  386. halfpages_number = 0;
  387. } else {
  388. if (retval != ERROR_OK)
  389. return ERROR_FAIL;
  390. }
  391. }
  392. /* write any remaining bytes */
  393. uint32_t page_bytes_written = 128 * halfpages_number;
  394. bytes_written += page_bytes_written;
  395. address += page_bytes_written;
  396. bytes_remaining = count - page_bytes_written;
  397. retval = stm32lx_unlock_program_memory(bank);
  398. if (retval != ERROR_OK)
  399. return retval;
  400. while (bytes_remaining > 0) {
  401. uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
  402. /* copy remaining bytes into the write buffer */
  403. uint32_t bytes_to_write = MIN(4, bytes_remaining);
  404. memcpy(value, buffer + bytes_written, bytes_to_write);
  405. retval = target_write_buffer(target, address, 4, value);
  406. if (retval != ERROR_OK)
  407. goto reset_pg_and_lock;
  408. bytes_written += bytes_to_write;
  409. bytes_remaining -= bytes_to_write;
  410. address += 4;
  411. retval = stm32lx_wait_until_bsy_clear(bank);
  412. if (retval != ERROR_OK)
  413. goto reset_pg_and_lock;
  414. }
  415. reset_pg_and_lock:
  416. retval2 = stm32lx_lock_program_memory(bank);
  417. if (retval == ERROR_OK)
  418. retval = retval2;
  419. return retval;
  420. }
  421. static int stm32lx_probe(struct flash_bank *bank)
  422. {
  423. struct target *target = bank->target;
  424. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  425. int i;
  426. uint16_t flash_size_in_kb;
  427. uint16_t max_flash_size_in_kb;
  428. uint32_t device_id;
  429. uint32_t base_address = FLASH_BANK0_ADDRESS;
  430. uint32_t second_bank_base;
  431. uint32_t first_bank_size_in_kb;
  432. stm32lx_info->probed = 0;
  433. /* read stm32 device id register */
  434. int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
  435. if (retval != ERROR_OK)
  436. return retval;
  437. LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
  438. /* set max flash size depending on family */
  439. switch (device_id & 0xfff) {
  440. case 0x416:
  441. max_flash_size_in_kb = 128;
  442. break;
  443. case 0x427:
  444. /* single bank, high density */
  445. max_flash_size_in_kb = 256;
  446. break;
  447. case 0x436:
  448. /* According to ST, the devices with id 0x436 have dual bank flash and comes with
  449. * a total flash size of 384k or 256kb. However, the first bank is always 192kb,
  450. * and second one holds the rest. The reason is that the 256kb version is actually
  451. * the same physical flash but only the first 256kb are verified.
  452. */
  453. max_flash_size_in_kb = 384;
  454. first_bank_size_in_kb = 192;
  455. stm32lx_info->has_dual_banks = true;
  456. break;
  457. default:
  458. LOG_WARNING("Cannot identify target as a STM32L family.");
  459. return ERROR_FAIL;
  460. }
  461. /* Get the flash size from target. */
  462. retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
  463. /* Failed reading flash size or flash size invalid (early silicon),
  464. * default to max target family */
  465. if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
  466. LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
  467. max_flash_size_in_kb);
  468. flash_size_in_kb = max_flash_size_in_kb;
  469. } else if (flash_size_in_kb > max_flash_size_in_kb) {
  470. LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
  471. flash_size_in_kb, max_flash_size_in_kb, max_flash_size_in_kb);
  472. flash_size_in_kb = max_flash_size_in_kb;
  473. }
  474. if (stm32lx_info->has_dual_banks) {
  475. /* Use the configured base address to determine if this is the first or second flash bank.
  476. * Verify that the base address is reasonably correct and determine the flash bank size
  477. */
  478. second_bank_base = base_address + first_bank_size_in_kb * 1024;
  479. if (bank->base == second_bank_base) {
  480. /* This is the second bank */
  481. base_address = second_bank_base;
  482. flash_size_in_kb = flash_size_in_kb - first_bank_size_in_kb;
  483. } else if (bank->base == 0 || bank->base == base_address) {
  484. /* This is the first bank */
  485. flash_size_in_kb = first_bank_size_in_kb;
  486. } else {
  487. LOG_WARNING("STM32L flash bank base address config is incorrect. 0x%x but should rather be 0x%x or 0x%x",
  488. bank->base, base_address, second_bank_base);
  489. return ERROR_FAIL;
  490. }
  491. LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%x",
  492. bank->bank_number, flash_size_in_kb, base_address);
  493. } else {
  494. LOG_INFO("STM32L flash size is %dkb, base address is 0x%x", flash_size_in_kb, base_address);
  495. }
  496. /* if the user sets the size manually then ignore the probed value
  497. * this allows us to work around devices that have a invalid flash size register value */
  498. if (stm32lx_info->user_bank_size) {
  499. flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
  500. LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
  501. }
  502. /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
  503. * 16 pages for a protection area */
  504. /* calculate numbers of sectors (4kB per sector) */
  505. int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
  506. if (bank->sectors) {
  507. free(bank->sectors);
  508. bank->sectors = NULL;
  509. }
  510. bank->size = flash_size_in_kb * 1024;
  511. bank->base = base_address;
  512. bank->num_sectors = num_sectors;
  513. bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
  514. if (bank->sectors == NULL) {
  515. LOG_ERROR("failed to allocate bank sectors");
  516. return ERROR_FAIL;
  517. }
  518. for (i = 0; i < num_sectors; i++) {
  519. bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
  520. bank->sectors[i].size = FLASH_SECTOR_SIZE;
  521. bank->sectors[i].is_erased = -1;
  522. bank->sectors[i].is_protected = 1;
  523. }
  524. stm32lx_info->probed = 1;
  525. return ERROR_OK;
  526. }
  527. static int stm32lx_auto_probe(struct flash_bank *bank)
  528. {
  529. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  530. if (stm32lx_info->probed)
  531. return ERROR_OK;
  532. return stm32lx_probe(bank);
  533. }
  534. static int stm32lx_erase_check(struct flash_bank *bank)
  535. {
  536. struct target *target = bank->target;
  537. const int buffer_size = 4096;
  538. int i;
  539. uint32_t nBytes;
  540. int retval = ERROR_OK;
  541. if (bank->target->state != TARGET_HALTED) {
  542. LOG_ERROR("Target not halted");
  543. return ERROR_TARGET_NOT_HALTED;
  544. }
  545. uint8_t *buffer = malloc(buffer_size);
  546. if (buffer == NULL) {
  547. LOG_ERROR("failed to allocate read buffer");
  548. return ERROR_FAIL;
  549. }
  550. for (i = 0; i < bank->num_sectors; i++) {
  551. uint32_t j;
  552. bank->sectors[i].is_erased = 1;
  553. /* Loop chunk by chunk over the sector */
  554. for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
  555. uint32_t chunk;
  556. chunk = buffer_size;
  557. if (chunk > (j - bank->sectors[i].size))
  558. chunk = (j - bank->sectors[i].size);
  559. retval = target_read_memory(target, bank->base
  560. + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
  561. if (retval != ERROR_OK)
  562. break;
  563. for (nBytes = 0; nBytes < chunk; nBytes++) {
  564. if (buffer[nBytes] != 0x00) {
  565. bank->sectors[i].is_erased = 0;
  566. break;
  567. }
  568. }
  569. }
  570. if (retval != ERROR_OK)
  571. break;
  572. }
  573. free(buffer);
  574. return retval;
  575. }
  576. static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
  577. {
  578. /* This method must return a string displaying information about the bank */
  579. struct target *target = bank->target;
  580. uint32_t device_id;
  581. int printed;
  582. /* read stm32 device id register */
  583. int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
  584. if (retval != ERROR_OK)
  585. return retval;
  586. if ((device_id & 0xfff) == 0x416) {
  587. printed = snprintf(buf, buf_size, "stm32lx - Rev: ");
  588. buf += printed;
  589. buf_size -= printed;
  590. switch (device_id >> 16) {
  591. case 0x1000:
  592. snprintf(buf, buf_size, "A");
  593. break;
  594. case 0x1008:
  595. snprintf(buf, buf_size, "Y");
  596. break;
  597. case 0x1018:
  598. snprintf(buf, buf_size, "X");
  599. break;
  600. case 0x1038:
  601. snprintf(buf, buf_size, "W");
  602. break;
  603. case 0x1078:
  604. snprintf(buf, buf_size, "V");
  605. break;
  606. default:
  607. snprintf(buf, buf_size, "unknown");
  608. break;
  609. }
  610. } else if ((device_id & 0xfff) == 0x436) {
  611. printed = snprintf(buf, buf_size, "stm32lx (HD) - Rev: ");
  612. buf += printed;
  613. buf_size -= printed;
  614. switch (device_id >> 16) {
  615. case 0x1000:
  616. snprintf(buf, buf_size, "A");
  617. break;
  618. case 0x1008:
  619. snprintf(buf, buf_size, "Z");
  620. break;
  621. case 0x1018:
  622. snprintf(buf, buf_size, "Y");
  623. break;
  624. default:
  625. snprintf(buf, buf_size, "unknown");
  626. break;
  627. }
  628. } else {
  629. snprintf(buf, buf_size, "Cannot identify target as a stm32lx");
  630. return ERROR_FAIL;
  631. }
  632. return ERROR_OK;
  633. }
  634. static const struct command_registration stm32lx_exec_command_handlers[] = {
  635. COMMAND_REGISTRATION_DONE
  636. };
  637. static const struct command_registration stm32lx_command_handlers[] = {
  638. {
  639. .name = "stm32lx",
  640. .mode = COMMAND_ANY,
  641. .help = "stm32lx flash command group",
  642. .usage = "",
  643. .chain = stm32lx_exec_command_handlers,
  644. },
  645. COMMAND_REGISTRATION_DONE
  646. };
  647. struct flash_driver stm32lx_flash = {
  648. .name = "stm32lx",
  649. .commands = stm32lx_command_handlers,
  650. .flash_bank_command = stm32lx_flash_bank_command,
  651. .erase = stm32lx_erase,
  652. .protect = stm32lx_protect,
  653. .write = stm32lx_write,
  654. .read = default_flash_read,
  655. .probe = stm32lx_probe,
  656. .auto_probe = stm32lx_auto_probe,
  657. .erase_check = stm32lx_erase_check,
  658. .protect_check = stm32lx_protect_check,
  659. .info = stm32lx_get_info,
  660. };
  661. /* Static methods implementation */
  662. static int stm32lx_unlock_program_memory(struct flash_bank *bank)
  663. {
  664. struct target *target = bank->target;
  665. int retval;
  666. uint32_t reg32;
  667. /*
  668. * Unlocking the program memory is done by unlocking the PECR,
  669. * then by writing the 2 PRGKEY to the PRGKEYR register
  670. */
  671. /* check flash is not already unlocked */
  672. retval = target_read_u32(target, FLASH_PECR, &reg32);
  673. if (retval != ERROR_OK)
  674. return retval;
  675. if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
  676. return ERROR_OK;
  677. /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
  678. retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
  679. if (retval != ERROR_OK)
  680. return retval;
  681. retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
  682. if (retval != ERROR_OK)
  683. return retval;
  684. /* Make sure it worked */
  685. retval = target_read_u32(target, FLASH_PECR, &reg32);
  686. if (retval != ERROR_OK)
  687. return retval;
  688. if (reg32 & FLASH_PECR__PELOCK) {
  689. LOG_ERROR("PELOCK is not cleared :(");
  690. return ERROR_FLASH_OPERATION_FAILED;
  691. }
  692. retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
  693. if (retval != ERROR_OK)
  694. return retval;
  695. retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
  696. if (retval != ERROR_OK)
  697. return retval;
  698. /* Make sure it worked */
  699. retval = target_read_u32(target, FLASH_PECR, &reg32);
  700. if (retval != ERROR_OK)
  701. return retval;
  702. if (reg32 & FLASH_PECR__PRGLOCK) {
  703. LOG_ERROR("PRGLOCK is not cleared :(");
  704. return ERROR_FLASH_OPERATION_FAILED;
  705. }
  706. return ERROR_OK;
  707. }
  708. static int stm32lx_enable_write_half_page(struct flash_bank *bank)
  709. {
  710. struct target *target = bank->target;
  711. int retval;
  712. uint32_t reg32;
  713. /**
  714. * Unlock the program memory, then set the FPRG bit in the PECR register.
  715. */
  716. retval = stm32lx_unlock_program_memory(bank);
  717. if (retval != ERROR_OK)
  718. return retval;
  719. retval = target_read_u32(target, FLASH_PECR, &reg32);
  720. if (retval != ERROR_OK)
  721. return retval;
  722. reg32 |= FLASH_PECR__FPRG;
  723. retval = target_write_u32(target, FLASH_PECR, reg32);
  724. if (retval != ERROR_OK)
  725. return retval;
  726. retval = target_read_u32(target, FLASH_PECR, &reg32);
  727. if (retval != ERROR_OK)
  728. return retval;
  729. reg32 |= FLASH_PECR__PROG;
  730. retval = target_write_u32(target, FLASH_PECR, reg32);
  731. return retval;
  732. }
  733. static int stm32lx_lock_program_memory(struct flash_bank *bank)
  734. {
  735. struct target *target = bank->target;
  736. int retval;
  737. uint32_t reg32;
  738. /* To lock the program memory, simply set the lock bit and lock PECR */
  739. retval = target_read_u32(target, FLASH_PECR, &reg32);
  740. if (retval != ERROR_OK)
  741. return retval;
  742. reg32 |= FLASH_PECR__PRGLOCK;
  743. retval = target_write_u32(target, FLASH_PECR, reg32);
  744. if (retval != ERROR_OK)
  745. return retval;
  746. retval = target_read_u32(target, FLASH_PECR, &reg32);
  747. if (retval != ERROR_OK)
  748. return retval;
  749. reg32 |= FLASH_PECR__PELOCK;
  750. retval = target_write_u32(target, FLASH_PECR, reg32);
  751. if (retval != ERROR_OK)
  752. return retval;
  753. return ERROR_OK;
  754. }
  755. static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
  756. {
  757. struct target *target = bank->target;
  758. int retval;
  759. uint32_t reg32;
  760. /*
  761. * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
  762. * first unlock the memory, loop over the pages of this sector
  763. * and write 0x0 to its first word.
  764. */
  765. retval = stm32lx_unlock_program_memory(bank);
  766. if (retval != ERROR_OK)
  767. return retval;
  768. for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
  769. reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
  770. retval = target_write_u32(target, FLASH_PECR, reg32);
  771. if (retval != ERROR_OK)
  772. return retval;
  773. retval = stm32lx_wait_until_bsy_clear(bank);
  774. if (retval != ERROR_OK)
  775. return retval;
  776. uint32_t addr = bank->base + bank->sectors[sector].offset + (page
  777. * FLASH_PAGE_SIZE);
  778. retval = target_write_u32(target, addr, 0x0);
  779. if (retval != ERROR_OK)
  780. return retval;
  781. retval = stm32lx_wait_until_bsy_clear(bank);
  782. if (retval != ERROR_OK)
  783. return retval;
  784. }
  785. retval = stm32lx_lock_program_memory(bank);
  786. if (retval != ERROR_OK)
  787. return retval;
  788. return ERROR_OK;
  789. }
  790. static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
  791. {
  792. struct target *target = bank->target;
  793. uint32_t status;
  794. int retval = ERROR_OK;
  795. int timeout = 100;
  796. /* wait for busy to clear */
  797. for (;;) {
  798. retval = target_read_u32(target, FLASH_SR, &status);
  799. if (retval != ERROR_OK)
  800. return retval;
  801. if ((status & FLASH_SR__BSY) == 0)
  802. break;
  803. if (timeout-- <= 0) {
  804. LOG_ERROR("timed out waiting for flash");
  805. return ERROR_FAIL;
  806. }
  807. alive_sleep(1);
  808. }
  809. if (status & FLASH_SR__WRPERR) {
  810. LOG_ERROR("access denied / write protected");
  811. retval = ERROR_FAIL;
  812. }
  813. if (status & FLASH_SR__PGAERR) {
  814. LOG_ERROR("invalid program address");
  815. retval = ERROR_FAIL;
  816. }
  817. return retval;
  818. }