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  1. /***************************************************************************
  2. * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  18. ***************************************************************************/
  19. /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
  20. * specifically designed for SPI memories.
  21. * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  22. * Two working modes are available:
  23. * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  24. * on the bus.
  25. * - HW mode: the SPI but is under SMI control. Memory content is directly
  26. * accessible in CPU memory space. CPU can read, write and execute memory
  27. * content. */
  28. /* ATTENTION:
  29. * To have flash memory mapped in CPU memory space, the SMI controller
  30. * have to be in "HW mode". This requires following constraints:
  31. * 1) The command "reset init" have to initialize SMI controller and put
  32. * it in HW mode;
  33. * 2) every command in this file have to return to prompt in HW mode. */
  34. #ifdef HAVE_CONFIG_H
  35. #include "config.h"
  36. #endif
  37. #include "imp.h"
  38. #include "spi.h"
  39. #include <jtag/jtag.h>
  40. #include <helper/time_support.h>
  41. #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  42. #define _SMI_READ_REG(a) \
  43. { \
  44. int __a; \
  45. uint32_t __v; \
  46. \
  47. __a = target_read_u32(target, io_base + (a), &__v); \
  48. if (__a != ERROR_OK) \
  49. return __a; \
  50. __v; \
  51. }
  52. #define SMI_WRITE_REG(a, v) \
  53. { \
  54. int __r; \
  55. \
  56. __r = target_write_u32(target, io_base + (a), (v)); \
  57. if (__r != ERROR_OK) \
  58. return __r; \
  59. }
  60. #define SMI_POLL_TFF(timeout) \
  61. { \
  62. int __r; \
  63. \
  64. __r = poll_tff(target, io_base, timeout); \
  65. if (__r != ERROR_OK) \
  66. return __r; \
  67. }
  68. #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
  69. SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  70. #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  71. (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  72. #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
  73. SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  74. #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  75. #define SMI_BANK_SIZE (0x01000000)
  76. #define SMI_CR1 (0x00) /* Control register 1 */
  77. #define SMI_CR2 (0x04) /* Control register 2 */
  78. #define SMI_SR (0x08) /* Status register */
  79. #define SMI_TR (0x0c) /* TX */
  80. #define SMI_RR (0x10) /* RX */
  81. /* fields in SMI_CR1 */
  82. #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
  83. #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
  84. /* fields in SMI_CR2 */
  85. #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
  86. #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
  87. #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
  88. #define SMI_SEND 0x00000080 /* Send data */
  89. #define SMI_RSR 0x00000400 /* reads status reg */
  90. #define SMI_WE 0x00000800 /* Write Enable */
  91. #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
  92. #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
  93. #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
  94. #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
  95. /* fields in SMI_SR */
  96. #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
  97. /* Commands */
  98. #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
  99. /* Timeout in ms */
  100. #define SMI_CMD_TIMEOUT (100)
  101. #define SMI_PROBE_TIMEOUT (100)
  102. #define SMI_MAX_TIMEOUT (3000)
  103. struct stmsmi_flash_bank {
  104. int probed;
  105. uint32_t io_base;
  106. uint32_t bank_num;
  107. struct flash_device *dev;
  108. };
  109. struct stmsmi_target {
  110. char *name;
  111. uint32_t tap_idcode;
  112. uint32_t smi_base;
  113. uint32_t io_base;
  114. };
  115. static struct stmsmi_target target_devices[] = {
  116. /* name, tap_idcode, smi_base, io_base */
  117. { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
  118. { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
  119. { NULL, 0, 0, 0 }
  120. };
  121. FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
  122. {
  123. struct stmsmi_flash_bank *stmsmi_info;
  124. LOG_DEBUG("%s", __func__);
  125. if (CMD_ARGC < 6)
  126. return ERROR_COMMAND_SYNTAX_ERROR;
  127. stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
  128. if (stmsmi_info == NULL) {
  129. LOG_ERROR("not enough memory");
  130. return ERROR_FAIL;
  131. }
  132. bank->driver_priv = stmsmi_info;
  133. stmsmi_info->probed = 0;
  134. return ERROR_OK;
  135. }
  136. /* Poll transmit finished flag */
  137. /* timeout in ms */
  138. static int poll_tff(struct target *target, uint32_t io_base, int timeout)
  139. {
  140. long long endtime;
  141. if (SMI_READ_REG(SMI_SR) & SMI_TFF)
  142. return ERROR_OK;
  143. endtime = timeval_ms() + timeout;
  144. do {
  145. alive_sleep(1);
  146. if (SMI_READ_REG(SMI_SR) & SMI_TFF)
  147. return ERROR_OK;
  148. } while (timeval_ms() < endtime);
  149. LOG_ERROR("Timeout while polling TFF");
  150. return ERROR_FLASH_OPERATION_FAILED;
  151. }
  152. /* Read the status register of the external SPI flash chip.
  153. * The operation is triggered by setting SMI_RSR bit.
  154. * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
  155. static int read_status_reg(struct flash_bank *bank, uint32_t *status)
  156. {
  157. struct target *target = bank->target;
  158. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  159. uint32_t io_base = stmsmi_info->io_base;
  160. /* clear transmit finished flag */
  161. SMI_CLEAR_TFF();
  162. /* Read status */
  163. SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
  164. /* Poll transmit finished flag */
  165. SMI_POLL_TFF(SMI_CMD_TIMEOUT);
  166. /* clear transmit finished flag */
  167. SMI_CLEAR_TFF();
  168. *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
  169. /* clean-up SMI_CR2 */
  170. SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
  171. return ERROR_OK;
  172. }
  173. /* check for WIP (write in progress) bit in status register */
  174. /* timeout in ms */
  175. static int wait_till_ready(struct flash_bank *bank, int timeout)
  176. {
  177. uint32_t status;
  178. int retval;
  179. long long endtime;
  180. endtime = timeval_ms() + timeout;
  181. do {
  182. /* read flash status register */
  183. retval = read_status_reg(bank, &status);
  184. if (retval != ERROR_OK)
  185. return retval;
  186. if ((status & SPIFLASH_BSY_BIT) == 0)
  187. return ERROR_OK;
  188. alive_sleep(1);
  189. } while (timeval_ms() < endtime);
  190. LOG_ERROR("timeout");
  191. return ERROR_FAIL;
  192. }
  193. /* Send "write enable" command to SPI flash chip.
  194. * The operation is triggered by setting SMI_WE bit, and SMI sends
  195. * the proper SPI command (0x06) */
  196. static int smi_write_enable(struct flash_bank *bank)
  197. {
  198. struct target *target = bank->target;
  199. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  200. uint32_t io_base = stmsmi_info->io_base;
  201. uint32_t status;
  202. int retval;
  203. /* Enter in HW mode */
  204. SMI_SET_HW_MODE(); /* AB: is this correct ?*/
  205. /* clear transmit finished flag */
  206. SMI_CLEAR_TFF();
  207. /* Send write enable command */
  208. SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
  209. /* Poll transmit finished flag */
  210. SMI_POLL_TFF(SMI_CMD_TIMEOUT);
  211. /* read flash status register */
  212. retval = read_status_reg(bank, &status);
  213. if (retval != ERROR_OK)
  214. return retval;
  215. /* Check write enabled */
  216. if ((status & SPIFLASH_WE_BIT) == 0) {
  217. LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
  218. return ERROR_FAIL;
  219. }
  220. return ERROR_OK;
  221. }
  222. static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
  223. uint32_t offset)
  224. {
  225. union {
  226. uint32_t command;
  227. uint8_t x[4];
  228. } cmd;
  229. cmd.x[0] = stmsmi_info->dev->erase_cmd;
  230. cmd.x[1] = offset >> 16;
  231. cmd.x[2] = offset >> 8;
  232. cmd.x[3] = offset;
  233. return cmd.command;
  234. }
  235. static int smi_erase_sector(struct flash_bank *bank, int sector)
  236. {
  237. struct target *target = bank->target;
  238. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  239. uint32_t io_base = stmsmi_info->io_base;
  240. uint32_t cmd;
  241. int retval;
  242. retval = smi_write_enable(bank);
  243. if (retval != ERROR_OK)
  244. return retval;
  245. /* Switch to SW mode to send sector erase command */
  246. SMI_SET_SW_MODE();
  247. /* clear transmit finished flag */
  248. SMI_CLEAR_TFF();
  249. /* send SPI command "block erase" */
  250. cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
  251. SMI_WRITE_REG(SMI_TR, cmd);
  252. SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
  253. /* Poll transmit finished flag */
  254. SMI_POLL_TFF(SMI_CMD_TIMEOUT);
  255. /* poll WIP for end of self timed Sector Erase cycle */
  256. retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
  257. if (retval != ERROR_OK)
  258. return retval;
  259. return ERROR_OK;
  260. }
  261. static int stmsmi_erase(struct flash_bank *bank, int first, int last)
  262. {
  263. struct target *target = bank->target;
  264. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  265. uint32_t io_base = stmsmi_info->io_base;
  266. int retval = ERROR_OK;
  267. int sector;
  268. LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
  269. if (target->state != TARGET_HALTED) {
  270. LOG_ERROR("Target not halted");
  271. return ERROR_TARGET_NOT_HALTED;
  272. }
  273. if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
  274. LOG_ERROR("Flash sector invalid");
  275. return ERROR_FLASH_SECTOR_INVALID;
  276. }
  277. if (!(stmsmi_info->probed)) {
  278. LOG_ERROR("Flash bank not probed");
  279. return ERROR_FLASH_BANK_NOT_PROBED;
  280. }
  281. for (sector = first; sector <= last; sector++) {
  282. if (bank->sectors[sector].is_protected) {
  283. LOG_ERROR("Flash sector %d protected", sector);
  284. return ERROR_FAIL;
  285. }
  286. }
  287. for (sector = first; sector <= last; sector++) {
  288. retval = smi_erase_sector(bank, sector);
  289. if (retval != ERROR_OK)
  290. break;
  291. keep_alive();
  292. }
  293. /* Switch to HW mode before return to prompt */
  294. SMI_SET_HW_MODE();
  295. return retval;
  296. }
  297. static int stmsmi_protect(struct flash_bank *bank, int set,
  298. int first, int last)
  299. {
  300. int sector;
  301. for (sector = first; sector <= last; sector++)
  302. bank->sectors[sector].is_protected = set;
  303. return ERROR_OK;
  304. }
  305. static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
  306. uint32_t address, uint32_t len)
  307. {
  308. struct target *target = bank->target;
  309. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  310. uint32_t io_base = stmsmi_info->io_base;
  311. int retval;
  312. LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
  313. __func__, address, len);
  314. retval = smi_write_enable(bank);
  315. if (retval != ERROR_OK)
  316. return retval;
  317. /* HW mode, write burst mode */
  318. SMI_SET_HWWB_MODE();
  319. retval = target_write_buffer(target, address, len, buffer);
  320. if (retval != ERROR_OK)
  321. return retval;
  322. return ERROR_OK;
  323. }
  324. static int stmsmi_write(struct flash_bank *bank, uint8_t *buffer,
  325. uint32_t offset, uint32_t count)
  326. {
  327. struct target *target = bank->target;
  328. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  329. uint32_t io_base = stmsmi_info->io_base;
  330. uint32_t cur_count, page_size, page_offset;
  331. int sector;
  332. int retval = ERROR_OK;
  333. LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
  334. __func__, offset, count);
  335. if (target->state != TARGET_HALTED) {
  336. LOG_ERROR("Target not halted");
  337. return ERROR_TARGET_NOT_HALTED;
  338. }
  339. if (offset + count > stmsmi_info->dev->size_in_bytes) {
  340. LOG_WARNING("Write pasts end of flash. Extra data discarded.");
  341. count = stmsmi_info->dev->size_in_bytes - offset;
  342. }
  343. /* Check sector protection */
  344. for (sector = 0; sector < bank->num_sectors; sector++) {
  345. /* Start offset in or before this sector? */
  346. /* End offset in or behind this sector? */
  347. if ((offset <
  348. (bank->sectors[sector].offset + bank->sectors[sector].size))
  349. && ((offset + count - 1) >= bank->sectors[sector].offset)
  350. && bank->sectors[sector].is_protected) {
  351. LOG_ERROR("Flash sector %d protected", sector);
  352. return ERROR_FAIL;
  353. }
  354. }
  355. page_size = stmsmi_info->dev->pagesize;
  356. /* unaligned buffer head */
  357. if (count > 0 && (offset & 3) != 0) {
  358. cur_count = 4 - (offset & 3);
  359. if (cur_count > count)
  360. cur_count = count;
  361. retval = smi_write_buffer(bank, buffer, bank->base + offset,
  362. cur_count);
  363. if (retval != ERROR_OK)
  364. goto err;
  365. offset += cur_count;
  366. buffer += cur_count;
  367. count -= cur_count;
  368. }
  369. page_offset = offset % page_size;
  370. /* central part, aligned words */
  371. while (count >= 4) {
  372. /* clip block at page boundary */
  373. if (page_offset + count > page_size)
  374. cur_count = page_size - page_offset;
  375. else
  376. cur_count = count & ~3;
  377. retval = smi_write_buffer(bank, buffer, bank->base + offset,
  378. cur_count);
  379. if (retval != ERROR_OK)
  380. goto err;
  381. page_offset = 0;
  382. buffer += cur_count;
  383. offset += cur_count;
  384. count -= cur_count;
  385. keep_alive();
  386. }
  387. /* buffer tail */
  388. if (count > 0)
  389. retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
  390. err:
  391. /* Switch to HW mode before return to prompt */
  392. SMI_SET_HW_MODE();
  393. return retval;
  394. }
  395. /* Return ID of flash device */
  396. /* On exit, SW mode is kept */
  397. static int read_flash_id(struct flash_bank *bank, uint32_t *id)
  398. {
  399. struct target *target = bank->target;
  400. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  401. uint32_t io_base = stmsmi_info->io_base;
  402. int retval;
  403. if (target->state != TARGET_HALTED) {
  404. LOG_ERROR("Target not halted");
  405. return ERROR_TARGET_NOT_HALTED;
  406. }
  407. /* poll WIP */
  408. retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
  409. if (retval != ERROR_OK)
  410. return retval;
  411. /* enter in SW mode */
  412. SMI_SET_SW_MODE();
  413. /* clear transmit finished flag */
  414. SMI_CLEAR_TFF();
  415. /* Send SPI command "read ID" */
  416. SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
  417. SMI_WRITE_REG(SMI_CR2,
  418. stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
  419. /* Poll transmit finished flag */
  420. SMI_POLL_TFF(SMI_CMD_TIMEOUT);
  421. /* clear transmit finished flag */
  422. SMI_CLEAR_TFF();
  423. /* read ID from Receive Register */
  424. *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
  425. return ERROR_OK;
  426. }
  427. static int stmsmi_probe(struct flash_bank *bank)
  428. {
  429. struct target *target = bank->target;
  430. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  431. uint32_t io_base;
  432. struct flash_sector *sectors;
  433. uint32_t id = 0; /* silence uninitialized warning */
  434. struct stmsmi_target *target_device;
  435. int retval;
  436. if (stmsmi_info->probed)
  437. free(bank->sectors);
  438. stmsmi_info->probed = 0;
  439. for (target_device = target_devices ; target_device->name ; ++target_device)
  440. if (target_device->tap_idcode == target->tap->idcode)
  441. break;
  442. if (!target_device->name) {
  443. LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
  444. target->tap->idcode);
  445. return ERROR_FAIL;
  446. }
  447. switch (bank->base - target_device->smi_base) {
  448. case 0:
  449. stmsmi_info->bank_num = SMI_SEL_BANK0;
  450. break;
  451. case SMI_BANK_SIZE:
  452. stmsmi_info->bank_num = SMI_SEL_BANK1;
  453. break;
  454. case 2*SMI_BANK_SIZE:
  455. stmsmi_info->bank_num = SMI_SEL_BANK2;
  456. break;
  457. case 3*SMI_BANK_SIZE:
  458. stmsmi_info->bank_num = SMI_SEL_BANK3;
  459. break;
  460. default:
  461. LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
  462. return ERROR_FAIL;
  463. }
  464. io_base = target_device->io_base;
  465. stmsmi_info->io_base = io_base;
  466. LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
  467. target_device->name, bank->base);
  468. /* read and decode flash ID; returns in SW mode */
  469. retval = read_flash_id(bank, &id);
  470. SMI_SET_HW_MODE();
  471. if (retval != ERROR_OK)
  472. return retval;
  473. stmsmi_info->dev = NULL;
  474. for (struct flash_device *p = flash_devices; p->name ; p++)
  475. if (p->device_id == id) {
  476. stmsmi_info->dev = p;
  477. break;
  478. }
  479. if (!stmsmi_info->dev) {
  480. LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
  481. return ERROR_FAIL;
  482. }
  483. LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
  484. stmsmi_info->dev->name, stmsmi_info->dev->device_id);
  485. /* Set correct size value */
  486. bank->size = stmsmi_info->dev->size_in_bytes;
  487. /* create and fill sectors array */
  488. bank->num_sectors =
  489. stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
  490. sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
  491. if (sectors == NULL) {
  492. LOG_ERROR("not enough memory");
  493. return ERROR_FAIL;
  494. }
  495. for (int sector = 0; sector < bank->num_sectors; sector++) {
  496. sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
  497. sectors[sector].size = stmsmi_info->dev->sectorsize;
  498. sectors[sector].is_erased = -1;
  499. sectors[sector].is_protected = 1;
  500. }
  501. bank->sectors = sectors;
  502. stmsmi_info->probed = 1;
  503. return ERROR_OK;
  504. }
  505. static int stmsmi_auto_probe(struct flash_bank *bank)
  506. {
  507. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  508. if (stmsmi_info->probed)
  509. return ERROR_OK;
  510. return stmsmi_probe(bank);
  511. }
  512. static int stmsmi_protect_check(struct flash_bank *bank)
  513. {
  514. /* Nothing to do. Protection is only handled in SW. */
  515. return ERROR_OK;
  516. }
  517. static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
  518. {
  519. struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
  520. if (!(stmsmi_info->probed)) {
  521. snprintf(buf, buf_size,
  522. "\nSMI flash bank not probed yet\n");
  523. return ERROR_OK;
  524. }
  525. snprintf(buf, buf_size, "\nSMI flash information:\n"
  526. " Device \'%s\' (ID 0x%08x)\n",
  527. stmsmi_info->dev->name, stmsmi_info->dev->device_id);
  528. return ERROR_OK;
  529. }
  530. struct flash_driver stmsmi_flash = {
  531. .name = "stmsmi",
  532. .flash_bank_command = stmsmi_flash_bank_command,
  533. .erase = stmsmi_erase,
  534. .protect = stmsmi_protect,
  535. .write = stmsmi_write,
  536. .read = default_flash_read,
  537. .probe = stmsmi_probe,
  538. .auto_probe = stmsmi_auto_probe,
  539. .erase_check = default_flash_blank_check,
  540. .protect_check = stmsmi_protect_check,
  541. .info = get_stmsmi_info,
  542. };