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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Andreas Fritiofson *
  9. * andreas.fritiofson@gmail.com *
  10. * *
  11. * Copyright (C) 2013 by Roman Dmitrienko *
  12. * me@iamroman.org *
  13. * *
  14. * Copyright (C) 2014 Nemui Trinomius *
  15. * nemuisan_kawausogasuki@live.jp *
  16. * *
  17. * This program is free software; you can redistribute it and/or modify *
  18. * it under the terms of the GNU General Public License as published by *
  19. * the Free Software Foundation; either version 2 of the License, or *
  20. * (at your option) any later version. *
  21. * *
  22. * This program is distributed in the hope that it will be useful, *
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  25. * GNU General Public License for more details. *
  26. * *
  27. * You should have received a copy of the GNU General Public License *
  28. * along with this program. If not, see <http://www.gnu.org/licenses/>. *
  29. ***************************************************************************/
  30. #ifdef HAVE_CONFIG_H
  31. #include "config.h"
  32. #endif
  33. #include "imp.h"
  34. #include <helper/binarybuffer.h>
  35. #include <target/algorithm.h>
  36. #include <target/armv7m.h>
  37. #include <target/cortex_m.h>
  38. #define EFM_FAMILY_ID_GIANT_GECKO 72
  39. #define EFM_FAMILY_ID_LEOPARD_GECKO 74
  40. #define EFM32_FLASH_ERASE_TMO 100
  41. #define EFM32_FLASH_WDATAREADY_TMO 100
  42. #define EFM32_FLASH_WRITE_TMO 100
  43. /* size in bytes, not words; must fit all Gecko devices */
  44. #define LOCKBITS_PAGE_SZ 512
  45. #define EFM32_MSC_INFO_BASE 0x0fe00000
  46. #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
  47. #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
  48. #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
  49. /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
  50. #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
  51. #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
  52. #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
  53. #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
  54. #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
  55. #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
  56. #define EFM32_MSC_REGBASE 0x400c0000
  57. #define EFM32_MSC_REGBASE_SERIES1 0x400e0000
  58. #define EFM32_MSC_REG_WRITECTRL 0x008
  59. #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
  60. #define EFM32_MSC_REG_WRITECMD 0x00c
  61. #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  62. #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  63. #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  64. #define EFM32_MSC_REG_ADDRB 0x010
  65. #define EFM32_MSC_REG_WDATA 0x018
  66. #define EFM32_MSC_REG_STATUS 0x01c
  67. #define EFM32_MSC_STATUS_BUSY_MASK 0x1
  68. #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
  69. #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
  70. #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  71. #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  72. #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  73. #define EFM32_MSC_REG_LOCK 0x03c
  74. #define EFM32_MSC_REG_LOCK_SERIES1 0x040
  75. #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
  76. struct efm32_family_data {
  77. int family_id;
  78. const char *name;
  79. /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
  80. is the "new" series 1). Determines location of MSC registers. */
  81. int series;
  82. /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
  83. int page_size;
  84. /* MSC register base address, or 0 to use default */
  85. uint32_t msc_regbase;
  86. };
  87. struct efm32x_flash_bank {
  88. bool probed;
  89. uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
  90. uint32_t reg_base;
  91. uint32_t reg_lock;
  92. };
  93. struct efm32_info {
  94. const struct efm32_family_data *family_data;
  95. uint16_t flash_sz_kib;
  96. uint16_t ram_sz_kib;
  97. uint16_t part_num;
  98. uint8_t part_family;
  99. uint8_t prod_rev;
  100. uint16_t page_size;
  101. };
  102. static const struct efm32_family_data efm32_families[] = {
  103. { 16, "EFR32MG1P Mighty", .series = 1 },
  104. { 17, "EFR32MG1B Mighty", .series = 1 },
  105. { 18, "EFR32MG1V Mighty", .series = 1 },
  106. { 19, "EFR32MG1P Blue", .series = 1 },
  107. { 20, "EFR32MG1B Blue", .series = 1 },
  108. { 21, "EFR32MG1V Blue", .series = 1 },
  109. { 25, "EFR32FG1P Flex", .series = 1 },
  110. { 26, "EFR32FG1B Flex", .series = 1 },
  111. { 27, "EFR32FG1V Flex", .series = 1 },
  112. { 28, "EFR32MG2P Mighty", .series = 1 },
  113. { 29, "EFR32MG2B Mighty", .series = 1 },
  114. { 30, "EFR32MG2V Mighty", .series = 1 },
  115. { 31, "EFR32BG12P Blue", .series = 1 },
  116. { 32, "EFR32BG12B Blue", .series = 1 },
  117. { 33, "EFR32BG12V Blue", .series = 1 },
  118. { 37, "EFR32FG12P Flex", .series = 1 },
  119. { 38, "EFR32FG12B Flex", .series = 1 },
  120. { 39, "EFR32FG12V Flex", .series = 1 },
  121. { 40, "EFR32MG13P Mighty", .series = 1 },
  122. { 41, "EFR32MG13B Mighty", .series = 1 },
  123. { 42, "EFR32MG13V Mighty", .series = 1 },
  124. { 43, "EFR32BG13P Blue", .series = 1 },
  125. { 44, "EFR32BG13B Blue", .series = 1 },
  126. { 45, "EFR32BG13V Blue", .series = 1 },
  127. { 46, "EFR32ZG13P Zen", .series = 1 },
  128. { 49, "EFR32FG13P Flex", .series = 1 },
  129. { 50, "EFR32FG13B Flex", .series = 1 },
  130. { 51, "EFR32FG13V Flex", .series = 1 },
  131. { 52, "EFR32MG14P Mighty", .series = 1 },
  132. { 53, "EFR32MG14B Mighty", .series = 1 },
  133. { 54, "EFR32MG14V Mighty", .series = 1 },
  134. { 55, "EFR32BG14P Blue", .series = 1 },
  135. { 56, "EFR32BG14B Blue", .series = 1 },
  136. { 57, "EFR32BG14V Blue", .series = 1 },
  137. { 58, "EFR32ZG14P Zen", .series = 1 },
  138. { 61, "EFR32FG14P Flex", .series = 1 },
  139. { 62, "EFR32FG14B Flex", .series = 1 },
  140. { 63, "EFR32FG14V Flex", .series = 1 },
  141. { 71, "EFM32G", .series = 0, .page_size = 512 },
  142. { 72, "EFM32GG Giant", .series = 0 },
  143. { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
  144. { 74, "EFM32LG Leopard", .series = 0 },
  145. { 75, "EFM32WG Wonder", .series = 0 },
  146. { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
  147. { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
  148. { 81, "EFM32PG1B Pearl", .series = 1 },
  149. { 83, "EFM32JG1B Jade", .series = 1 },
  150. { 85, "EFM32PG12B Pearl", .series = 1 },
  151. { 87, "EFM32JG12B Jade", .series = 1 },
  152. { 89, "EFM32PG13B Pearl", .series = 1 },
  153. { 91, "EFM32JG13B Jade", .series = 1 },
  154. { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
  155. { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
  156. { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
  157. { 120, "EZR32WG Wonder", .series = 0 },
  158. { 121, "EZR32LG Leopard", .series = 0 },
  159. { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
  160. };
  161. static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
  162. uint32_t offset, uint32_t count);
  163. static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
  164. {
  165. return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
  166. }
  167. static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
  168. {
  169. return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
  170. }
  171. static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
  172. {
  173. return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
  174. }
  175. static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
  176. {
  177. return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
  178. }
  179. static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
  180. {
  181. return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
  182. }
  183. static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
  184. uint32_t *value)
  185. {
  186. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  187. uint32_t base = efm32x_info->reg_base;
  188. return target_read_u32(bank->target, base + offset, value);
  189. }
  190. static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
  191. uint32_t value)
  192. {
  193. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  194. uint32_t base = efm32x_info->reg_base;
  195. return target_write_u32(bank->target, base + offset, value);
  196. }
  197. static int efm32x_read_info(struct flash_bank *bank,
  198. struct efm32_info *efm32_info)
  199. {
  200. int ret;
  201. uint32_t cpuid = 0;
  202. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  203. memset(efm32_info, 0, sizeof(struct efm32_info));
  204. ret = target_read_u32(bank->target, CPUID, &cpuid);
  205. if (ret != ERROR_OK)
  206. return ret;
  207. if (((cpuid >> 4) & 0xfff) == 0xc23) {
  208. /* Cortex-M3 device */
  209. } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
  210. /* Cortex-M4 device (WONDER GECKO) */
  211. } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
  212. /* Cortex-M0+ device */
  213. } else {
  214. LOG_ERROR("Target is not Cortex-Mx Device");
  215. return ERROR_FAIL;
  216. }
  217. ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
  218. if (ret != ERROR_OK)
  219. return ret;
  220. ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
  221. if (ret != ERROR_OK)
  222. return ret;
  223. ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
  224. if (ret != ERROR_OK)
  225. return ret;
  226. ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
  227. if (ret != ERROR_OK)
  228. return ret;
  229. ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
  230. if (ret != ERROR_OK)
  231. return ret;
  232. for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
  233. if (efm32_families[i].family_id == efm32_info->part_family)
  234. efm32_info->family_data = &efm32_families[i];
  235. }
  236. if (!efm32_info->family_data) {
  237. LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
  238. return ERROR_FAIL;
  239. }
  240. switch (efm32_info->family_data->series) {
  241. case 0:
  242. efm32x_info->reg_base = EFM32_MSC_REGBASE;
  243. efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
  244. break;
  245. case 1:
  246. efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
  247. efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
  248. break;
  249. }
  250. if (efm32_info->family_data->msc_regbase != 0)
  251. efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
  252. if (efm32_info->family_data->page_size != 0) {
  253. efm32_info->page_size = efm32_info->family_data->page_size;
  254. } else {
  255. uint8_t pg_size = 0;
  256. ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
  257. &pg_size);
  258. if (ret != ERROR_OK)
  259. return ret;
  260. efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
  261. if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
  262. efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
  263. /* Giant or Leopard Gecko */
  264. if (efm32_info->prod_rev < 18) {
  265. /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
  266. for MCUs with PROD_REV < 18 */
  267. if (efm32_info->flash_sz_kib < 512)
  268. efm32_info->page_size = 2048;
  269. else
  270. efm32_info->page_size = 4096;
  271. }
  272. }
  273. if ((efm32_info->page_size != 2048) &&
  274. (efm32_info->page_size != 4096)) {
  275. LOG_ERROR("Invalid page size %u", efm32_info->page_size);
  276. return ERROR_FAIL;
  277. }
  278. }
  279. return ERROR_OK;
  280. }
  281. /* flash bank efm32 <base> <size> 0 0 <target#> */
  282. FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
  283. {
  284. struct efm32x_flash_bank *efm32x_info;
  285. if (CMD_ARGC < 6)
  286. return ERROR_COMMAND_SYNTAX_ERROR;
  287. efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
  288. bank->driver_priv = efm32x_info;
  289. efm32x_info->probed = false;
  290. memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
  291. return ERROR_OK;
  292. }
  293. /* set or reset given bits in a register */
  294. static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
  295. uint32_t bitmask, int set)
  296. {
  297. int ret = 0;
  298. uint32_t reg_val = 0;
  299. ret = efm32x_read_reg_u32(bank, reg, &reg_val);
  300. if (ret != ERROR_OK)
  301. return ret;
  302. if (set)
  303. reg_val |= bitmask;
  304. else
  305. reg_val &= ~bitmask;
  306. return efm32x_write_reg_u32(bank, reg, reg_val);
  307. }
  308. static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
  309. {
  310. return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
  311. EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
  312. }
  313. static int efm32x_msc_lock(struct flash_bank *bank, int lock)
  314. {
  315. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  316. return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
  317. (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
  318. }
  319. static int efm32x_wait_status(struct flash_bank *bank, int timeout,
  320. uint32_t wait_mask, int wait_for_set)
  321. {
  322. int ret = 0;
  323. uint32_t status = 0;
  324. while (1) {
  325. ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
  326. if (ret != ERROR_OK)
  327. break;
  328. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  329. if (((status & wait_mask) == 0) && (0 == wait_for_set))
  330. break;
  331. else if (((status & wait_mask) != 0) && wait_for_set)
  332. break;
  333. if (timeout-- <= 0) {
  334. LOG_ERROR("timed out waiting for MSC status");
  335. return ERROR_FAIL;
  336. }
  337. alive_sleep(1);
  338. }
  339. if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
  340. LOG_WARNING("page erase was aborted");
  341. return ret;
  342. }
  343. static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
  344. {
  345. /* this function DOES NOT set WREN; must be set already */
  346. /* 1. write address to ADDRB
  347. 2. write LADDRIM
  348. 3. check status (INVADDR, LOCKED)
  349. 4. write ERASEPAGE
  350. 5. wait until !STATUS_BUSY
  351. */
  352. int ret = 0;
  353. uint32_t status = 0;
  354. addr += bank->base;
  355. LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
  356. ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
  357. if (ret != ERROR_OK)
  358. return ret;
  359. ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
  360. EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
  361. if (ret != ERROR_OK)
  362. return ret;
  363. ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
  364. if (ret != ERROR_OK)
  365. return ret;
  366. LOG_DEBUG("status 0x%" PRIx32, status);
  367. if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
  368. LOG_ERROR("Page is locked");
  369. return ERROR_FAIL;
  370. } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
  371. LOG_ERROR("Invalid address 0x%" PRIx32, addr);
  372. return ERROR_FAIL;
  373. }
  374. ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
  375. EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
  376. if (ret != ERROR_OK)
  377. return ret;
  378. return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
  379. EFM32_MSC_STATUS_BUSY_MASK, 0);
  380. }
  381. static int efm32x_erase(struct flash_bank *bank, unsigned int first,
  382. unsigned int last)
  383. {
  384. struct target *target = bank->target;
  385. int ret = 0;
  386. if (TARGET_HALTED != target->state) {
  387. LOG_ERROR("Target not halted");
  388. return ERROR_TARGET_NOT_HALTED;
  389. }
  390. efm32x_msc_lock(bank, 0);
  391. ret = efm32x_set_wren(bank, 1);
  392. if (ret != ERROR_OK) {
  393. LOG_ERROR("Failed to enable MSC write");
  394. return ret;
  395. }
  396. for (unsigned int i = first; i <= last; i++) {
  397. ret = efm32x_erase_page(bank, bank->sectors[i].offset);
  398. if (ret != ERROR_OK)
  399. LOG_ERROR("Failed to erase page %d", i);
  400. }
  401. ret = efm32x_set_wren(bank, 0);
  402. efm32x_msc_lock(bank, 1);
  403. return ret;
  404. }
  405. static int efm32x_read_lock_data(struct flash_bank *bank)
  406. {
  407. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  408. struct target *target = bank->target;
  409. int data_size = 0;
  410. uint32_t *ptr = NULL;
  411. int ret = 0;
  412. assert(bank->num_sectors > 0);
  413. /* calculate the number of 32-bit words to read (one lock bit per sector) */
  414. data_size = (bank->num_sectors + 31) / 32;
  415. ptr = efm32x_info->lb_page;
  416. for (int i = 0; i < data_size; i++, ptr++) {
  417. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
  418. if (ret != ERROR_OK) {
  419. LOG_ERROR("Failed to read PLW %d", i);
  420. return ret;
  421. }
  422. }
  423. /* also, read ULW, DLW, MLW, ALW and CLW words */
  424. /* ULW, word 126 */
  425. ptr = efm32x_info->lb_page + 126;
  426. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
  427. if (ret != ERROR_OK) {
  428. LOG_ERROR("Failed to read ULW");
  429. return ret;
  430. }
  431. /* DLW, word 127 */
  432. ptr = efm32x_info->lb_page + 127;
  433. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
  434. if (ret != ERROR_OK) {
  435. LOG_ERROR("Failed to read DLW");
  436. return ret;
  437. }
  438. /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
  439. ptr = efm32x_info->lb_page + 125;
  440. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
  441. if (ret != ERROR_OK) {
  442. LOG_ERROR("Failed to read MLW");
  443. return ret;
  444. }
  445. /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
  446. ptr = efm32x_info->lb_page + 124;
  447. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
  448. if (ret != ERROR_OK) {
  449. LOG_ERROR("Failed to read ALW");
  450. return ret;
  451. }
  452. /* CLW1, word 123, present in EFR32 */
  453. ptr = efm32x_info->lb_page + 123;
  454. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
  455. if (ret != ERROR_OK) {
  456. LOG_ERROR("Failed to read CLW1");
  457. return ret;
  458. }
  459. /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
  460. ptr = efm32x_info->lb_page + 122;
  461. ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
  462. if (ret != ERROR_OK) {
  463. LOG_ERROR("Failed to read CLW0");
  464. return ret;
  465. }
  466. return ERROR_OK;
  467. }
  468. static int efm32x_write_lock_data(struct flash_bank *bank)
  469. {
  470. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  471. int ret = 0;
  472. ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
  473. if (ret != ERROR_OK) {
  474. LOG_ERROR("Failed to erase LB page");
  475. return ret;
  476. }
  477. return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
  478. LOCKBITS_PAGE_SZ);
  479. }
  480. static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
  481. {
  482. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  483. uint32_t dw = efm32x_info->lb_page[page >> 5];
  484. uint32_t mask = 0;
  485. mask = 1 << (page & 0x1f);
  486. return (dw & mask) ? 0 : 1;
  487. }
  488. static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
  489. {
  490. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  491. uint32_t *dw = &efm32x_info->lb_page[page >> 5];
  492. uint32_t mask = 0;
  493. mask = 1 << (page & 0x1f);
  494. if (!set)
  495. *dw |= mask;
  496. else
  497. *dw &= ~mask;
  498. return ERROR_OK;
  499. }
  500. static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
  501. unsigned int last)
  502. {
  503. struct target *target = bank->target;
  504. int ret = 0;
  505. if (!set) {
  506. LOG_ERROR("Erase device data to reset page locks");
  507. return ERROR_FAIL;
  508. }
  509. if (target->state != TARGET_HALTED) {
  510. LOG_ERROR("Target not halted");
  511. return ERROR_TARGET_NOT_HALTED;
  512. }
  513. for (unsigned int i = first; i <= last; i++) {
  514. ret = efm32x_set_page_lock(bank, i, set);
  515. if (ret != ERROR_OK) {
  516. LOG_ERROR("Failed to set lock on page %d", i);
  517. return ret;
  518. }
  519. }
  520. ret = efm32x_write_lock_data(bank);
  521. if (ret != ERROR_OK) {
  522. LOG_ERROR("Failed to write LB page");
  523. return ret;
  524. }
  525. return ERROR_OK;
  526. }
  527. static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
  528. uint32_t offset, uint32_t count)
  529. {
  530. struct target *target = bank->target;
  531. uint32_t buffer_size = 16384;
  532. struct working_area *write_algorithm;
  533. struct working_area *source;
  534. uint32_t address = bank->base + offset;
  535. struct reg_param reg_params[5];
  536. struct armv7m_algorithm armv7m_info;
  537. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  538. int ret = ERROR_OK;
  539. /* see contrib/loaders/flash/efm32.S for src */
  540. static const uint8_t efm32x_flash_write_code[] = {
  541. /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
  542. /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
  543. /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
  544. /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
  545. /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
  546. 0x01, 0x26, /* movs r6, #1 */
  547. 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
  548. /* wait_fifo: */
  549. 0x16, 0x68, /* ldr r6, [r2, #0] */
  550. 0x00, 0x2e, /* cmp r6, #0 */
  551. 0x22, 0xd0, /* beq exit */
  552. 0x55, 0x68, /* ldr r5, [r2, #4] */
  553. 0xb5, 0x42, /* cmp r5, r6 */
  554. 0xf9, 0xd0, /* beq wait_fifo */
  555. 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
  556. 0x01, 0x26, /* movs r6, #1 */
  557. 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
  558. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  559. 0x06, 0x27, /* movs r7, #6 */
  560. 0x3e, 0x42, /* tst r6, r7 */
  561. 0x16, 0xd1, /* bne error */
  562. /* wait_wdataready: */
  563. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  564. 0x08, 0x27, /* movs r7, #8 */
  565. 0x3e, 0x42, /* tst r6, r7 */
  566. 0xfb, 0xd0, /* beq wait_wdataready */
  567. 0x2e, 0x68, /* ldr r6, [r5] */
  568. 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
  569. 0x08, 0x26, /* movs r6, #8 */
  570. 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
  571. 0x04, 0x35, /* adds r5, #4 */
  572. 0x04, 0x34, /* adds r4, #4 */
  573. /* busy: */
  574. 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
  575. 0x01, 0x27, /* movs r7, #1 */
  576. 0x3e, 0x42, /* tst r6, r7 */
  577. 0xfb, 0xd1, /* bne busy */
  578. 0x9d, 0x42, /* cmp r5, r3 */
  579. 0x01, 0xd3, /* bcc no_wrap */
  580. 0x15, 0x46, /* mov r5, r2 */
  581. 0x08, 0x35, /* adds r5, #8 */
  582. /* no_wrap: */
  583. 0x55, 0x60, /* str r5, [r2, #4] */
  584. 0x01, 0x39, /* subs r1, r1, #1 */
  585. 0x00, 0x29, /* cmp r1, #0 */
  586. 0x02, 0xd0, /* beq exit */
  587. 0xdb, 0xe7, /* b wait_fifo */
  588. /* error: */
  589. 0x00, 0x20, /* movs r0, #0 */
  590. 0x50, 0x60, /* str r0, [r2, #4] */
  591. /* exit: */
  592. 0x30, 0x46, /* mov r0, r6 */
  593. 0x00, 0xbe, /* bkpt #0 */
  594. };
  595. /* flash write code */
  596. if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
  597. &write_algorithm) != ERROR_OK) {
  598. LOG_WARNING("no working area available, can't do block memory writes");
  599. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  600. }
  601. ret = target_write_buffer(target, write_algorithm->address,
  602. sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
  603. if (ret != ERROR_OK)
  604. return ret;
  605. /* memory buffer */
  606. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  607. buffer_size /= 2;
  608. buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
  609. if (buffer_size <= 256) {
  610. /* we already allocated the writing code, but failed to get a
  611. * buffer, free the algorithm */
  612. target_free_working_area(target, write_algorithm);
  613. LOG_WARNING("no large enough working area available, can't do block memory writes");
  614. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  615. }
  616. }
  617. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
  618. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
  619. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
  620. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
  621. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
  622. buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
  623. buf_set_u32(reg_params[1].value, 0, 32, count);
  624. buf_set_u32(reg_params[2].value, 0, 32, source->address);
  625. buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
  626. buf_set_u32(reg_params[4].value, 0, 32, address);
  627. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  628. armv7m_info.core_mode = ARM_MODE_THREAD;
  629. ret = target_run_flash_async_algorithm(target, buf, count, 4,
  630. 0, NULL,
  631. 5, reg_params,
  632. source->address, source->size,
  633. write_algorithm->address, 0,
  634. &armv7m_info);
  635. if (ret == ERROR_FLASH_OPERATION_FAILED) {
  636. LOG_ERROR("flash write failed at address 0x%"PRIx32,
  637. buf_get_u32(reg_params[4].value, 0, 32));
  638. if (buf_get_u32(reg_params[0].value, 0, 32) &
  639. EFM32_MSC_STATUS_LOCKED_MASK) {
  640. LOG_ERROR("flash memory write protected");
  641. }
  642. if (buf_get_u32(reg_params[0].value, 0, 32) &
  643. EFM32_MSC_STATUS_INVADDR_MASK) {
  644. LOG_ERROR("invalid flash memory write address");
  645. }
  646. }
  647. target_free_working_area(target, source);
  648. target_free_working_area(target, write_algorithm);
  649. destroy_reg_param(&reg_params[0]);
  650. destroy_reg_param(&reg_params[1]);
  651. destroy_reg_param(&reg_params[2]);
  652. destroy_reg_param(&reg_params[3]);
  653. destroy_reg_param(&reg_params[4]);
  654. return ret;
  655. }
  656. static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
  657. uint32_t val)
  658. {
  659. /* this function DOES NOT set WREN; must be set already */
  660. /* 1. write address to ADDRB
  661. 2. write LADDRIM
  662. 3. check status (INVADDR, LOCKED)
  663. 4. wait for WDATAREADY
  664. 5. write data to WDATA
  665. 6. write WRITECMD_WRITEONCE to WRITECMD
  666. 7. wait until !STATUS_BUSY
  667. */
  668. /* FIXME: EFM32G ref states (7.3.2) that writes should be
  669. * performed twice per dword */
  670. int ret = 0;
  671. uint32_t status = 0;
  672. /* if not called, GDB errors will be reported during large writes */
  673. keep_alive();
  674. ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
  675. if (ret != ERROR_OK)
  676. return ret;
  677. ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
  678. EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
  679. if (ret != ERROR_OK)
  680. return ret;
  681. ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
  682. if (ret != ERROR_OK)
  683. return ret;
  684. LOG_DEBUG("status 0x%" PRIx32, status);
  685. if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
  686. LOG_ERROR("Page is locked");
  687. return ERROR_FAIL;
  688. } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
  689. LOG_ERROR("Invalid address 0x%" PRIx32, addr);
  690. return ERROR_FAIL;
  691. }
  692. ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
  693. EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
  694. if (ret != ERROR_OK) {
  695. LOG_ERROR("Wait for WDATAREADY failed");
  696. return ret;
  697. }
  698. ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
  699. if (ret != ERROR_OK) {
  700. LOG_ERROR("WDATA write failed");
  701. return ret;
  702. }
  703. ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
  704. EFM32_MSC_WRITECMD_WRITEONCE_MASK);
  705. if (ret != ERROR_OK) {
  706. LOG_ERROR("WRITECMD write failed");
  707. return ret;
  708. }
  709. ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
  710. EFM32_MSC_STATUS_BUSY_MASK, 0);
  711. if (ret != ERROR_OK) {
  712. LOG_ERROR("Wait for BUSY failed");
  713. return ret;
  714. }
  715. return ERROR_OK;
  716. }
  717. static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
  718. uint32_t offset, uint32_t count)
  719. {
  720. struct target *target = bank->target;
  721. uint8_t *new_buffer = NULL;
  722. if (target->state != TARGET_HALTED) {
  723. LOG_ERROR("Target not halted");
  724. return ERROR_TARGET_NOT_HALTED;
  725. }
  726. if (offset & 0x3) {
  727. LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
  728. "alignment", offset);
  729. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  730. }
  731. if (count & 0x3) {
  732. uint32_t old_count = count;
  733. count = (old_count | 3) + 1;
  734. new_buffer = malloc(count);
  735. if (!new_buffer) {
  736. LOG_ERROR("odd number of bytes to write and no memory "
  737. "for padding buffer");
  738. return ERROR_FAIL;
  739. }
  740. LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
  741. "and padding with 0xff", old_count, count);
  742. memset(new_buffer, 0xff, count);
  743. buffer = memcpy(new_buffer, buffer, old_count);
  744. }
  745. uint32_t words_remaining = count / 4;
  746. int retval, retval2;
  747. /* unlock flash registers */
  748. efm32x_msc_lock(bank, 0);
  749. retval = efm32x_set_wren(bank, 1);
  750. if (retval != ERROR_OK)
  751. goto cleanup;
  752. /* try using a block write */
  753. retval = efm32x_write_block(bank, buffer, offset, words_remaining);
  754. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  755. /* if block write failed (no sufficient working area),
  756. * we use normal (slow) single word accesses */
  757. LOG_WARNING("couldn't use block writes, falling back to single "
  758. "memory accesses");
  759. while (words_remaining > 0) {
  760. uint32_t value;
  761. memcpy(&value, buffer, sizeof(uint32_t));
  762. retval = efm32x_write_word(bank, offset, value);
  763. if (retval != ERROR_OK)
  764. goto reset_pg_and_lock;
  765. words_remaining--;
  766. buffer += 4;
  767. offset += 4;
  768. }
  769. }
  770. reset_pg_and_lock:
  771. retval2 = efm32x_set_wren(bank, 0);
  772. efm32x_msc_lock(bank, 1);
  773. if (retval == ERROR_OK)
  774. retval = retval2;
  775. cleanup:
  776. free(new_buffer);
  777. return retval;
  778. }
  779. static int efm32x_probe(struct flash_bank *bank)
  780. {
  781. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  782. struct efm32_info efm32_mcu_info;
  783. int ret;
  784. uint32_t base_address = 0x00000000;
  785. efm32x_info->probed = false;
  786. memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
  787. ret = efm32x_read_info(bank, &efm32_mcu_info);
  788. if (ret != ERROR_OK)
  789. return ret;
  790. LOG_INFO("detected part: %s Gecko, rev %d",
  791. efm32_mcu_info.family_data->name, efm32_mcu_info.prod_rev);
  792. LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
  793. LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
  794. assert(0 != efm32_mcu_info.page_size);
  795. int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
  796. efm32_mcu_info.page_size;
  797. assert(num_pages > 0);
  798. free(bank->sectors);
  799. bank->sectors = NULL;
  800. bank->base = base_address;
  801. bank->size = (num_pages * efm32_mcu_info.page_size);
  802. bank->num_sectors = num_pages;
  803. ret = efm32x_read_lock_data(bank);
  804. if (ret != ERROR_OK) {
  805. LOG_ERROR("Failed to read LB data");
  806. return ret;
  807. }
  808. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  809. for (int i = 0; i < num_pages; i++) {
  810. bank->sectors[i].offset = i * efm32_mcu_info.page_size;
  811. bank->sectors[i].size = efm32_mcu_info.page_size;
  812. bank->sectors[i].is_erased = -1;
  813. bank->sectors[i].is_protected = 1;
  814. }
  815. efm32x_info->probed = true;
  816. return ERROR_OK;
  817. }
  818. static int efm32x_auto_probe(struct flash_bank *bank)
  819. {
  820. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  821. if (efm32x_info->probed)
  822. return ERROR_OK;
  823. return efm32x_probe(bank);
  824. }
  825. static int efm32x_protect_check(struct flash_bank *bank)
  826. {
  827. struct target *target = bank->target;
  828. int ret = 0;
  829. if (target->state != TARGET_HALTED) {
  830. LOG_ERROR("Target not halted");
  831. return ERROR_TARGET_NOT_HALTED;
  832. }
  833. ret = efm32x_read_lock_data(bank);
  834. if (ret != ERROR_OK) {
  835. LOG_ERROR("Failed to read LB data");
  836. return ret;
  837. }
  838. assert(bank->sectors);
  839. for (unsigned int i = 0; i < bank->num_sectors; i++)
  840. bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
  841. return ERROR_OK;
  842. }
  843. static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
  844. {
  845. struct efm32_info info;
  846. int ret;
  847. ret = efm32x_read_info(bank, &info);
  848. if (ret != ERROR_OK) {
  849. LOG_ERROR("Failed to read EFM32 info");
  850. return ret;
  851. }
  852. command_print_sameline(cmd, "%s Gecko, rev %d", info.family_data->name, info.prod_rev);
  853. return ERROR_OK;
  854. }
  855. COMMAND_HANDLER(efm32x_handle_debuglock_command)
  856. {
  857. struct target *target = NULL;
  858. if (CMD_ARGC < 1)
  859. return ERROR_COMMAND_SYNTAX_ERROR;
  860. struct flash_bank *bank;
  861. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  862. if (retval != ERROR_OK)
  863. return retval;
  864. struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
  865. target = bank->target;
  866. if (target->state != TARGET_HALTED) {
  867. LOG_ERROR("Target not halted");
  868. return ERROR_TARGET_NOT_HALTED;
  869. }
  870. uint32_t *ptr;
  871. ptr = efm32x_info->lb_page + 127;
  872. *ptr = 0;
  873. retval = efm32x_write_lock_data(bank);
  874. if (retval != ERROR_OK) {
  875. LOG_ERROR("Failed to write LB page");
  876. return retval;
  877. }
  878. command_print(CMD, "efm32x debug interface locked, reset the device to apply");
  879. return ERROR_OK;
  880. }
  881. static const struct command_registration efm32x_exec_command_handlers[] = {
  882. {
  883. .name = "debuglock",
  884. .handler = efm32x_handle_debuglock_command,
  885. .mode = COMMAND_EXEC,
  886. .usage = "bank_id",
  887. .help = "Lock the debug interface of the device.",
  888. },
  889. COMMAND_REGISTRATION_DONE
  890. };
  891. static const struct command_registration efm32x_command_handlers[] = {
  892. {
  893. .name = "efm32",
  894. .mode = COMMAND_ANY,
  895. .help = "efm32 flash command group",
  896. .usage = "",
  897. .chain = efm32x_exec_command_handlers,
  898. },
  899. COMMAND_REGISTRATION_DONE
  900. };
  901. const struct flash_driver efm32_flash = {
  902. .name = "efm32",
  903. .commands = efm32x_command_handlers,
  904. .flash_bank_command = efm32x_flash_bank_command,
  905. .erase = efm32x_erase,
  906. .protect = efm32x_protect,
  907. .write = efm32x_write,
  908. .read = default_flash_read,
  909. .probe = efm32x_probe,
  910. .auto_probe = efm32x_auto_probe,
  911. .erase_check = default_flash_blank_check,
  912. .protect_check = efm32x_protect_check,
  913. .info = get_efm32x_info,
  914. .free_driver_priv = default_flash_free_driver_priv,
  915. };