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  1. /*
  2. * Copyright (C) 2009 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the
  16. * Free Software Foundation, Inc.,
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18. */
  19. #ifdef HAVE_CONFIG_H
  20. #include "config.h"
  21. #endif
  22. #include "arm.h"
  23. #include "arm_dpm.h"
  24. #include <jtag/jtag.h>
  25. #include "register.h"
  26. #include "breakpoints.h"
  27. #include "target_type.h"
  28. #include "arm_opcodes.h"
  29. /**
  30. * @file
  31. * Implements various ARM DPM operations using architectural debug registers.
  32. * These routines layer over core-specific communication methods to cope with
  33. * implementation differences between cores like ARM1136 and Cortex-A8.
  34. *
  35. * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
  36. * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
  37. * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
  38. * are abstracted through internal programming interfaces to share code and
  39. * to minimize needless differences in debug behavior between cores.
  40. */
  41. /*----------------------------------------------------------------------*/
  42. /*
  43. * Coprocessor support
  44. */
  45. /* Read coprocessor */
  46. static int dpm_mrc(struct target *target, int cpnum,
  47. uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  48. uint32_t *value)
  49. {
  50. struct arm *arm = target_to_arm(target);
  51. struct arm_dpm *dpm = arm->dpm;
  52. int retval;
  53. retval = dpm->prepare(dpm);
  54. if (retval != ERROR_OK)
  55. return retval;
  56. LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  57. (int) op1, (int) CRn,
  58. (int) CRm, (int) op2);
  59. /* read coprocessor register into R0; return via DCC */
  60. retval = dpm->instr_read_data_r0(dpm,
  61. ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  62. value);
  63. /* (void) */ dpm->finish(dpm);
  64. return retval;
  65. }
  66. static int dpm_mcr(struct target *target, int cpnum,
  67. uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  68. uint32_t value)
  69. {
  70. struct arm *arm = target_to_arm(target);
  71. struct arm_dpm *dpm = arm->dpm;
  72. int retval;
  73. retval = dpm->prepare(dpm);
  74. if (retval != ERROR_OK)
  75. return retval;
  76. LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  77. (int) op1, (int) CRn,
  78. (int) CRm, (int) op2);
  79. /* read DCC into r0; then write coprocessor register from R0 */
  80. retval = dpm->instr_write_data_r0(dpm,
  81. ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  82. value);
  83. /* (void) */ dpm->finish(dpm);
  84. return retval;
  85. }
  86. /*----------------------------------------------------------------------*/
  87. /*
  88. * Register access utilities
  89. */
  90. /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  91. * Routines *must* restore the original mode before returning!!
  92. */
  93. int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
  94. {
  95. int retval;
  96. uint32_t cpsr;
  97. /* restore previous mode */
  98. if (mode == ARM_MODE_ANY)
  99. cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
  100. /* else force to the specified mode */
  101. else
  102. cpsr = mode;
  103. retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
  104. if (retval != ERROR_OK)
  105. return retval;
  106. if (dpm->instr_cpsr_sync)
  107. retval = dpm->instr_cpsr_sync(dpm);
  108. return retval;
  109. }
  110. /* just read the register -- rely on the core mode being right */
  111. static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
  112. {
  113. uint32_t value;
  114. int retval;
  115. switch (regnum) {
  116. case 0 ... 14:
  117. /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
  118. retval = dpm->instr_read_data_dcc(dpm,
  119. ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
  120. &value);
  121. break;
  122. case 15:/* PC
  123. * "MOV r0, pc"; then return via DCC */
  124. retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
  125. /* NOTE: this seems like a slightly awkward place to update
  126. * this value ... but if the PC gets written (the only way
  127. * to change what we compute), the arch spec says subsequent
  128. * reads return values which are "unpredictable". So this
  129. * is always right except in those broken-by-intent cases.
  130. */
  131. switch (dpm->arm->core_state) {
  132. case ARM_STATE_ARM:
  133. value -= 8;
  134. break;
  135. case ARM_STATE_THUMB:
  136. case ARM_STATE_THUMB_EE:
  137. value -= 4;
  138. break;
  139. case ARM_STATE_JAZELLE:
  140. /* core-specific ... ? */
  141. LOG_WARNING("Jazelle PC adjustment unknown");
  142. break;
  143. }
  144. break;
  145. default:
  146. /* 16: "MRS r0, CPSR"; then return via DCC
  147. * 17: "MRS r0, SPSR"; then return via DCC
  148. */
  149. retval = dpm->instr_read_data_r0(dpm,
  150. ARMV4_5_MRS(0, regnum & 1),
  151. &value);
  152. break;
  153. }
  154. if (retval == ERROR_OK) {
  155. buf_set_u32(r->value, 0, 32, value);
  156. r->valid = true;
  157. r->dirty = false;
  158. LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
  159. }
  160. return retval;
  161. }
  162. /* just write the register -- rely on the core mode being right */
  163. static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
  164. {
  165. int retval;
  166. uint32_t value = buf_get_u32(r->value, 0, 32);
  167. switch (regnum) {
  168. case 0 ... 14:
  169. /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
  170. retval = dpm->instr_write_data_dcc(dpm,
  171. ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
  172. value);
  173. break;
  174. case 15:/* PC
  175. * read r0 from DCC; then "MOV pc, r0" */
  176. retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
  177. break;
  178. default:
  179. /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
  180. * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
  181. */
  182. retval = dpm->instr_write_data_r0(dpm,
  183. ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
  184. value);
  185. if (retval != ERROR_OK)
  186. return retval;
  187. if (regnum == 16 && dpm->instr_cpsr_sync)
  188. retval = dpm->instr_cpsr_sync(dpm);
  189. break;
  190. }
  191. if (retval == ERROR_OK) {
  192. r->dirty = false;
  193. LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
  194. }
  195. return retval;
  196. }
  197. /**
  198. * Read basic registers of the the current context: R0 to R15, and CPSR;
  199. * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  200. * In normal operation this is called on entry to halting debug state,
  201. * possibly after some other operations supporting restore of debug state
  202. * or making sure the CPU is fully idle (drain write buffer, etc).
  203. */
  204. int arm_dpm_read_current_registers(struct arm_dpm *dpm)
  205. {
  206. struct arm *arm = dpm->arm;
  207. uint32_t cpsr;
  208. int retval;
  209. struct reg *r;
  210. retval = dpm->prepare(dpm);
  211. if (retval != ERROR_OK)
  212. return retval;
  213. /* read R0 first (it's used for scratch), then CPSR */
  214. r = arm->core_cache->reg_list + 0;
  215. if (!r->valid) {
  216. retval = dpm_read_reg(dpm, r, 0);
  217. if (retval != ERROR_OK)
  218. goto fail;
  219. }
  220. r->dirty = true;
  221. retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
  222. if (retval != ERROR_OK)
  223. goto fail;
  224. /* update core mode and state, plus shadow mapping for R8..R14 */
  225. arm_set_cpsr(arm, cpsr);
  226. /* REVISIT we can probably avoid reading R1..R14, saving time... */
  227. for (unsigned i = 1; i < 16; i++) {
  228. r = arm_reg_current(arm, i);
  229. if (r->valid)
  230. continue;
  231. retval = dpm_read_reg(dpm, r, i);
  232. if (retval != ERROR_OK)
  233. goto fail;
  234. }
  235. /* NOTE: SPSR ignored (if it's even relevant). */
  236. /* REVISIT the debugger can trigger various exceptions. See the
  237. * ARMv7A architecture spec, section C5.7, for more info about
  238. * what defenses are needed; v6 debug has the most issues.
  239. */
  240. fail:
  241. /* (void) */ dpm->finish(dpm);
  242. return retval;
  243. }
  244. /* Avoid needless I/O ... leave breakpoints and watchpoints alone
  245. * unless they're removed, or need updating because of single-stepping
  246. * or running debugger code.
  247. */
  248. static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
  249. struct dpm_bpwp *xp, int *set_p)
  250. {
  251. int retval = ERROR_OK;
  252. bool disable;
  253. if (!set_p) {
  254. if (!xp->dirty)
  255. goto done;
  256. xp->dirty = false;
  257. /* removed or startup; we must disable it */
  258. disable = true;
  259. } else if (bpwp) {
  260. if (!xp->dirty)
  261. goto done;
  262. /* disabled, but we must set it */
  263. xp->dirty = disable = false;
  264. *set_p = true;
  265. } else {
  266. if (!*set_p)
  267. goto done;
  268. /* set, but we must temporarily disable it */
  269. xp->dirty = disable = true;
  270. *set_p = false;
  271. }
  272. if (disable)
  273. retval = dpm->bpwp_disable(dpm, xp->number);
  274. else
  275. retval = dpm->bpwp_enable(dpm, xp->number,
  276. xp->address, xp->control);
  277. if (retval != ERROR_OK)
  278. LOG_ERROR("%s: can't %s HW %spoint %d",
  279. disable ? "disable" : "enable",
  280. target_name(dpm->arm->target),
  281. (xp->number < 16) ? "break" : "watch",
  282. xp->number & 0xf);
  283. done:
  284. return retval;
  285. }
  286. static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
  287. /**
  288. * Writes all modified core registers for all processor modes. In normal
  289. * operation this is called on exit from halting debug state.
  290. *
  291. * @param dpm: represents the processor
  292. * @param bpwp: true ensures breakpoints and watchpoints are set,
  293. * false ensures they are cleared
  294. */
  295. int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
  296. {
  297. struct arm *arm = dpm->arm;
  298. struct reg_cache *cache = arm->core_cache;
  299. int retval;
  300. bool did_write;
  301. retval = dpm->prepare(dpm);
  302. if (retval != ERROR_OK)
  303. goto done;
  304. /* If we're managing hardware breakpoints for this core, enable
  305. * or disable them as requested.
  306. *
  307. * REVISIT We don't yet manage them for ANY cores. Eventually
  308. * we should be able to assume we handle them; but until then,
  309. * cope with the hand-crafted breakpoint code.
  310. */
  311. if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
  312. for (unsigned i = 0; i < dpm->nbp; i++) {
  313. struct dpm_bp *dbp = dpm->dbp + i;
  314. struct breakpoint *bp = dbp->bp;
  315. retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
  316. bp ? &bp->set : NULL);
  317. if (retval != ERROR_OK)
  318. goto done;
  319. }
  320. }
  321. /* enable/disable watchpoints */
  322. for (unsigned i = 0; i < dpm->nwp; i++) {
  323. struct dpm_wp *dwp = dpm->dwp + i;
  324. struct watchpoint *wp = dwp->wp;
  325. retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
  326. wp ? &wp->set : NULL);
  327. if (retval != ERROR_OK)
  328. goto done;
  329. }
  330. /* NOTE: writes to breakpoint and watchpoint registers might
  331. * be queued, and need (efficient/batched) flushing later.
  332. */
  333. /* Scan the registers until we find one that's both dirty and
  334. * eligible for flushing. Flush that and everything else that
  335. * shares the same core mode setting. Typically this won't
  336. * actually find anything to do...
  337. */
  338. do {
  339. enum arm_mode mode = ARM_MODE_ANY;
  340. did_write = false;
  341. /* check everything except our scratch register R0 */
  342. for (unsigned i = 1; i < cache->num_regs; i++) {
  343. struct arm_reg *r;
  344. unsigned regnum;
  345. /* also skip PC, CPSR, and non-dirty */
  346. if (i == 15)
  347. continue;
  348. if (arm->cpsr == cache->reg_list + i)
  349. continue;
  350. if (!cache->reg_list[i].dirty)
  351. continue;
  352. r = cache->reg_list[i].arch_info;
  353. regnum = r->num;
  354. /* may need to pick and set a mode */
  355. if (!did_write) {
  356. enum arm_mode tmode;
  357. did_write = true;
  358. mode = tmode = r->mode;
  359. /* cope with special cases */
  360. switch (regnum) {
  361. case 8 ... 12:
  362. /* r8..r12 "anything but FIQ" case;
  363. * we "know" core mode is accurate
  364. * since we haven't changed it yet
  365. */
  366. if (arm->core_mode == ARM_MODE_FIQ
  367. && ARM_MODE_ANY
  368. != mode)
  369. tmode = ARM_MODE_USR;
  370. break;
  371. case 16:
  372. /* SPSR */
  373. regnum++;
  374. break;
  375. }
  376. /* REVISIT error checks */
  377. if (tmode != ARM_MODE_ANY) {
  378. retval = dpm_modeswitch(dpm, tmode);
  379. if (retval != ERROR_OK)
  380. goto done;
  381. }
  382. }
  383. if (r->mode != mode)
  384. continue;
  385. retval = dpm_write_reg(dpm,
  386. &cache->reg_list[i],
  387. regnum);
  388. if (retval != ERROR_OK)
  389. goto done;
  390. }
  391. } while (did_write);
  392. /* Restore original CPSR ... assuming either that we changed it,
  393. * or it's dirty. Must write PC to ensure the return address is
  394. * defined, and must not write it before CPSR.
  395. */
  396. retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
  397. if (retval != ERROR_OK)
  398. goto done;
  399. arm->cpsr->dirty = false;
  400. retval = dpm_write_reg(dpm, arm->pc, 15);
  401. if (retval != ERROR_OK)
  402. goto done;
  403. arm->pc->dirty = false;
  404. /* flush R0 -- it's *very* dirty by now */
  405. retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
  406. if (retval != ERROR_OK)
  407. goto done;
  408. cache->reg_list[0].dirty = false;
  409. /* (void) */ dpm->finish(dpm);
  410. done:
  411. return retval;
  412. }
  413. /* Returns ARM_MODE_ANY or temporary mode to use while reading the
  414. * specified register ... works around flakiness from ARM core calls.
  415. * Caller already filtered out SPSR access; mode is never MODE_SYS
  416. * or MODE_ANY.
  417. */
  418. static enum arm_mode dpm_mapmode(struct arm *arm,
  419. unsigned num, enum arm_mode mode)
  420. {
  421. enum arm_mode amode = arm->core_mode;
  422. /* don't switch if the mode is already correct */
  423. if (amode == ARM_MODE_SYS)
  424. amode = ARM_MODE_USR;
  425. if (mode == amode)
  426. return ARM_MODE_ANY;
  427. switch (num) {
  428. /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
  429. case 0 ... 7:
  430. case 15:
  431. case 16:
  432. break;
  433. /* r8..r12 aren't shadowed for anything except FIQ */
  434. case 8 ... 12:
  435. if (mode == ARM_MODE_FIQ)
  436. return mode;
  437. break;
  438. /* r13/sp, and r14/lr are always shadowed */
  439. case 13:
  440. case 14:
  441. return mode;
  442. default:
  443. LOG_WARNING("invalid register #%u", num);
  444. break;
  445. }
  446. return ARM_MODE_ANY;
  447. }
  448. /*
  449. * Standard ARM register accessors ... there are three methods
  450. * in "struct arm", to support individual read/write and bulk read
  451. * of registers.
  452. */
  453. static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
  454. int regnum, enum arm_mode mode)
  455. {
  456. struct arm_dpm *dpm = target_to_arm(target)->dpm;
  457. int retval;
  458. if (regnum < 0 || regnum > 16)
  459. return ERROR_COMMAND_SYNTAX_ERROR;
  460. if (regnum == 16) {
  461. if (mode != ARM_MODE_ANY)
  462. regnum = 17;
  463. } else
  464. mode = dpm_mapmode(dpm->arm, regnum, mode);
  465. /* REVISIT what happens if we try to read SPSR in a core mode
  466. * which has no such register?
  467. */
  468. retval = dpm->prepare(dpm);
  469. if (retval != ERROR_OK)
  470. return retval;
  471. if (mode != ARM_MODE_ANY) {
  472. retval = dpm_modeswitch(dpm, mode);
  473. if (retval != ERROR_OK)
  474. goto fail;
  475. }
  476. retval = dpm_read_reg(dpm, r, regnum);
  477. if (retval != ERROR_OK)
  478. goto fail;
  479. /* always clean up, regardless of error */
  480. if (mode != ARM_MODE_ANY)
  481. /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
  482. fail:
  483. /* (void) */ dpm->finish(dpm);
  484. return retval;
  485. }
  486. static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
  487. int regnum, enum arm_mode mode, uint32_t value)
  488. {
  489. struct arm_dpm *dpm = target_to_arm(target)->dpm;
  490. int retval;
  491. if (regnum < 0 || regnum > 16)
  492. return ERROR_COMMAND_SYNTAX_ERROR;
  493. if (regnum == 16) {
  494. if (mode != ARM_MODE_ANY)
  495. regnum = 17;
  496. } else
  497. mode = dpm_mapmode(dpm->arm, regnum, mode);
  498. /* REVISIT what happens if we try to write SPSR in a core mode
  499. * which has no such register?
  500. */
  501. retval = dpm->prepare(dpm);
  502. if (retval != ERROR_OK)
  503. return retval;
  504. if (mode != ARM_MODE_ANY) {
  505. retval = dpm_modeswitch(dpm, mode);
  506. if (retval != ERROR_OK)
  507. goto fail;
  508. }
  509. retval = dpm_write_reg(dpm, r, regnum);
  510. /* always clean up, regardless of error */
  511. if (mode != ARM_MODE_ANY)
  512. /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
  513. fail:
  514. /* (void) */ dpm->finish(dpm);
  515. return retval;
  516. }
  517. static int arm_dpm_full_context(struct target *target)
  518. {
  519. struct arm *arm = target_to_arm(target);
  520. struct arm_dpm *dpm = arm->dpm;
  521. struct reg_cache *cache = arm->core_cache;
  522. int retval;
  523. bool did_read;
  524. retval = dpm->prepare(dpm);
  525. if (retval != ERROR_OK)
  526. goto done;
  527. do {
  528. enum arm_mode mode = ARM_MODE_ANY;
  529. did_read = false;
  530. /* We "know" arm_dpm_read_current_registers() was called so
  531. * the unmapped registers (R0..R7, PC, AND CPSR) and some
  532. * view of R8..R14 are current. We also "know" oddities of
  533. * register mapping: special cases for R8..R12 and SPSR.
  534. *
  535. * Pick some mode with unread registers and read them all.
  536. * Repeat until done.
  537. */
  538. for (unsigned i = 0; i < cache->num_regs; i++) {
  539. struct arm_reg *r;
  540. if (cache->reg_list[i].valid)
  541. continue;
  542. r = cache->reg_list[i].arch_info;
  543. /* may need to pick a mode and set CPSR */
  544. if (!did_read) {
  545. did_read = true;
  546. mode = r->mode;
  547. /* For R8..R12 when we've entered debug
  548. * state in FIQ mode... patch mode.
  549. */
  550. if (mode == ARM_MODE_ANY)
  551. mode = ARM_MODE_USR;
  552. /* REVISIT error checks */
  553. retval = dpm_modeswitch(dpm, mode);
  554. if (retval != ERROR_OK)
  555. goto done;
  556. }
  557. if (r->mode != mode)
  558. continue;
  559. /* CPSR was read, so "R16" must mean SPSR */
  560. retval = dpm_read_reg(dpm,
  561. &cache->reg_list[i],
  562. (r->num == 16) ? 17 : r->num);
  563. if (retval != ERROR_OK)
  564. goto done;
  565. }
  566. } while (did_read);
  567. retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
  568. /* (void) */ dpm->finish(dpm);
  569. done:
  570. return retval;
  571. }
  572. /*----------------------------------------------------------------------*/
  573. /*
  574. * Breakpoint and Watchpoint support.
  575. *
  576. * Hardware {break,watch}points are usually left active, to minimize
  577. * debug entry/exit costs. When they are set or cleared, it's done in
  578. * batches. Also, DPM-conformant hardware can update debug registers
  579. * regardless of whether the CPU is running or halted ... though that
  580. * fact isn't currently leveraged.
  581. */
  582. static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
  583. uint32_t addr, uint32_t length)
  584. {
  585. uint32_t control;
  586. control = (1 << 0) /* enable */
  587. | (3 << 1); /* both user and privileged access */
  588. /* Match 1, 2, or all 4 byte addresses in this word.
  589. *
  590. * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
  591. * Support larger length, when addr is suitably aligned. In
  592. * particular, allow watchpoints on 8 byte "double" values.
  593. *
  594. * REVISIT allow watchpoints on unaligned 2-bit values; and on
  595. * v7 hardware, unaligned 4-byte ones too.
  596. */
  597. switch (length) {
  598. case 1:
  599. control |= (1 << (addr & 3)) << 5;
  600. break;
  601. case 2:
  602. /* require 2-byte alignment */
  603. if (!(addr & 1)) {
  604. control |= (3 << (addr & 2)) << 5;
  605. break;
  606. }
  607. /* FALL THROUGH */
  608. case 4:
  609. /* require 4-byte alignment */
  610. if (!(addr & 3)) {
  611. control |= 0xf << 5;
  612. break;
  613. }
  614. /* FALL THROUGH */
  615. default:
  616. LOG_ERROR("unsupported {break,watch}point length/alignment");
  617. return ERROR_COMMAND_SYNTAX_ERROR;
  618. }
  619. /* other shared control bits:
  620. * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
  621. * bit 20 == 0 ... not linked to a context ID
  622. * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
  623. */
  624. xp->address = addr & ~3;
  625. xp->control = control;
  626. xp->dirty = true;
  627. LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
  628. xp->address, control, xp->number);
  629. /* hardware is updated in write_dirty_registers() */
  630. return ERROR_OK;
  631. }
  632. static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
  633. {
  634. struct arm *arm = target_to_arm(target);
  635. struct arm_dpm *dpm = arm->dpm;
  636. int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  637. if (bp->length < 2)
  638. return ERROR_COMMAND_SYNTAX_ERROR;
  639. if (!dpm->bpwp_enable)
  640. return retval;
  641. /* FIXME we need a generic solution for software breakpoints. */
  642. if (bp->type == BKPT_SOFT)
  643. LOG_DEBUG("using HW bkpt, not SW...");
  644. for (unsigned i = 0; i < dpm->nbp; i++) {
  645. if (!dpm->dbp[i].bp) {
  646. retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
  647. bp->address, bp->length);
  648. if (retval == ERROR_OK)
  649. dpm->dbp[i].bp = bp;
  650. break;
  651. }
  652. }
  653. return retval;
  654. }
  655. static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
  656. {
  657. struct arm *arm = target_to_arm(target);
  658. struct arm_dpm *dpm = arm->dpm;
  659. int retval = ERROR_COMMAND_SYNTAX_ERROR;
  660. for (unsigned i = 0; i < dpm->nbp; i++) {
  661. if (dpm->dbp[i].bp == bp) {
  662. dpm->dbp[i].bp = NULL;
  663. dpm->dbp[i].bpwp.dirty = true;
  664. /* hardware is updated in write_dirty_registers() */
  665. retval = ERROR_OK;
  666. break;
  667. }
  668. }
  669. return retval;
  670. }
  671. static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
  672. struct watchpoint *wp)
  673. {
  674. int retval;
  675. struct dpm_wp *dwp = dpm->dwp + index_t;
  676. uint32_t control;
  677. /* this hardware doesn't support data value matching or masking */
  678. if (wp->value || wp->mask != ~(uint32_t)0) {
  679. LOG_DEBUG("watchpoint values and masking not supported");
  680. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  681. }
  682. retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
  683. if (retval != ERROR_OK)
  684. return retval;
  685. control = dwp->bpwp.control;
  686. switch (wp->rw) {
  687. case WPT_READ:
  688. control |= 1 << 3;
  689. break;
  690. case WPT_WRITE:
  691. control |= 2 << 3;
  692. break;
  693. case WPT_ACCESS:
  694. control |= 3 << 3;
  695. break;
  696. }
  697. dwp->bpwp.control = control;
  698. dpm->dwp[index_t].wp = wp;
  699. return retval;
  700. }
  701. static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
  702. {
  703. struct arm *arm = target_to_arm(target);
  704. struct arm_dpm *dpm = arm->dpm;
  705. int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  706. if (dpm->bpwp_enable) {
  707. for (unsigned i = 0; i < dpm->nwp; i++) {
  708. if (!dpm->dwp[i].wp) {
  709. retval = dpm_watchpoint_setup(dpm, i, wp);
  710. break;
  711. }
  712. }
  713. }
  714. return retval;
  715. }
  716. static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
  717. {
  718. struct arm *arm = target_to_arm(target);
  719. struct arm_dpm *dpm = arm->dpm;
  720. int retval = ERROR_COMMAND_SYNTAX_ERROR;
  721. for (unsigned i = 0; i < dpm->nwp; i++) {
  722. if (dpm->dwp[i].wp == wp) {
  723. dpm->dwp[i].wp = NULL;
  724. dpm->dwp[i].bpwp.dirty = true;
  725. /* hardware is updated in write_dirty_registers() */
  726. retval = ERROR_OK;
  727. break;
  728. }
  729. }
  730. return retval;
  731. }
  732. void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
  733. {
  734. switch (dpm->arm->core_state) {
  735. case ARM_STATE_ARM:
  736. addr -= 8;
  737. break;
  738. case ARM_STATE_THUMB:
  739. case ARM_STATE_THUMB_EE:
  740. addr -= 4;
  741. break;
  742. case ARM_STATE_JAZELLE:
  743. /* ?? */
  744. break;
  745. }
  746. dpm->wp_pc = addr;
  747. }
  748. /*----------------------------------------------------------------------*/
  749. /*
  750. * Other debug and support utilities
  751. */
  752. void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
  753. {
  754. struct target *target = dpm->arm->target;
  755. dpm->dscr = dscr;
  756. /* Examine debug reason */
  757. switch (DSCR_ENTRY(dscr)) {
  758. case 6: /* Data abort (v6 only) */
  759. case 7: /* Prefetch abort (v6 only) */
  760. /* FALL THROUGH -- assume a v6 core in abort mode */
  761. case 0: /* HALT request from debugger */
  762. case 4: /* EDBGRQ */
  763. target->debug_reason = DBG_REASON_DBGRQ;
  764. break;
  765. case 1: /* HW breakpoint */
  766. case 3: /* SW BKPT */
  767. case 5: /* vector catch */
  768. target->debug_reason = DBG_REASON_BREAKPOINT;
  769. break;
  770. case 2: /* asynch watchpoint */
  771. case 10:/* precise watchpoint */
  772. target->debug_reason = DBG_REASON_WATCHPOINT;
  773. break;
  774. default:
  775. target->debug_reason = DBG_REASON_UNDEFINED;
  776. break;
  777. }
  778. }
  779. /*----------------------------------------------------------------------*/
  780. /*
  781. * Setup and management support.
  782. */
  783. /**
  784. * Hooks up this DPM to its associated target; call only once.
  785. * Initially this only covers the register cache.
  786. *
  787. * Oh, and watchpoints. Yeah.
  788. */
  789. int arm_dpm_setup(struct arm_dpm *dpm)
  790. {
  791. struct arm *arm = dpm->arm;
  792. struct target *target = arm->target;
  793. struct reg_cache *cache;
  794. arm->dpm = dpm;
  795. /* register access setup */
  796. arm->full_context = arm_dpm_full_context;
  797. arm->read_core_reg = arm_dpm_read_core_reg;
  798. arm->write_core_reg = arm_dpm_write_core_reg;
  799. cache = arm_build_reg_cache(target, arm);
  800. if (!cache)
  801. return ERROR_FAIL;
  802. *register_get_last_cache_p(&target->reg_cache) = cache;
  803. /* coprocessor access setup */
  804. arm->mrc = dpm_mrc;
  805. arm->mcr = dpm_mcr;
  806. /* breakpoint setup -- optional until it works everywhere */
  807. if (!target->type->add_breakpoint) {
  808. target->type->add_breakpoint = dpm_add_breakpoint;
  809. target->type->remove_breakpoint = dpm_remove_breakpoint;
  810. }
  811. /* watchpoint setup */
  812. target->type->add_watchpoint = dpm_add_watchpoint;
  813. target->type->remove_watchpoint = dpm_remove_watchpoint;
  814. /* FIXME add vector catch support */
  815. dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
  816. dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
  817. dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
  818. dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
  819. if (!dpm->dbp || !dpm->dwp) {
  820. free(dpm->dbp);
  821. free(dpm->dwp);
  822. return ERROR_FAIL;
  823. }
  824. LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
  825. target_name(target), dpm->nbp, dpm->nwp);
  826. /* REVISIT ... and some of those breakpoints could match
  827. * execution context IDs...
  828. */
  829. return ERROR_OK;
  830. }
  831. /**
  832. * Reinitializes DPM state at the beginning of a new debug session
  833. * or after a reset which may have affected the debug module.
  834. */
  835. int arm_dpm_initialize(struct arm_dpm *dpm)
  836. {
  837. /* Disable all breakpoints and watchpoints at startup. */
  838. if (dpm->bpwp_disable) {
  839. unsigned i;
  840. for (i = 0; i < dpm->nbp; i++) {
  841. dpm->dbp[i].bpwp.number = i;
  842. (void) dpm->bpwp_disable(dpm, i);
  843. }
  844. for (i = 0; i < dpm->nwp; i++) {
  845. dpm->dwp[i].bpwp.number = 16 + i;
  846. (void) dpm->bpwp_disable(dpm, 16 + i);
  847. }
  848. } else
  849. LOG_WARNING("%s: can't disable breakpoints and watchpoints",
  850. target_name(dpm->arm->target));
  851. return ERROR_OK;
  852. }