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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundinªmlu.mine.nu *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifndef AT91SAM7_H
  21. #define AT91SAM7_H
  22. #include "flash.h"
  23. #include "target.h"
  24. typedef struct at91sam7_flash_bank_s
  25. {
  26. u32 working_area;
  27. u32 working_area_size;
  28. /* chip id register */
  29. u32 cidr;
  30. u16 cidr_ext;
  31. u16 cidr_nvptyp;
  32. u16 cidr_arch;
  33. u16 cidr_sramsiz;
  34. u16 cidr_nvpsiz;
  35. u16 cidr_nvpsiz2;
  36. u16 cidr_eproc;
  37. u16 cidr_version;
  38. char * target_name;
  39. /* flash geometry */
  40. u16 num_pages;
  41. u16 pagesize;
  42. u16 pages_in_lockregion;
  43. u8 num_erase_regions;
  44. u32 *erase_region_info;
  45. /* nv memory bits */
  46. u16 num_lockbits;
  47. u16 lockbits;
  48. u16 num_nvmbits;
  49. u16 nvmbits;
  50. u8 securitybit;
  51. u8 flashmode; /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */
  52. /* main clock status */
  53. u8 mck_valid;
  54. u32 mck_freq;
  55. } at91sam7_flash_bank_t;
  56. /* AT91SAM7 control registers */
  57. #define DBGU_CIDR 0xFFFFF240
  58. #define CKGR_MCFR 0xFFFFFC24
  59. #define CKGR_MCFR_MAINRDY 0x10000
  60. #define CKGR_PLLR 0xFFFFFC2c
  61. #define CKGR_PLLR_DIV 0xff
  62. #define CKGR_PLLR_MUL 0x07ff0000
  63. #define PMC_MCKR 0xFFFFFC30
  64. #define PMC_MCKR_CSS 0x03
  65. #define PMC_MCKR_PRES 0x1c
  66. #define MC_FMR 0xFFFFFF60
  67. #define MC_FCR 0xFFFFFF64
  68. #define MC_FSR 0xFFFFFF68
  69. /* Flash Controller Commands */
  70. #define WP 0x01
  71. #define SLB 0x02
  72. #define WPL 0x03
  73. #define CLB 0x04
  74. #define EA 0x08
  75. #define SGPB 0x0B
  76. #define CGPB 0x0D
  77. #define SSB 0x0F
  78. /* MC_FSR bit definitions */
  79. #define MC_FSR_FRDY 1
  80. #define MC_FSR_EOL 2
  81. /* AT91SAM7 constants */
  82. #define RC_FREQ 32000
  83. /* FLASH_TIMING_MODES */
  84. #define FMR_TIMING_NONE 0
  85. #define FMR_TIMING_NVBITS 1
  86. #define FMR_TIMING_FLASH 2
  87. #endif /* AT91SAM7_H */