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openocd/src/target/arm7_9_common.c

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  1. /***************************************************************************

  2.  *   Copyright (C) 2005 by Dominic Rath                                    *

  3.  *   Dominic.Rath@gmx.de                                                   *

  4.  *                                                                         *

  5.  *   This program is free software; you can redistribute it and/or modify  *

  6.  *   it under the terms of the GNU General Public License as published by  *

  7.  *   the Free Software Foundation; either version 2 of the License, or     *

  8.  *   (at your option) any later version.                                   *

  9.  *                                                                         *

  10.  *   This program is distributed in the hope that it will be useful,       *

  11.  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

  12.  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

  13.  *   GNU General Public License for more details.                          *

  14.  *                                                                         *

  15.  *   You should have received a copy of the GNU General Public License     *

  16.  *   along with this program; if not, write to the                         *

  17.  *   Free Software Foundation, Inc.,                                       *

  18.  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *

  19.  ***************************************************************************/

  20. #ifdef HAVE_CONFIG_H

  21. #include "config.h"

  22. #endif

  23. 

  24. #include "replacements.h"

  25. 

  26. #include "embeddedice.h"

  27. #include "target.h"

  28. #include "armv4_5.h"

  29. #include "arm_jtag.h"

  30. #include "jtag.h"

  31. #include "log.h"

  32. #include "arm7_9_common.h"

  33. #include "breakpoints.h"

  34. 

  35. #include <stdlib.h>

  36. #include <string.h>

  37. #include <unistd.h>

  38. 

  39. #include <sys/types.h>

  40. #include <sys/stat.h>

  41. #include <sys/time.h>

  42. #include <errno.h>

  43. 

  44. int arm7_9_debug_entry(target_t *target);

  45. int arm7_9_enable_sw_bkpts(struct target_s *target);

  46. 

  47. /* command handler forward declarations */

  48. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  49. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  50. int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  51. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  52. int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  53. int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  54. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  55. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  56. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  57. int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

  58. 

  59. int arm7_9_reinit_embeddedice(target_t *target)

  60. {

  61. 	armv4_5_common_t *armv4_5 = target->arch_info;

  62. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  63. 	

  64. 	breakpoint_t *breakpoint = target->breakpoints;

  65. 	

  66. 	arm7_9->wp_available = 2;

  67. 	arm7_9->wp0_used = 0;

  68. 	arm7_9->wp1_used = 0;

  69. 		

  70. 	/* mark all hardware breakpoints as unset */

  71. 	while (breakpoint)

  72. 	{

  73. 		if (breakpoint->type == BKPT_HARD)

  74. 		{

  75. 			breakpoint->set = 0;

  76. 		}

  77. 		breakpoint = breakpoint->next;

  78. 	}

  79. 		

  80. 	if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)

  81. 	{

  82. 		arm7_9->sw_bkpts_enabled = 0;

  83. 		arm7_9_enable_sw_bkpts(target);

  84. 	}

  85. 	

  86. 	arm7_9->reinit_embeddedice = 0;

  87. 	

  88. 	return ERROR_OK;

  89. }

  90. 

  91. int arm7_9_jtag_callback(enum jtag_event event, void *priv)

  92. {

  93. 	target_t *target = priv;

  94. 	armv4_5_common_t *armv4_5 = target->arch_info;

  95. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  96. 	

  97. 	/* a test-logic reset occured

  98. 	 * the EmbeddedICE registers have been reset

  99. 	 * hardware breakpoints have been cleared

  100. 	 */

  101. 	if (event == JTAG_TRST_ASSERTED)

  102. 	{

  103. 		arm7_9->reinit_embeddedice = 1;

  104. 	}

  105. 	

  106. 	return ERROR_OK;

  107. }

  108. 

  109. int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)

  110. {

  111. 	armv4_5_common_t *armv4_5 = target->arch_info;

  112. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  113. 	

  114. 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)

  115. 	{

  116. 		return -1;

  117. 	}

  118. 	

  119. 	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)

  120. 	{

  121. 		return -1;

  122. 	}

  123. 	

  124. 	*armv4_5_p = armv4_5;

  125. 	*arm7_9_p = arm7_9;

  126. 	

  127. 	return ERROR_OK;

  128. }

  129. 

  130. int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)

  131. {

  132. 	armv4_5_common_t *armv4_5 = target->arch_info;

  133. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  134. 	

  135. 	if (target->state != TARGET_HALTED)

  136. 	{

  137. 		WARNING("target not halted");

  138. 		return ERROR_TARGET_NOT_HALTED;

  139. 	}

  140. 	

  141. 	if (arm7_9->force_hw_bkpts)

  142. 		breakpoint->type = BKPT_HARD;

  143. 

  144. 	if (breakpoint->set)

  145. 	{

  146. 		WARNING("breakpoint already set");

  147. 		return ERROR_OK;

  148. 	}

  149. 

  150. 	if (breakpoint->type == BKPT_HARD)

  151. 	{

  152. 		/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */

  153. 		u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;

  154. 		if (!arm7_9->wp0_used)

  155. 		{

  156. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);

  157. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);

  158. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);

  159. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);

  160. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

  161. 

  162. 			jtag_execute_queue();

  163. 			arm7_9->wp0_used = 1;

  164. 			breakpoint->set = 1;

  165. 		}

  166. 		else if (!arm7_9->wp1_used)

  167. 		{

  168. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);

  169. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);

  170. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);

  171. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);

  172. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

  173. 

  174. 			jtag_execute_queue();

  175. 			arm7_9->wp1_used = 1;

  176. 			breakpoint->set = 2;

  177. 		}

  178. 		else

  179. 		{

  180. 			ERROR("BUG: no hardware comparator available");

  181. 			return ERROR_OK;

  182. 		}

  183. 	}

  184. 	else if (breakpoint->type == BKPT_SOFT)

  185. 	{

  186. 		if (breakpoint->length == 4)

  187. 		{

  188. 			/* keep the original instruction in target endianness */

  189. 			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);

  190. 			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */

  191. 			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);

  192. 		}

  193. 		else

  194. 		{

  195. 			/* keep the original instruction in target endianness */

  196. 			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);

  197. 			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */

  198. 			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);

  199. 		}

  200. 		breakpoint->set = 1;

  201. 	}

  202. 

  203. 	return ERROR_OK;

  204. 

  205. }

  206. 

  207. int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)

  208. {

  209. 	armv4_5_common_t *armv4_5 = target->arch_info;

  210. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  211. 	

  212. 	if (target->state != TARGET_HALTED)

  213. 	{

  214. 		WARNING("target not halted");

  215. 		return ERROR_TARGET_NOT_HALTED;

  216. 	}

  217. 

  218. 	if (!breakpoint->set)

  219. 	{

  220. 		WARNING("breakpoint not set");

  221. 		return ERROR_OK;

  222. 	}

  223. 	

  224. 	if (breakpoint->type == BKPT_HARD)

  225. 	{

  226. 		if (breakpoint->set == 1)

  227. 		{

  228. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);

  229. 			jtag_execute_queue();

  230. 			arm7_9->wp0_used = 0;

  231. 		}

  232. 		else if (breakpoint->set == 2)

  233. 		{

  234. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);

  235. 			jtag_execute_queue();

  236. 			arm7_9->wp1_used = 0;

  237. 		}

  238. 		breakpoint->set = 0;

  239. 	}

  240. 	else

  241. 	{

  242. 		/* restore original instruction (kept in target endianness) */

  243. 		if (breakpoint->length == 4)

  244. 		{

  245. 			target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);

  246. 		}

  247. 		else

  248. 		{

  249. 			target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);

  250. 		}

  251. 		breakpoint->set = 0;

  252. 	}

  253. 

  254. 	return ERROR_OK;

  255. }

  256. 

  257. int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)

  258. {

  259. 	armv4_5_common_t *armv4_5 = target->arch_info;

  260. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  261. 	

  262. 	if (target->state != TARGET_HALTED)

  263. 	{

  264. 		WARNING("target not halted");

  265. 		return ERROR_TARGET_NOT_HALTED;

  266. 	}

  267. 	

  268. 	if (arm7_9->force_hw_bkpts)

  269. 	{

  270. 		DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);

  271. 		breakpoint->type = BKPT_HARD;

  272. 	}

  273. 	

  274. 	if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))

  275. 	{

  276. 		INFO("sw breakpoint requested, but software breakpoints not enabled");

  277. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  278. 	}

  279. 	

  280. 	if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))

  281. 	{

  282. 		INFO("no watchpoint unit available for hardware breakpoint");

  283. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  284. 	}

  285. 	

  286. 	if ((breakpoint->length != 2) && (breakpoint->length != 4))

  287. 	{

  288. 		INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");

  289. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  290. 	}

  291. 	

  292. 	if (breakpoint->type == BKPT_HARD)

  293. 		arm7_9->wp_available--;

  294. 	

  295. 	return ERROR_OK;

  296. }

  297. 

  298. int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)

  299. {

  300. 	armv4_5_common_t *armv4_5 = target->arch_info;

  301. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  302. 	

  303. 	if (target->state != TARGET_HALTED)

  304. 	{

  305. 		WARNING("target not halted");

  306. 		return ERROR_TARGET_NOT_HALTED;

  307. 	}

  308. 	

  309. 	if (breakpoint->set)

  310. 	{

  311. 		arm7_9_unset_breakpoint(target, breakpoint);

  312. 	}

  313. 	

  314. 	if (breakpoint->type == BKPT_HARD)

  315. 		arm7_9->wp_available++;

  316. 	

  317. 	return ERROR_OK;

  318. }

  319. 

  320. int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)

  321. {

  322. 	armv4_5_common_t *armv4_5 = target->arch_info;

  323. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  324. 	int rw_mask = 1;

  325. 	u32 mask;

  326. 	

  327. 	mask = watchpoint->length - 1;

  328. 	

  329. 	if (target->state != TARGET_HALTED)

  330. 	{

  331. 		WARNING("target not halted");

  332. 		return ERROR_TARGET_NOT_HALTED;

  333. 	}

  334. 	

  335. 	if (watchpoint->rw == WPT_ACCESS)

  336. 		rw_mask = 0;

  337. 	else

  338. 		rw_mask = 1;

  339. 	

  340. 	if (!arm7_9->wp0_used)

  341. 	{

  342. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);

  343. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);

  344. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);

  345. 		if( watchpoint->mask != 0xffffffffu )

  346. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);

  347. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);

  348. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

  349. 

  350. 		jtag_execute_queue();

  351. 		watchpoint->set = 1;

  352. 		arm7_9->wp0_used = 2;

  353. 	}

  354. 	else if (!arm7_9->wp1_used)

  355. 	{

  356. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);

  357. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);

  358. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);

  359. 		if( watchpoint->mask != 0xffffffffu )

  360. 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);

  361. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);

  362. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

  363. 

  364. 		jtag_execute_queue();

  365. 		watchpoint->set = 2;

  366. 		arm7_9->wp1_used = 2;

  367. 	} 

  368. 	else

  369. 	{

  370. 		ERROR("BUG: no hardware comparator available");

  371. 		return ERROR_OK;

  372. 	}

  373. 	

  374. 	return ERROR_OK;

  375. }

  376. 

  377. int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)

  378. {

  379. 	armv4_5_common_t *armv4_5 = target->arch_info;

  380. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  381. 	

  382. 	if (target->state != TARGET_HALTED)

  383. 	{

  384. 		WARNING("target not halted");

  385. 		return ERROR_TARGET_NOT_HALTED;

  386. 	}

  387. 	

  388. 	if (!watchpoint->set)

  389. 	{

  390. 		WARNING("breakpoint not set");

  391. 		return ERROR_OK;

  392. 	}

  393. 	

  394. 	if (watchpoint->set == 1)

  395. 	{

  396. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);

  397. 		jtag_execute_queue();

  398. 		arm7_9->wp0_used = 0;

  399. 	}

  400. 	else if (watchpoint->set == 2)

  401. 	{

  402. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);

  403. 		jtag_execute_queue();

  404. 		arm7_9->wp1_used = 0;

  405. 	}

  406. 	watchpoint->set = 0;

  407. 

  408. 	return ERROR_OK;

  409. }

  410. 

  411. int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)

  412. {

  413. 	armv4_5_common_t *armv4_5 = target->arch_info;

  414. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  415. 	

  416. 	if (target->state != TARGET_HALTED)

  417. 	{

  418. 		WARNING("target not halted");

  419. 		return ERROR_TARGET_NOT_HALTED;

  420. 	}

  421. 	

  422. 	if (arm7_9->wp_available < 1)

  423. 	{

  424. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  425. 	}

  426. 	

  427. 	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))

  428. 	{

  429. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  430. 	}

  431. 	

  432. 	arm7_9->wp_available--;

  433. 		

  434. 	return ERROR_OK;

  435. }

  436. 

  437. int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)

  438. {

  439. 	armv4_5_common_t *armv4_5 = target->arch_info;

  440. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  441. 	

  442. 	if (target->state != TARGET_HALTED)

  443. 	{

  444. 		WARNING("target not halted");

  445. 		return ERROR_TARGET_NOT_HALTED;

  446. 	}

  447. 	

  448. 	if (watchpoint->set)

  449. 	{

  450. 		arm7_9_unset_watchpoint(target, watchpoint);

  451. 	}

  452. 		

  453. 	arm7_9->wp_available++;

  454. 	

  455. 	return ERROR_OK;

  456. }

  457. 

  458. int arm7_9_enable_sw_bkpts(struct target_s *target)

  459. {

  460. 	armv4_5_common_t *armv4_5 = target->arch_info;

  461. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  462. 	int retval;

  463. 	

  464. 	if (arm7_9->sw_bkpts_enabled)

  465. 		return ERROR_OK;

  466. 	

  467. 	if (arm7_9->wp_available < 1)

  468. 	{

  469. 		WARNING("can't enable sw breakpoints with no watchpoint unit available");

  470. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  471. 	}

  472. 	arm7_9->wp_available--;

  473. 	

  474. 	if (!arm7_9->wp0_used)

  475. 	{

  476. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);

  477. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);

  478. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);

  479. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);

  480. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

  481. 		arm7_9->sw_bkpts_enabled = 1;

  482. 		arm7_9->wp0_used = 3;

  483. 	}

  484. 	else if (!arm7_9->wp1_used)

  485. 	{

  486. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);

  487. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);

  488. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);

  489. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);

  490. 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

  491. 		arm7_9->sw_bkpts_enabled = 2;

  492. 		arm7_9->wp1_used = 3;

  493. 	}

  494. 	else

  495. 	{

  496. 		ERROR("BUG: both watchpoints used, but wp_available >= 1");

  497. 		exit(-1);

  498. 	}

  499. 	

  500. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  501. 	{

  502. 		ERROR("error writing EmbeddedICE registers to enable sw breakpoints");

  503. 		exit(-1);

  504. 	};

  505. 	

  506. 	return ERROR_OK;

  507. }

  508. 

  509. int arm7_9_disable_sw_bkpts(struct target_s *target)

  510. {

  511. 	armv4_5_common_t *armv4_5 = target->arch_info;

  512. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  513. 	

  514. 	if (!arm7_9->sw_bkpts_enabled)

  515. 		return ERROR_OK;

  516. 	

  517. 	if (arm7_9->sw_bkpts_enabled == 1)

  518. 	{

  519. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);

  520. 		arm7_9->sw_bkpts_enabled = 0;

  521. 		arm7_9->wp0_used = 0;

  522. 		arm7_9->wp_available++;

  523. 	}

  524. 	else if (arm7_9->sw_bkpts_enabled == 2)

  525. 	{

  526. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);

  527. 		arm7_9->sw_bkpts_enabled = 0;

  528. 		arm7_9->wp1_used = 0;

  529. 		arm7_9->wp_available++;

  530. 	}

  531. 

  532. 	return ERROR_OK;

  533. }

  534. 

  535. int arm7_9_execute_sys_speed(struct target_s *target)

  536. {

  537. 	int timeout;

  538. 	int retval;

  539. 	

  540. 	armv4_5_common_t *armv4_5 = target->arch_info;

  541. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  542. 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;

  543. 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

  544. 				

  545. 	/* set RESTART instruction */

  546. 	jtag_add_end_state(TAP_RTI);

  547. 	arm_jtag_set_instr(jtag_info, 0x4, NULL);

  548. 	

  549. 	for (timeout=0; timeout<50; timeout++)

  550. 	{

  551. 		/* read debug status register */

  552. 		embeddedice_read_reg(dbg_stat);

  553. 		if ((retval = jtag_execute_queue()) != ERROR_OK)

  554. 			return retval;

  555. 		if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))

  556. 				   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))

  557. 			break;

  558. 		usleep(100000);	

  559. 	}

  560. 	if (timeout == 50)

  561. 	{

  562. 		ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));

  563. 		return ERROR_TARGET_TIMEOUT;

  564. 	}

  565. 	

  566. 	return ERROR_OK;

  567. }

  568. 

  569. int arm7_9_execute_fast_sys_speed(struct target_s *target)

  570. {

  571. 	u8 check_value[4], check_mask[4];

  572. 	

  573. 	armv4_5_common_t *armv4_5 = target->arch_info;

  574. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  575. 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;

  576. 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

  577. 				

  578. 	/* set RESTART instruction */

  579. 	jtag_add_end_state(TAP_RTI);

  580. 	arm_jtag_set_instr(jtag_info, 0x4, NULL);

  581. 	

  582. 	/* check for DBGACK and SYSCOMP set (others don't care) */

  583. 	buf_set_u32(check_value, 0, 32, 0x9);

  584. 	buf_set_u32(check_mask, 0, 32, 0x9);

  585. 	

  586. 	/* read debug status register */

  587. 	embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);

  588. 

  589. 	return ERROR_OK;

  590. }

  591. 

  592. enum target_state arm7_9_poll(target_t *target)

  593. {

  594. 	int retval;

  595. 	armv4_5_common_t *armv4_5 = target->arch_info;

  596. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  597. 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

  598. 

  599. 	if (arm7_9->reinit_embeddedice)

  600. 	{

  601. 		arm7_9_reinit_embeddedice(target);

  602. 	}

  603. 	

  604. 	/* read debug status register */

  605. 	embeddedice_read_reg(dbg_stat);

  606. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  607. 	{

  608. 		switch (retval)

  609. 		{

  610. 			case ERROR_JTAG_QUEUE_FAILED:

  611. 				ERROR("JTAG queue failed while reading EmbeddedICE status register");

  612. 				exit(-1);

  613. 				break;

  614. 			default:

  615. 				break;

  616. 		}

  617. 	}

  618. 	

  619. 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))

  620. 	{

  621. 		DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));

  622. 		if ((target->state == TARGET_UNKNOWN))

  623. 		{

  624. 			WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");

  625. 			target->state = TARGET_RUNNING;

  626. 		}

  627. 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))

  628. 		{

  629. 			target->state = TARGET_HALTED;

  630. 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)

  631. 				return retval;

  632. 			

  633. 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  634. 		}

  635. 		if (target->state == TARGET_DEBUG_RUNNING)

  636. 		{

  637. 			target->state = TARGET_HALTED;

  638. 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)

  639. 				return retval;

  640. 			

  641. 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);

  642. 		}

  643. 	}

  644. 	else

  645. 	{

  646. 		if (target->state != TARGET_DEBUG_RUNNING)

  647. 			target->state = TARGET_RUNNING;

  648. 	}

  649. 	

  650. 	return target->state;

  651. }

  652. 

  653. int arm7_9_assert_reset(target_t *target)

  654. {

  655. 	int retval;

  656. 	

  657. 	DEBUG("target->state: %s", target_state_strings[target->state]);

  658. 	

  659. 	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)

  660. 	{

  661. 		/* if the target wasn't running, there might be working areas allocated */

  662. 		target_free_all_working_areas(target);

  663. 		

  664. 		/* assert SRST and TRST */

  665. 		/* system would get ouf sync if we didn't reset test-logic, too */

  666. 		if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)

  667. 		{

  668. 			if (retval == ERROR_JTAG_RESET_CANT_SRST)

  669. 			{

  670. 				WARNING("can't assert srst");

  671. 				return retval;

  672. 			}

  673. 			else

  674. 			{

  675. 				ERROR("unknown error");

  676. 				exit(-1);

  677. 			}

  678. 		}

  679. 		jtag_add_sleep(5000);

  680. 		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)

  681. 		{

  682. 			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)

  683. 			{

  684. 				WARNING("srst resets test logic, too");

  685. 				retval = jtag_add_reset(1, 1);

  686. 			}

  687. 		}

  688. 	}

  689. 	else

  690. 	{

  691. 		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)

  692. 		{

  693. 			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)

  694. 			{

  695. 				WARNING("srst resets test logic, too");

  696. 				retval = jtag_add_reset(1, 1);

  697. 			}

  698. 			

  699. 			if (retval == ERROR_JTAG_RESET_CANT_SRST)

  700. 			{

  701. 				WARNING("can't assert srst");

  702. 				return retval;

  703. 			}

  704. 			else if (retval != ERROR_OK)

  705. 			{

  706. 				ERROR("unknown error");

  707. 				exit(-1);

  708. 			}

  709. 		}

  710. 	}

  711. 	

  712. 	target->state = TARGET_RESET;

  713. 	jtag_add_sleep(50000);

  714. 	

  715. 	armv4_5_invalidate_core_regs(target);

  716. 

  717. 	return ERROR_OK;

  718. 

  719. }

  720. 

  721. int arm7_9_deassert_reset(target_t *target)

  722. {

  723. 	DEBUG("target->state: %s", target_state_strings[target->state]);

  724. 	

  725. 	/* deassert reset lines */

  726. 	jtag_add_reset(0, 0);

  727. 	

  728. 	return ERROR_OK;

  729. }

  730. 

  731. int arm7_9_clear_halt(target_t *target)

  732. {

  733. 	armv4_5_common_t *armv4_5 = target->arch_info;

  734. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  735. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  736. 	

  737. 	/* we used DBGRQ only if we didn't come out of reset */

  738. 	if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)

  739. 	{

  740. 		/* program EmbeddedICE Debug Control Register to deassert DBGRQ

  741. 		 */

  742. 		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	

  743. 		embeddedice_store_reg(dbg_ctrl);

  744. 	}

  745. 	else

  746. 	{

  747. 		if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)

  748. 		{

  749. 			/* if we came out of reset, and vector catch is supported, we used

  750. 			 * vector catch to enter debug state

  751. 			 * restore the register in that case

  752. 			 */

  753. 			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);

  754. 		}

  755. 		else

  756. 		{

  757. 			/* restore registers if watchpoint unit 0 was in use

  758. 			 */

  759. 			if (arm7_9->wp0_used)

  760. 			{

  761. 				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);

  762. 				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);

  763. 				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);

  764. 			}

  765. 			/* control value always has to be restored, as it was either disabled, 

  766. 			 * or enabled with possibly different bits

  767. 			 */

  768. 			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);

  769. 		}

  770. 	}

  771. 	

  772. 	return ERROR_OK;

  773. }

  774. 

  775. int arm7_9_soft_reset_halt(struct target_s *target)

  776. {

  777. 	armv4_5_common_t *armv4_5 = target->arch_info;

  778. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  779. 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

  780. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  781. 	int i;

  782. 	

  783. 	if (target->state == TARGET_RUNNING)

  784. 	{

  785. 		target->type->halt(target);

  786. 	}

  787. 	

  788. 	while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)

  789. 	{

  790. 		embeddedice_read_reg(dbg_stat);

  791. 		jtag_execute_queue();

  792. 	}

  793. 	target->state = TARGET_HALTED;

  794. 	

  795. 	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS

  796. 	 * ensure that DBGRQ is cleared

  797. 	 */

  798. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);

  799. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);

  800. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);

  801. 	embeddedice_store_reg(dbg_ctrl);

  802. 	

  803. 	arm7_9_clear_halt(target);

  804. 	

  805. 	/* if the target is in Thumb state, change to ARM state */

  806. 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))

  807. 	{

  808. 		u32 r0_thumb, pc_thumb;

  809. 		DEBUG("target entered debug from Thumb state, changing to ARM");

  810. 		/* Entered debug from Thumb mode */

  811. 		armv4_5->core_state = ARMV4_5_STATE_THUMB;

  812. 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);

  813. 	}

  814. 	

  815. 	/* all register content is now invalid */

  816. 	armv4_5_invalidate_core_regs(target);

  817. 	

  818. 	/* SVC, ARM state, IRQ and FIQ disabled */

  819. 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);

  820. 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;

  821. 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;

  822. 	

  823. 	/* start fetching from 0x0 */

  824. 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);

  825. 	armv4_5->core_cache->reg_list[15].dirty = 1;

  826. 	armv4_5->core_cache->reg_list[15].valid = 1;

  827. 	

  828. 	armv4_5->core_mode = ARMV4_5_MODE_SVC;

  829. 	armv4_5->core_state = ARMV4_5_STATE_ARM;

  830. 	

  831. 	/* reset registers */

  832. 	for (i = 0; i <= 14; i++)

  833. 	{	

  834. 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);

  835. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;

  836. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;

  837. 	}

  838. 	

  839. 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  840. 	

  841. 	return ERROR_OK;

  842. }

  843. 

  844. int arm7_9_prepare_reset_halt(target_t *target)

  845. {

  846. 	armv4_5_common_t *armv4_5 = target->arch_info;

  847. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  848. 	

  849. 	if (arm7_9->has_vector_catch)

  850. 	{

  851. 		/* program vector catch register to catch reset vector */

  852. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);

  853. 	}

  854. 	else

  855. 	{

  856. 		/* program watchpoint unit to match on reset vector address */

  857. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);

  858. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);

  859. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);

  860. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);

  861. 	}

  862. 	

  863. 	return ERROR_OK;

  864. }

  865. 

  866. int arm7_9_halt(target_t *target)

  867. {

  868. 	armv4_5_common_t *armv4_5 = target->arch_info;

  869. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  870. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  871. 	

  872. 	DEBUG("target->state: %s", target_state_strings[target->state]);

  873. 	

  874. 	if (target->state == TARGET_HALTED)

  875. 	{

  876. 		WARNING("target was already halted");

  877. 		return ERROR_TARGET_ALREADY_HALTED;

  878. 	}

  879. 	

  880. 	if (target->state == TARGET_UNKNOWN)

  881. 	{

  882. 		WARNING("target was in unknown state when halt was requested");

  883. 	}

  884. 	

  885. 	if (target->state == TARGET_RESET) 

  886. 	{

  887. 		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)

  888. 		{

  889. 			ERROR("can't request a halt while in reset if nSRST pulls nTRST");

  890. 			return ERROR_TARGET_FAILURE;

  891. 		}

  892. 		else

  893. 		{

  894. 			/* we came here in a reset_halt or reset_init sequence

  895. 			 * debug entry was already prepared in arm7_9_prepare_reset_halt()

  896. 			 */

  897. 			target->debug_reason = DBG_REASON_DBGRQ;

  898. 			

  899. 			return ERROR_OK; 

  900. 		}

  901. 	}

  902. 

  903. 	if (arm7_9->use_dbgrq)

  904. 	{

  905. 		/* program EmbeddedICE Debug Control Register to assert DBGRQ

  906. 		 */

  907. 		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);	

  908. 		embeddedice_store_reg(dbg_ctrl);

  909. 	}

  910. 	else

  911. 	{

  912. 		/* program watchpoint unit to match on any address

  913. 		 */

  914. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);

  915. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);

  916. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);

  917. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);

  918. 	}

  919. 

  920. 	target->debug_reason = DBG_REASON_DBGRQ;

  921. 	

  922. 	return ERROR_OK;

  923. }

  924. 

  925. int arm7_9_debug_entry(target_t *target)

  926. {

  927. 	int i;

  928. 	u32 context[16];

  929. 	u32* context_p[16];

  930. 	u32 r0_thumb, pc_thumb;

  931. 	u32 cpsr;

  932. 	int retval;

  933. 	/* get pointers to arch-specific information */

  934. 	armv4_5_common_t *armv4_5 = target->arch_info;

  935. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  936. 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

  937. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  938. 

  939. #ifdef _DEBUG_ARM7_9_

  940. 	DEBUG("-");

  941. #endif

  942. 

  943. 	if (arm7_9->pre_debug_entry)

  944. 		arm7_9->pre_debug_entry(target);

  945. 

  946. 	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS

  947. 	 * ensure that DBGRQ is cleared

  948. 	 */

  949. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);

  950. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);

  951. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);

  952. 	embeddedice_store_reg(dbg_ctrl);

  953. 	

  954. 	arm7_9_clear_halt(target);

  955. 	

  956. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  957. 	{

  958. 		switch (retval)

  959. 		{

  960. 			case ERROR_JTAG_QUEUE_FAILED:

  961. 				ERROR("JTAG queue failed while writing EmbeddedICE control register");

  962. 				exit(-1);

  963. 				break;

  964. 			default:

  965. 				break;

  966. 		}

  967. 	}

  968. 

  969. 	if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)

  970. 		return retval;

  971. 

  972. 

  973. 	if (target->state != TARGET_HALTED)

  974. 	{

  975. 		WARNING("target not halted");

  976. 		return ERROR_TARGET_NOT_HALTED;

  977. 	}

  978. 	

  979. 	/* if the target is in Thumb state, change to ARM state */

  980. 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))

  981. 	{

  982. 		DEBUG("target entered debug from Thumb state");

  983. 		/* Entered debug from Thumb mode */

  984. 		armv4_5->core_state = ARMV4_5_STATE_THUMB;

  985. 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);

  986. 		DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);

  987. 	}

  988. 	else

  989. 	{

  990. 		DEBUG("target entered debug from ARM state");

  991. 		/* Entered debug from ARM mode */

  992. 		armv4_5->core_state = ARMV4_5_STATE_ARM;

  993. 	}

  994. 	

  995. 	for (i = 0; i < 16; i++)

  996. 		context_p[i] = &context[i];

  997. 	/* save core registers (r0 - r15 of current core mode) */

  998. 	arm7_9->read_core_regs(target, 0xffff, context_p);

  999. 

  1000. 	arm7_9->read_xpsr(target, &cpsr, 0);

  1001. 	

  1002. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  1003. 		return retval;

  1004. 	

  1005. 	/* if the core has been executing in Thumb state, set the T bit */

  1006. 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)

  1007. 		cpsr |= 0x20;	

  1008. 	

  1009. 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);

  1010. 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;

  1011. 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;

  1012. 	

  1013. 	armv4_5->core_mode = cpsr & 0x1f;

  1014. 	

  1015. 	if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)

  1016. 	{

  1017. 		target->state = TARGET_UNKNOWN;

  1018. 		ERROR("cpsr contains invalid mode value - communication failure");

  1019. 		return ERROR_TARGET_FAILURE;

  1020. 	}

  1021. 

  1022. 	DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);

  1023. 	

  1024. 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)

  1025. 	{

  1026. 		DEBUG("thumb state, applying fixups");

  1027. 		context[0] = r0_thumb;

  1028. 		context[15] = pc_thumb;

  1029. 	} else if (armv4_5->core_state == ARMV4_5_STATE_ARM)

  1030. 	{

  1031. 		/* adjust value stored by STM */

  1032. 		context[15] -= 3 * 4;

  1033. 	}

  1034. 

  1035. 	if ((target->debug_reason == DBG_REASON_BREAKPOINT)

  1036. 			|| (target->debug_reason == DBG_REASON_SINGLESTEP)

  1037. 			|| (target->debug_reason == DBG_REASON_WATCHPOINT)

  1038. 			|| (target->debug_reason == DBG_REASON_WPTANDBKPT)

  1039. 			|| ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))

  1040. 		context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);

  1041. 	else if (target->debug_reason == DBG_REASON_DBGRQ)

  1042. 		context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);

  1043. 	else

  1044. 	{

  1045. 		ERROR("unknown debug reason: %i", target->debug_reason);

  1046. 	}

  1047. 

  1048. 	

  1049. 	for (i=0; i<=15; i++)

  1050. 	{

  1051. 		DEBUG("r%i: 0x%8.8x", i, context[i]);

  1052. 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);

  1053. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;

  1054. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;

  1055. 	}

  1056. 	

  1057. 	DEBUG("entered debug state at PC 0x%x", context[15]);

  1058. 

  1059. 	/* exceptions other than USR & SYS have a saved program status register */

  1060. 	if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))

  1061. 	{

  1062. 		u32 spsr;

  1063. 		arm7_9->read_xpsr(target, &spsr, 1);

  1064. 		jtag_execute_queue();

  1065. 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);

  1066. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;

  1067. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;

  1068. 	}

  1069. 

  1070. 	/* r0 and r15 (pc) have to be restored later */

  1071. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;

  1072. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;

  1073. 

  1074. 	if ((retval = jtag->execute_queue()) != ERROR_OK)

  1075. 		return retval;

  1076. 

  1077. 	if (arm7_9->post_debug_entry)

  1078. 		arm7_9->post_debug_entry(target);

  1079. 

  1080. 	return ERROR_OK;

  1081. }

  1082. 

  1083. int arm7_9_full_context(target_t *target)

  1084. {

  1085. 	int i;

  1086. 	int retval;

  1087. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1088. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1089. 

  1090. 	DEBUG("-");

  1091. 	

  1092. 	if (target->state != TARGET_HALTED)

  1093. 	{

  1094. 		WARNING("target not halted");

  1095. 		return ERROR_TARGET_NOT_HALTED;

  1096. 	}

  1097. 

  1098. 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)

  1099. 	 * SYS shares registers with User, so we don't touch SYS

  1100. 	 */

  1101. 	for(i = 0; i < 6; i++)

  1102. 	{

  1103. 		u32 mask = 0;

  1104. 		u32* reg_p[16];

  1105. 		int j;

  1106. 		int valid = 1;

  1107. 		

  1108. 		/* check if there are invalid registers in the current mode 

  1109. 		 */

  1110. 		for (j = 0; j <= 16; j++)

  1111. 		{

  1112. 			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)

  1113. 				valid = 0;

  1114. 		}

  1115. 		

  1116. 		if (!valid)

  1117. 		{

  1118. 			u32 tmp_cpsr;

  1119. 			

  1120. 			/* change processor mode (and mask T bit) */

  1121. 			tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;

  1122. 			tmp_cpsr |= armv4_5_number_to_mode(i);

  1123. 			tmp_cpsr &= ~0x20;

  1124. 			arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);

  1125. 

  1126. 			for (j = 0; j < 15; j++)

  1127. 			{

  1128. 				if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)

  1129. 				{	

  1130. 					reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;

  1131. 					mask |= 1 << j;

  1132. 					ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;

  1133. 					ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;

  1134. 				}

  1135. 			}

  1136. 			

  1137. 			/* if only the PSR is invalid, mask is all zeroes */

  1138. 			if (mask)

  1139. 				arm7_9->read_core_regs(target, mask, reg_p);

  1140. 			

  1141. 			/* check if the PSR has to be read */

  1142. 			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)

  1143. 			{

  1144. 				arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);

  1145. 				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;

  1146. 				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;

  1147. 			}

  1148. 		}

  1149. 	}

  1150. 

  1151. 	/* restore processor mode (mask T bit) */

  1152. 	arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);

  1153. 	

  1154. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  1155. 	{

  1156. 		ERROR("JTAG failure");

  1157. 		exit(-1);

  1158. 	}

  1159. 	return ERROR_OK;

  1160. }

  1161. 

  1162. int arm7_9_restore_context(target_t *target)

  1163. {

  1164. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1165. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1166. 	reg_t *reg; 

  1167. 	armv4_5_core_reg_t *reg_arch_info;

  1168. 	enum armv4_5_mode current_mode = armv4_5->core_mode;

  1169. 	int i, j;

  1170. 	int dirty;

  1171. 	int mode_change;

  1172. 	

  1173. 	DEBUG("-");

  1174. 	

  1175. 	if (target->state != TARGET_HALTED)

  1176. 	{

  1177. 		WARNING("target not halted");

  1178. 		return ERROR_TARGET_NOT_HALTED;

  1179. 	}

  1180. 	

  1181. 	if (arm7_9->pre_restore_context)

  1182. 		arm7_9->pre_restore_context(target);

  1183. 	

  1184. 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)

  1185. 	 * SYS shares registers with User, so we don't touch SYS

  1186. 	 */

  1187. 	for (i = 0; i < 6; i++)

  1188. 	{

  1189. 		DEBUG("examining %s mode", armv4_5_mode_strings[i]);

  1190. 		dirty = 0;

  1191. 		mode_change = 0;

  1192. 		/* check if there are dirty registers in the current mode 

  1193. 		*/

  1194. 		for (j = 0; j <= 16; j++)

  1195. 		{

  1196. 			reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);

  1197. 			reg_arch_info = reg->arch_info;

  1198. 			if (reg->dirty == 1)

  1199. 			{

  1200. 				if (reg->valid == 1)

  1201. 				{

  1202. 					dirty = 1;

  1203. 					DEBUG("examining dirty reg: %s", reg->name);

  1204. 					if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)

  1205. 						&& (reg_arch_info->mode != current_mode)

  1206. 						&& !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS)) 

  1207. 						&& !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))

  1208. 					{

  1209. 						mode_change = 1;

  1210. 						DEBUG("require mode change");

  1211. 					}

  1212. 				}

  1213. 				else

  1214. 				{

  1215. 					ERROR("BUG: dirty register '%s', but no valid data", reg->name);

  1216. 					exit(-1);

  1217. 				}

  1218. 			}

  1219. 		}

  1220. 		

  1221. 		if (dirty)

  1222. 		{

  1223. 			u32 mask = 0x0;

  1224. 			int num_regs = 0;

  1225. 			u32 regs[16];

  1226. 

  1227. 			if (mode_change)

  1228. 			{

  1229. 				u32 tmp_cpsr;

  1230. 			

  1231. 				/* change processor mode (mask T bit) */

  1232. 				tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;

  1233. 				tmp_cpsr |= armv4_5_number_to_mode(i);

  1234. 				tmp_cpsr &= ~0x20;

  1235. 				arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);

  1236. 				current_mode = armv4_5_number_to_mode(i);

  1237. 			}

  1238. 			

  1239. 			for (j = 0; j <= 14; j++)

  1240. 			{

  1241. 				reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);

  1242. 				reg_arch_info = reg->arch_info;

  1243. 				

  1244. 				

  1245. 				if (reg->dirty == 1)

  1246. 				{

  1247. 					regs[j] = buf_get_u32(reg->value, 0, 32);

  1248. 					mask |= 1 << j;

  1249. 					num_regs++;

  1250. 					reg->dirty = 0;

  1251. 					reg->valid = 1;

  1252. 					DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);

  1253. 				}

  1254. 			}

  1255. 			

  1256. 			if (mask)

  1257. 			{

  1258. 				arm7_9->write_core_regs(target, mask, regs);

  1259. 			}

  1260. 			

  1261. 			reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);

  1262. 			reg_arch_info = reg->arch_info;

  1263. 			if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))

  1264. 			{

  1265. 				DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));

  1266. 				arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);

  1267. 			}

  1268. 		}

  1269. 	}

  1270. 	

  1271. 	if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))

  1272. 	{

  1273. 		/* restore processor mode (mask T bit) */

  1274. 		u32 tmp_cpsr;

  1275. 			

  1276. 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;

  1277. 		tmp_cpsr |= armv4_5_number_to_mode(i);

  1278. 		tmp_cpsr &= ~0x20;

  1279. 		DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);

  1280. 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);

  1281. 	}

  1282. 	else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)

  1283. 	{

  1284. 		/* CPSR has been changed, full restore necessary (mask T bit) */

  1285. 		DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));

  1286. 		arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);

  1287. 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;

  1288. 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;

  1289. 	}

  1290. 	

  1291. 	/* restore PC */

  1292. 	DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

  1293. 	arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

  1294. 	armv4_5->core_cache->reg_list[15].dirty = 0;

  1295. 			

  1296. 	if (arm7_9->post_restore_context)

  1297. 		arm7_9->post_restore_context(target);

  1298. 

  1299. 	return ERROR_OK;

  1300. }

  1301. 

  1302. int arm7_9_restart_core(struct target_s *target)

  1303. {

  1304. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1305. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1306. 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;

  1307. 	

  1308. 	/* set RESTART instruction */

  1309. 	jtag_add_end_state(TAP_RTI);

  1310. 	arm_jtag_set_instr(jtag_info, 0x4, NULL);

  1311. 	

  1312. 	jtag_add_runtest(1, TAP_RTI);

  1313. 	if ((jtag_execute_queue()) != ERROR_OK)

  1314. 	{

  1315. 		exit(-1);

  1316. 	}

  1317. 	

  1318. 	return ERROR_OK;

  1319. }

  1320. 

  1321. void arm7_9_enable_watchpoints(struct target_s *target)

  1322. {

  1323. 	watchpoint_t *watchpoint = target->watchpoints;

  1324. 	

  1325. 	while (watchpoint)

  1326. 	{

  1327. 		if (watchpoint->set == 0)

  1328. 			arm7_9_set_watchpoint(target, watchpoint);

  1329. 		watchpoint = watchpoint->next;

  1330. 	}

  1331. }

  1332. 

  1333. void arm7_9_enable_breakpoints(struct target_s *target)

  1334. {

  1335. 	breakpoint_t *breakpoint = target->breakpoints;

  1336. 	

  1337. 	/* set any pending breakpoints */

  1338. 	while (breakpoint)

  1339. 	{

  1340. 		if (breakpoint->set == 0)

  1341. 			arm7_9_set_breakpoint(target, breakpoint);

  1342. 		breakpoint = breakpoint->next;

  1343. 	}

  1344. }

  1345. 

  1346. void arm7_9_disable_bkpts_and_wpts(struct target_s *target)

  1347. {

  1348. 	breakpoint_t *breakpoint = target->breakpoints;

  1349. 	watchpoint_t *watchpoint = target->watchpoints;

  1350. 

  1351. 	/* set any pending breakpoints */

  1352. 	while (breakpoint)

  1353. 	{

  1354. 		if (breakpoint->set != 0)

  1355. 			arm7_9_unset_breakpoint(target, breakpoint);

  1356. 		breakpoint = breakpoint->next;

  1357. 	}

  1358. 	

  1359. 	while (watchpoint)

  1360. 	{

  1361. 		if (watchpoint->set != 0)

  1362. 			arm7_9_unset_watchpoint(target, watchpoint);

  1363. 		watchpoint = watchpoint->next;

  1364. 	}

  1365. }

  1366. 

  1367. int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)

  1368. {

  1369. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1370. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1371. 	breakpoint_t *breakpoint = target->breakpoints;

  1372. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  1373. 	

  1374. 	DEBUG("-");

  1375. 	

  1376. 	if (target->state != TARGET_HALTED)

  1377. 	{

  1378. 		WARNING("target not halted");

  1379. 		return ERROR_TARGET_NOT_HALTED;

  1380. 	}

  1381. 	

  1382. 	if (!debug_execution)

  1383. 	{

  1384. 		target_free_all_working_areas(target);

  1385. 	}

  1386. 	

  1387. 	/* current = 1: continue on current pc, otherwise continue at <address> */

  1388. 	if (!current)

  1389. 		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);

  1390. 	

  1391. 	/* the front-end may request us not to handle breakpoints */

  1392. 	if (handle_breakpoints)

  1393. 	{

  1394. 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))

  1395. 		{

  1396. 			DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);

  1397. 			arm7_9_unset_breakpoint(target, breakpoint);

  1398. 			

  1399. 			DEBUG("enable single-step");

  1400. 			arm7_9->enable_single_step(target);

  1401. 			

  1402. 			target->debug_reason = DBG_REASON_SINGLESTEP;

  1403. 

  1404. 			arm7_9_restore_context(target);

  1405. 			

  1406. 			if (armv4_5->core_state == ARMV4_5_STATE_ARM)

  1407. 				arm7_9->branch_resume(target);

  1408. 			else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)

  1409. 			{

  1410. 				arm7_9->branch_resume_thumb(target);

  1411. 			}

  1412. 			else

  1413. 			{

  1414. 				ERROR("unhandled core state");

  1415. 				exit(-1);

  1416. 			}

  1417. 				

  1418. 			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);

  1419. 			embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));

  1420. 			arm7_9_execute_sys_speed(target);

  1421. 			

  1422. 			DEBUG("disable single-step");

  1423. 			arm7_9->disable_single_step(target);

  1424. 			

  1425. 			arm7_9_debug_entry(target);

  1426. 			DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

  1427. 		

  1428. 			DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);

  1429. 			arm7_9_set_breakpoint(target, breakpoint);

  1430. 		}

  1431. 	}

  1432. 	

  1433. 	/* enable any pending breakpoints and watchpoints */

  1434. 	arm7_9_enable_breakpoints(target);

  1435. 	arm7_9_enable_watchpoints(target);

  1436. 	

  1437. 	arm7_9_restore_context(target);

  1438. 	

  1439. 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)

  1440. 	{

  1441. 		arm7_9->branch_resume(target);

  1442. 	}

  1443. 	else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)

  1444. 	{

  1445. 		arm7_9->branch_resume_thumb(target);

  1446. 	}

  1447. 	else

  1448. 	{

  1449. 		ERROR("unhandled core state");

  1450. 		exit(-1);

  1451. 	}

  1452. 	

  1453. 	/* deassert DBGACK and INTDIS */

  1454. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);

  1455. 	/* INTDIS only when we really resume, not during debug execution */

  1456. 	if (!debug_execution)

  1457. 		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);

  1458. 	embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));

  1459. 	

  1460. 	arm7_9_restart_core(target);

  1461. 	

  1462. 	target->debug_reason = DBG_REASON_NOTHALTED;

  1463. 	

  1464. 	if (!debug_execution)

  1465. 	{

  1466. 		/* registers are now invalid */

  1467. 		armv4_5_invalidate_core_regs(target);

  1468. 		target->state = TARGET_RUNNING;

  1469. 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);

  1470. 	}

  1471. 	else

  1472. 	{

  1473. 		target->state = TARGET_DEBUG_RUNNING;

  1474. 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);

  1475. 	}

  1476. 	

  1477. 	DEBUG("target resumed");

  1478. 	

  1479. 	return ERROR_OK;

  1480. }

  1481. 

  1482. void arm7_9_enable_eice_step(target_t *target)

  1483. {

  1484. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1485. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1486. 	

  1487. 	/* setup an inverse breakpoint on the current PC

  1488. 	* - comparator 1 matches the current address

  1489. 	* - rangeout from comparator 1 is connected to comparator 0 rangein

  1490. 	* - comparator 0 matches any address, as long as rangein is low */

  1491. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);

  1492. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);

  1493. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);

  1494. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);

  1495. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

  1496. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);

  1497. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);

  1498. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);

  1499. 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);

  1500. }

  1501. 

  1502. void arm7_9_disable_eice_step(target_t *target)

  1503. {

  1504. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1505. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1506. 

  1507. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);

  1508. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);

  1509. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);

  1510. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);

  1511. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);

  1512. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);

  1513. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);

  1514. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);

  1515. 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);

  1516. }

  1517. 

  1518. int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)

  1519. {

  1520. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1521. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1522. 	breakpoint_t *breakpoint = NULL;

  1523. 

  1524. 	if (target->state != TARGET_HALTED)

  1525. 	{

  1526. 		WARNING("target not halted");

  1527. 		return ERROR_TARGET_NOT_HALTED;

  1528. 	}

  1529. 	

  1530. 	/* current = 1: continue on current pc, otherwise continue at <address> */

  1531. 	if (!current)

  1532. 		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);

  1533. 	

  1534. 	/* the front-end may request us not to handle breakpoints */

  1535. 	if (handle_breakpoints)

  1536. 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))

  1537. 			arm7_9_unset_breakpoint(target, breakpoint);

  1538. 	

  1539. 	target->debug_reason = DBG_REASON_SINGLESTEP;

  1540. 

  1541. 	arm7_9_restore_context(target);

  1542. 	

  1543. 	arm7_9->enable_single_step(target);

  1544. 	

  1545. 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)

  1546. 	{

  1547. 		arm7_9->branch_resume(target);

  1548. 	}

  1549. 	else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)

  1550. 	{

  1551. 		arm7_9->branch_resume_thumb(target);

  1552. 	}

  1553. 	else

  1554. 	{

  1555. 		ERROR("unhandled core state");

  1556. 		exit(-1);

  1557. 	}

  1558. 	

  1559. 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);

  1560. 

  1561. 	arm7_9_execute_sys_speed(target);

  1562. 	arm7_9->disable_single_step(target);

  1563. 	

  1564. 	/* registers are now invalid */

  1565. 	armv4_5_invalidate_core_regs(target);

  1566. 	

  1567. 	arm7_9_debug_entry(target);

  1568. 	

  1569. 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  1570. 

  1571. 	if (breakpoint)

  1572. 		arm7_9_set_breakpoint(target, breakpoint);

  1573. 	

  1574. 	DEBUG("target stepped");

  1575. 

  1576. 	return ERROR_OK;

  1577. 

  1578. }

  1579. 

  1580. int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)

  1581. {

  1582. 	u32* reg_p[16];

  1583. 	u32 value;

  1584. 	int retval;

  1585. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1586. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1587. 	enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;

  1588. 	

  1589. 	if ((num < 0) || (num > 16))

  1590. 		return ERROR_INVALID_ARGUMENTS;

  1591. 	

  1592. 	if ((mode != ARMV4_5_MODE_ANY)

  1593. 			&& (mode != armv4_5->core_mode)

  1594. 			&& (reg_mode != ARMV4_5_MODE_ANY))

  1595. 	{

  1596. 		u32 tmp_cpsr;

  1597. 			

  1598. 		/* change processor mode (mask T bit) */

  1599. 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;

  1600. 		tmp_cpsr |= mode;

  1601. 		tmp_cpsr &= ~0x20;

  1602. 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);

  1603. 	}

  1604. 	

  1605. 	if ((num >= 0) && (num <= 15))

  1606. 	{

  1607. 		/* read a normal core register */

  1608. 		reg_p[num] = &value;

  1609. 		

  1610. 		arm7_9->read_core_regs(target, 1 << num, reg_p);

  1611. 	}

  1612. 	else

  1613. 	{

  1614. 		/* read a program status register

  1615. 		 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr

  1616. 		 */

  1617. 		armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;

  1618. 		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;

  1619. 		

  1620. 		arm7_9->read_xpsr(target, &value, spsr);

  1621. 	}

  1622. 	

  1623. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  1624. 	{

  1625. 		ERROR("JTAG failure");

  1626. 		exit(-1);

  1627. 	}

  1628. 		

  1629. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;

  1630. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;

  1631. 	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);

  1632. 		

  1633. 	if ((mode != ARMV4_5_MODE_ANY)

  1634. 			&& (mode != armv4_5->core_mode)

  1635. 			&& (reg_mode != ARMV4_5_MODE_ANY))	{

  1636. 		/* restore processor mode (mask T bit) */

  1637. 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);

  1638. 	}

  1639. 	

  1640. 	return ERROR_OK;

  1641. 	

  1642. }

  1643. 

  1644. int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)

  1645. {

  1646. 	u32 reg[16];

  1647. 	int retval;

  1648. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1649. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1650. 	enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;

  1651. 

  1652. 	if ((num < 0) || (num > 16))

  1653. 		return ERROR_INVALID_ARGUMENTS;

  1654. 	

  1655. 	if ((mode != ARMV4_5_MODE_ANY)

  1656. 			&& (mode != armv4_5->core_mode)

  1657. 			&& (reg_mode != ARMV4_5_MODE_ANY))	{

  1658. 		u32 tmp_cpsr;

  1659. 			

  1660. 		/* change processor mode (mask T bit) */

  1661. 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;

  1662. 		tmp_cpsr |= mode;

  1663. 		tmp_cpsr &= ~0x20;

  1664. 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);

  1665. 	}

  1666. 	

  1667. 	if ((num >= 0) && (num <= 15))

  1668. 	{

  1669. 		/* write a normal core register */

  1670. 		reg[num] = value;

  1671. 		

  1672. 		arm7_9->write_core_regs(target, 1 << num, reg);

  1673. 	}

  1674. 	else

  1675. 	{

  1676. 		/* write a program status register

  1677. 		* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr

  1678. 		*/

  1679. 		armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;

  1680. 		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;

  1681. 		

  1682. 		/* if we're writing the CPSR, mask the T bit */

  1683. 		if (!spsr)

  1684. 			value &= ~0x20;

  1685. 		

  1686. 		arm7_9->write_xpsr(target, value, spsr);

  1687. 	}

  1688. 	

  1689. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;

  1690. 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;

  1691. 		

  1692. 	if ((mode != ARMV4_5_MODE_ANY)

  1693. 			&& (mode != armv4_5->core_mode)

  1694. 			&& (reg_mode != ARMV4_5_MODE_ANY))	{

  1695. 		/* restore processor mode (mask T bit) */

  1696. 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);

  1697. 	}

  1698. 	

  1699. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  1700. 	{

  1701. 		ERROR("JTAG failure");

  1702. 		exit(-1);

  1703. 	}

  1704. 	

  1705. 	return ERROR_OK;

  1706. 	

  1707. }

  1708. 

  1709. int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)

  1710. {

  1711. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1712. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1713. 	

  1714. 	u32 reg[16];

  1715. 	int num_accesses = 0;

  1716. 	int thisrun_accesses;

  1717. 	int i;

  1718. 	u32 cpsr;

  1719. 	int retval;

  1720. 	int last_reg = 0;

  1721. 	

  1722. 	DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);

  1723. 

  1724. 	if (target->state != TARGET_HALTED)

  1725. 	{

  1726. 		WARNING("target not halted");

  1727. 		return ERROR_TARGET_NOT_HALTED;

  1728. 	}

  1729. 

  1730. 	/* sanitize arguments */

  1731. 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))

  1732. 		return ERROR_INVALID_ARGUMENTS;

  1733. 

  1734. 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))

  1735. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  1736. 	

  1737. 	/* load the base register with the address of the first word */

  1738. 	reg[0] = address;

  1739. 	arm7_9->write_core_regs(target, 0x1, reg);

  1740. 	

  1741. 	switch (size)

  1742. 	{

  1743. 		case 4:

  1744. 			while (num_accesses < count)

  1745. 			{

  1746. 				u32 reg_list;

  1747. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1748. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1749. 				

  1750. 				if (last_reg <= thisrun_accesses)

  1751. 					last_reg = thisrun_accesses;

  1752. 				

  1753. 				arm7_9->load_word_regs(target, reg_list);

  1754. 				

  1755. 				/* fast memory reads are only safe when the target is running

  1756. 				 * from a sufficiently high clock (32 kHz is usually too slow)

  1757. 				 */

  1758. 				if (arm7_9->fast_memory_access)

  1759. 					arm7_9_execute_fast_sys_speed(target);

  1760. 				else

  1761. 					arm7_9_execute_sys_speed(target);

  1762. 									

  1763. 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);

  1764. 				

  1765. 				/* advance buffer, count number of accesses */

  1766. 				buffer += thisrun_accesses * 4;

  1767. 				num_accesses += thisrun_accesses;

  1768. 			}	

  1769. 			break;

  1770. 		case 2:

  1771. 			while (num_accesses < count)

  1772. 			{

  1773. 				u32 reg_list;

  1774. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1775. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1776. 				

  1777. 				for (i = 1; i <= thisrun_accesses; i++)

  1778. 				{

  1779. 					if (i > last_reg)

  1780. 						last_reg = i;

  1781. 					arm7_9->load_hword_reg(target, i);

  1782. 					/* fast memory reads are only safe when the target is running

  1783. 					 * from a sufficiently high clock (32 kHz is usually too slow)

  1784. 					 */

  1785. 					if (arm7_9->fast_memory_access)

  1786. 						arm7_9_execute_fast_sys_speed(target);

  1787. 					else

  1788. 						arm7_9_execute_sys_speed(target);

  1789. 				}

  1790. 				

  1791. 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);

  1792. 				

  1793. 				/* advance buffer, count number of accesses */

  1794. 				buffer += thisrun_accesses * 2;

  1795. 				num_accesses += thisrun_accesses;

  1796. 			}	

  1797. 			break;

  1798. 		case 1:

  1799. 			while (num_accesses < count)

  1800. 			{

  1801. 				u32 reg_list;

  1802. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1803. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1804. 				

  1805. 				for (i = 1; i <= thisrun_accesses; i++)

  1806. 				{

  1807. 					if (i > last_reg)

  1808. 						last_reg = i;

  1809. 					arm7_9->load_byte_reg(target, i);

  1810. 					/* fast memory reads are only safe when the target is running

  1811. 					 * from a sufficiently high clock (32 kHz is usually too slow)

  1812. 					 */

  1813. 					if (arm7_9->fast_memory_access)

  1814. 						arm7_9_execute_fast_sys_speed(target);

  1815. 					else

  1816. 						arm7_9_execute_sys_speed(target);

  1817. 				}

  1818. 				

  1819. 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);

  1820. 				

  1821. 				/* advance buffer, count number of accesses */

  1822. 				buffer += thisrun_accesses * 1;

  1823. 				num_accesses += thisrun_accesses;

  1824. 			}	

  1825. 			break;

  1826. 		default:

  1827. 			ERROR("BUG: we shouldn't get here");

  1828. 			exit(-1);

  1829. 			break;

  1830. 	}

  1831. 	

  1832. 	for (i=0; i<=last_reg; i++)

  1833. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;

  1834. 

  1835. 	arm7_9->read_xpsr(target, &cpsr, 0);

  1836. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  1837. 	{

  1838. 		ERROR("JTAG error while reading cpsr");

  1839. 		exit(-1);

  1840. 	}

  1841. 

  1842. 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))

  1843. 	{

  1844. 		WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);

  1845. 

  1846. 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);

  1847. 

  1848. 		return ERROR_TARGET_DATA_ABORT;

  1849. 	}

  1850. 	

  1851. 	return ERROR_OK;

  1852. }

  1853. 

  1854. int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)

  1855. {

  1856. 	armv4_5_common_t *armv4_5 = target->arch_info;

  1857. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  1858. 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

  1859. 	

  1860. 	u32 reg[16];

  1861. 	int num_accesses = 0;

  1862. 	int thisrun_accesses;

  1863. 	int i;

  1864. 	u32 cpsr;

  1865. 	int retval;

  1866. 	int last_reg = 0;

  1867. 

  1868. 	DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);

  1869. 

  1870. 	if (target->state != TARGET_HALTED)

  1871. 	{

  1872. 		WARNING("target not halted");

  1873. 		return ERROR_TARGET_NOT_HALTED;

  1874. 	}

  1875. 

  1876. 	/* sanitize arguments */

  1877. 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))

  1878. 		return ERROR_INVALID_ARGUMENTS;

  1879. 

  1880. 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))

  1881. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  1882. 	

  1883. 	/* load the base register with the address of the first word */

  1884. 	reg[0] = address;

  1885. 	arm7_9->write_core_regs(target, 0x1, reg);

  1886. 	

  1887. 	/* Clear DBGACK, to make sure memory fetches work as expected */

  1888. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);

  1889. 	embeddedice_store_reg(dbg_ctrl);

  1890. 	

  1891. 	switch (size)

  1892. 	{

  1893. 		case 4:

  1894. 			while (num_accesses < count)

  1895. 			{

  1896. 				u32 reg_list;

  1897. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1898. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1899. 				

  1900. 				for (i = 1; i <= thisrun_accesses; i++)

  1901. 				{

  1902. 					if (i > last_reg)

  1903. 						last_reg = i;

  1904. 					reg[i] = target_buffer_get_u32(target, buffer);

  1905. 					buffer += 4;

  1906. 				}

  1907. 				

  1908. 				arm7_9->write_core_regs(target, reg_list, reg);

  1909. 				

  1910. 				arm7_9->store_word_regs(target, reg_list);

  1911. 				

  1912. 				/* fast memory writes are only safe when the target is running

  1913. 				 * from a sufficiently high clock (32 kHz is usually too slow)

  1914. 				 */

  1915. 				if (arm7_9->fast_memory_access)

  1916. 					arm7_9_execute_fast_sys_speed(target);

  1917. 				else

  1918. 					arm7_9_execute_sys_speed(target);

  1919. 				

  1920. 				num_accesses += thisrun_accesses;

  1921. 			}	

  1922. 			break;

  1923. 		case 2:

  1924. 			while (num_accesses < count)

  1925. 			{

  1926. 				u32 reg_list;

  1927. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1928. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1929. 				

  1930. 				for (i = 1; i <= thisrun_accesses; i++)

  1931. 				{

  1932. 					if (i > last_reg)

  1933. 						last_reg = i;

  1934. 					reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;

  1935. 					buffer += 2;

  1936. 				}

  1937. 				

  1938. 				arm7_9->write_core_regs(target, reg_list, reg);

  1939. 				

  1940. 				for (i = 1; i <= thisrun_accesses; i++)

  1941. 				{

  1942. 					arm7_9->store_hword_reg(target, i);

  1943. 					

  1944. 					/* fast memory writes are only safe when the target is running

  1945. 					 * from a sufficiently high clock (32 kHz is usually too slow)

  1946. 					 */

  1947. 					if (arm7_9->fast_memory_access)

  1948. 						arm7_9_execute_fast_sys_speed(target);

  1949. 					else

  1950. 						arm7_9_execute_sys_speed(target);

  1951. 				}

  1952. 				

  1953. 				num_accesses += thisrun_accesses;

  1954. 			}	

  1955. 			break;

  1956. 		case 1:

  1957. 			while (num_accesses < count)

  1958. 			{

  1959. 				u32 reg_list;

  1960. 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);

  1961. 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;

  1962. 				

  1963. 				for (i = 1; i <= thisrun_accesses; i++)

  1964. 				{

  1965. 					if (i > last_reg)

  1966. 						last_reg = i;

  1967. 					reg[i] = *buffer++ & 0xff;

  1968. 				}

  1969. 				

  1970. 				arm7_9->write_core_regs(target, reg_list, reg);

  1971. 				

  1972. 				for (i = 1; i <= thisrun_accesses; i++)

  1973. 				{

  1974. 					arm7_9->store_byte_reg(target, i);

  1975. 					/* fast memory writes are only safe when the target is running

  1976. 					 * from a sufficiently high clock (32 kHz is usually too slow)

  1977. 					 */

  1978. 					if (arm7_9->fast_memory_access)

  1979. 						arm7_9_execute_fast_sys_speed(target);

  1980. 					else

  1981. 						arm7_9_execute_sys_speed(target);

  1982. 				}

  1983. 				

  1984. 				num_accesses += thisrun_accesses;

  1985. 			}	

  1986. 			break;

  1987. 		default:

  1988. 			ERROR("BUG: we shouldn't get here");

  1989. 			exit(-1);

  1990. 			break;

  1991. 	}

  1992. 	

  1993. 	/* Re-Set DBGACK */

  1994. 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);

  1995. 	embeddedice_store_reg(dbg_ctrl);

  1996. 	

  1997. 	for (i=0; i<=last_reg; i++)

  1998. 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;

  1999. 

  2000. 	arm7_9->read_xpsr(target, &cpsr, 0);

  2001. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  2002. 	{

  2003. 		ERROR("JTAG error while reading cpsr");

  2004. 		exit(-1);

  2005. 	}

  2006. 

  2007. 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))

  2008. 	{

  2009. 		WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);

  2010. 

  2011. 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);

  2012. 

  2013. 		return ERROR_TARGET_DATA_ABORT;

  2014. 	}

  2015. 	

  2016. 	return ERROR_OK;

  2017. }

  2018. 

  2019. int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)

  2020. {

  2021. 	armv4_5_common_t *armv4_5 = target->arch_info;

  2022. 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

  2023. 	enum armv4_5_state core_state = armv4_5->core_state;

  2024. 	u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);

  2025. 	u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);

  2026. 	u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);

  2027. 	int i;

  2028. 	

  2029. 	u32 dcc_code[] = 

  2030. 	{

  2031. 		/* MRC      TST         BNE         MRC         STR         B */

  2032. 		0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9

  2033. 	};

  2034. 	

  2035. 	if (!arm7_9->dcc_downloads)

  2036. 		return target->type->write_memory(target, address, 4, count, buffer);

  2037. 

  2038. 	/* regrab previously allocated working_area, or allocate a new one */

  2039. 	if (!arm7_9->dcc_working_area)

  2040. 	{

  2041. 		u8 dcc_code_buf[6 * 4];

  2042. 		

  2043. 		/* make sure we have a working area */

  2044. 		if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)

  2045. 		{

  2046. 			INFO("no working area available, falling back to memory writes");

  2047. 			return target->type->write_memory(target, address, 4, count, buffer);

  2048. 		}

  2049. 		

  2050. 		/* copy target instructions to target endianness */

  2051. 		for (i = 0; i < 6; i++)

  2052. 		{

  2053. 			target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);

  2054. 		}

  2055. 		

  2056. 		/* write DCC code to working area */

  2057. 		target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);

  2058. 	}

  2059. 	

  2060. 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);

  2061. 	armv4_5->core_cache->reg_list[0].valid = 1;

  2062. 	armv4_5->core_cache->reg_list[0].dirty = 1;

  2063. 	armv4_5->core_state = ARMV4_5_STATE_ARM;

  2064. 

  2065. 	arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);

  2066. 	

  2067. 	for (i = 0; i < count; i++)

  2068. 	{

  2069. 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));

  2070. 		buffer += 4;

  2071. 	}

  2072. 	

  2073. 	target->type->halt(target);

  2074. 	

  2075. 	while (target->state != TARGET_HALTED)

  2076. 		target->type->poll(target);

  2077. 	

  2078. 	/* restore target state */

  2079. 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);

  2080. 	armv4_5->core_cache->reg_list[0].valid = 1;

  2081. 	armv4_5->core_cache->reg_list[0].dirty = 1;

  2082. 	buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);

  2083. 	armv4_5->core_cache->reg_list[1].valid = 1;

  2084. 	armv4_5->core_cache->reg_list[1].dirty = 1;

  2085. 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);

  2086. 	armv4_5->core_cache->reg_list[15].valid = 1;

  2087. 	armv4_5->core_cache->reg_list[15].dirty = 1;

  2088. 	armv4_5->core_state = core_state;

  2089. 	

  2090. 	return ERROR_OK;

  2091. }

  2092. 

  2093. int arm7_9_register_commands(struct command_context_s *cmd_ctx)

  2094. {

  2095. 	command_t *arm7_9_cmd;

  2096. 	

  2097. 	arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");

  2098. 

  2099. 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");

  2100. 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");

  2101. 	

  2102. 	register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");	

  2103. 	

  2104. 	register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");

  2105. 	register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");

  2106. 	register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,

  2107. 		COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");

  2108. 	register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,

  2109. 		 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");

  2110. 	register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,

  2111. 		 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");

  2112. 	register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,

  2113. 		COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");

  2114. 

  2115. 	armv4_5_register_commands(cmd_ctx);

  2116. 	

  2117. 	etm_register_commands(cmd_ctx);

  2118. 	

  2119. 	return ERROR_OK;

  2120. }

  2121. 

  2122. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2123. {

  2124. 	u32 value;

  2125. 	int spsr;

  2126. 	int retval;

  2127. 	target_t *target = get_current_target(cmd_ctx);

  2128. 	armv4_5_common_t *armv4_5;

  2129. 	arm7_9_common_t *arm7_9;

  2130. 

  2131. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2132. 	{

  2133. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2134. 		return ERROR_OK;

  2135. 	}

  2136. 	

  2137. 	if (target->state != TARGET_HALTED)

  2138. 	{

  2139. 		command_print(cmd_ctx, "can't write registers while running");

  2140. 		return ERROR_OK;

  2141. 	}

  2142. 	

  2143. 	if (argc < 2)

  2144. 	{

  2145. 		command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");

  2146. 		return ERROR_OK;

  2147. 	}

  2148. 	

  2149. 	value = strtoul(args[0], NULL, 0);

  2150. 	spsr = strtol(args[1], NULL, 0);

  2151. 	

  2152. 	/* if we're writing the CPSR, mask the T bit */

  2153. 	if (!spsr)

  2154. 		value &= ~0x20;

  2155. 	

  2156. 	arm7_9->write_xpsr(target, value, spsr);

  2157. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  2158. 	{

  2159. 		ERROR("JTAG error while writing to xpsr");

  2160. 		exit(-1);

  2161. 	}

  2162. 	

  2163. 	return ERROR_OK;

  2164. }

  2165. 

  2166. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2167. {

  2168. 	u32 value;

  2169. 	int rotate;

  2170. 	int spsr;

  2171. 	int retval;

  2172. 	target_t *target = get_current_target(cmd_ctx);

  2173. 	armv4_5_common_t *armv4_5;

  2174. 	arm7_9_common_t *arm7_9;

  2175. 

  2176. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2177. 	{

  2178. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2179. 		return ERROR_OK;

  2180. 	}

  2181. 	

  2182. 	if (target->state != TARGET_HALTED)

  2183. 	{

  2184. 		command_print(cmd_ctx, "can't write registers while running");

  2185. 		return ERROR_OK;

  2186. 	}

  2187. 	

  2188. 	if (argc < 3)

  2189. 	{

  2190. 		command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");

  2191. 		return ERROR_OK;

  2192. 	}

  2193. 	

  2194. 	value = strtoul(args[0], NULL, 0);

  2195. 	rotate = strtol(args[1], NULL, 0);

  2196. 	spsr = strtol(args[2], NULL, 0);

  2197. 		

  2198. 	arm7_9->write_xpsr_im8(target, value, rotate, spsr);

  2199. 	if ((retval = jtag_execute_queue()) != ERROR_OK)

  2200. 	{

  2201. 		ERROR("JTAG error while writing 8-bit immediate to xpsr");

  2202. 		exit(-1);

  2203. 	}

  2204. 	

  2205. 	return ERROR_OK;

  2206. }

  2207. 

  2208. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2209. {

  2210. 	u32 value;

  2211. 	u32 mode;

  2212. 	int num;

  2213. 	target_t *target = get_current_target(cmd_ctx);

  2214. 	armv4_5_common_t *armv4_5;

  2215. 	arm7_9_common_t *arm7_9;

  2216. 		

  2217. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2218. 	{

  2219. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2220. 		return ERROR_OK;

  2221. 	}

  2222. 	

  2223. 	if (target->state != TARGET_HALTED)

  2224. 	{

  2225. 		command_print(cmd_ctx, "can't write registers while running");

  2226. 		return ERROR_OK;

  2227. 	}

  2228. 	

  2229. 	if (argc < 3)

  2230. 	{

  2231. 		command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");

  2232. 		return ERROR_OK;

  2233. 	}

  2234. 	

  2235. 	num = strtol(args[0], NULL, 0);

  2236. 	mode = strtoul(args[1], NULL, 0);

  2237. 	value = strtoul(args[2], NULL, 0);

  2238. 	

  2239. 	arm7_9_write_core_reg(target, num, mode, value);

  2240. 	

  2241. 	return ERROR_OK;

  2242. }

  2243. 

  2244. int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2245. {

  2246. 	target_t *target = get_current_target(cmd_ctx);

  2247. 	armv4_5_common_t *armv4_5;

  2248. 	arm7_9_common_t *arm7_9;

  2249. 	

  2250. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2251. 	{

  2252. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2253. 		return ERROR_OK;

  2254. 	}

  2255. 	

  2256. 	if (argc == 0)

  2257. 	{

  2258. 		command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");

  2259. 		return ERROR_OK;

  2260. 	}

  2261. 	

  2262. 	if (strcmp("enable", args[0]) == 0)

  2263. 	{

  2264. 		if (arm7_9->sw_bkpts_use_wp)

  2265. 		{

  2266. 			arm7_9_enable_sw_bkpts(target);

  2267. 		}

  2268. 		else

  2269. 		{

  2270. 			arm7_9->sw_bkpts_enabled = 1;

  2271. 		}

  2272. 	}

  2273. 	else if (strcmp("disable", args[0]) == 0)

  2274. 	{

  2275. 		if (arm7_9->sw_bkpts_use_wp)

  2276. 		{

  2277. 			arm7_9_disable_sw_bkpts(target);

  2278. 		}

  2279. 		else

  2280. 		{

  2281. 			arm7_9->sw_bkpts_enabled = 0;

  2282. 		}

  2283. 	}

  2284. 	else

  2285. 	{

  2286. 		command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");

  2287. 	}

  2288. 	

  2289. 	command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");

  2290. 	

  2291. 	return ERROR_OK;

  2292. }

  2293. 

  2294. int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2295. {

  2296. 	target_t *target = get_current_target(cmd_ctx);

  2297. 	armv4_5_common_t *armv4_5;

  2298. 	arm7_9_common_t *arm7_9;

  2299. 	

  2300. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2301. 	{

  2302. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2303. 		return ERROR_OK;

  2304. 	}

  2305. 	

  2306. 	if ((argc >= 1) && (strcmp("enable", args[0]) == 0))

  2307. 	{

  2308. 		arm7_9->force_hw_bkpts = 1;

  2309. 		if (arm7_9->sw_bkpts_use_wp)

  2310. 		{

  2311. 			arm7_9_disable_sw_bkpts(target);

  2312. 		}

  2313. 	}

  2314. 	else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))

  2315. 	{

  2316. 		arm7_9->force_hw_bkpts = 0;

  2317. 	}

  2318. 	else

  2319. 	{

  2320. 		command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");

  2321. 	}

  2322. 		

  2323. 	command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");

  2324. 

  2325. 	return ERROR_OK;

  2326. }

  2327. 

  2328. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2329. {

  2330. 	target_t *target = get_current_target(cmd_ctx);

  2331. 	armv4_5_common_t *armv4_5;

  2332. 	arm7_9_common_t *arm7_9;

  2333. 	

  2334. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2335. 	{

  2336. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2337. 		return ERROR_OK;

  2338. 	}

  2339. 	

  2340. 	if (argc > 0)

  2341. 	{

  2342. 		if (strcmp("enable", args[0]) == 0)

  2343. 		{

  2344. 			arm7_9->use_dbgrq = 1;

  2345. 		}

  2346. 		else if (strcmp("disable", args[0]) == 0)

  2347. 		{

  2348. 			arm7_9->use_dbgrq = 0;

  2349. 		}

  2350. 		else

  2351. 		{

  2352. 			command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");

  2353. 		}

  2354. 	}

  2355. 		

  2356. 	command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");

  2357. 

  2358. 	return ERROR_OK;

  2359. }

  2360. 

  2361. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2362. {

  2363. 	target_t *target = get_current_target(cmd_ctx);

  2364. 	armv4_5_common_t *armv4_5;

  2365. 	arm7_9_common_t *arm7_9;

  2366. 	

  2367. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2368. 	{

  2369. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2370. 		return ERROR_OK;

  2371. 	}

  2372. 	

  2373. 	if (argc > 0)

  2374. 	{

  2375. 		if (strcmp("enable", args[0]) == 0)

  2376. 		{

  2377. 			arm7_9->fast_memory_access = 1;

  2378. 		}

  2379. 		else if (strcmp("disable", args[0]) == 0)

  2380. 		{

  2381. 			arm7_9->fast_memory_access = 0;

  2382. 		}

  2383. 		else

  2384. 		{

  2385. 			command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");

  2386. 		}

  2387. 	}

  2388. 		

  2389. 	command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");

  2390. 

  2391. 	return ERROR_OK;

  2392. }

  2393. 

  2394. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

  2395. {

  2396. 	target_t *target = get_current_target(cmd_ctx);

  2397. 	armv4_5_common_t *armv4_5;

  2398. 	arm7_9_common_t *arm7_9;

  2399. 	

  2400. 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)

  2401. 	{

  2402. 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");

  2403. 		return ERROR_OK;

  2404. 	}

  2405. 	

  2406. 	if (argc > 0)

  2407. 	{

  2408. 		if (strcmp("enable", args[0]) == 0)

  2409. 		{

  2410. 			arm7_9->dcc_downloads = 1;

  2411. 		}

  2412. 		else if (strcmp("disable", args[0]) == 0)

  2413. 		{

  2414. 			arm7_9->dcc_downloads = 0;

  2415. 		}

  2416. 		else

  2417. 		{

  2418. 			command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");

  2419. 		}

  2420. 	}

  2421. 		

  2422. 	command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");

  2423. 

  2424. 	return ERROR_OK;

  2425. }

  2426. 

  2427. int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)

  2428. {

  2429. 	armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;

  2430. 	

  2431. 	arm7_9->common_magic = ARM7_9_COMMON_MAGIC;

  2432. 	

  2433. 	arm_jtag_setup_connection(&arm7_9->jtag_info);

  2434. 	arm7_9->wp_available = 2;

  2435. 	arm7_9->wp0_used = 0;

  2436. 	arm7_9->wp1_used = 0;

  2437. 	arm7_9->force_hw_bkpts = 0;

  2438. 	arm7_9->use_dbgrq = 0;

  2439. 	

  2440. 	arm7_9->etm_ctx = NULL;

  2441. 	arm7_9->has_single_step = 0;

  2442. 	arm7_9->has_monitor_mode = 0;

  2443. 	arm7_9->has_vector_catch = 0;

  2444. 	

  2445. 	arm7_9->reinit_embeddedice = 0;

  2446. 	

  2447. 	arm7_9->debug_entry_from_reset = 0;

  2448. 	

  2449. 	arm7_9->dcc_working_area = NULL;

  2450. 	

  2451. 	arm7_9->fast_memory_access = 0;

  2452. 	arm7_9->dcc_downloads = 0;

  2453. 

  2454. 	jtag_register_event_callback(arm7_9_jtag_callback, target);

  2455. 

  2456. 	armv4_5->arch_info = arm7_9;

  2457. 	armv4_5->read_core_reg = arm7_9_read_core_reg;

  2458. 	armv4_5->write_core_reg = arm7_9_write_core_reg;

  2459. 	armv4_5->full_context = arm7_9_full_context;

  2460. 	

  2461. 	armv4_5_init_arch_info(target, armv4_5);

  2462. 	

  2463. 	return ERROR_OK;

  2464. }