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6.7 KiB

  1. /****************************************************************************
  2. * Copyright (c) 2006 by Michael Fischer. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * 3. Neither the name of the author nor the names of its contributors may
  14. * be used to endorse or promote products derived from this software
  15. * without specific prior written permission.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21. * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27. * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28. * SUCH DAMAGE.
  29. *
  30. ****************************************************************************
  31. *
  32. * History:
  33. *
  34. * 18.12.06 mifi First Version
  35. * The hardware initialization is based on the startup file
  36. * crtat91sam7x256_rom.S from NutOS 4.2.1.
  37. * Therefore partial copyright by egnite Software GmbH.
  38. ****************************************************************************/
  39. /*
  40. * Some defines for the program status registers
  41. */
  42. ARM_MODE_USER = 0x10 /* Normal User Mode */
  43. ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
  44. ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
  45. ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
  46. ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
  47. ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
  48. ARM_MODE_SYS = 0x1F /* System Running in Privileged Operating Mode */
  49. ARM_MODE_MASK = 0x1F
  50. I_BIT = 0x80 /* disable IRQ when I bit is set */
  51. F_BIT = 0x40 /* disable IRQ when I bit is set */
  52. /*
  53. * Register Base Address
  54. */
  55. AIC_BASE = 0xFFFFF000
  56. AIC_EOICR_OFF = 0x130
  57. AIC_IDCR_OFF = 0x124
  58. RSTC_MR = 0xFFFFFD08
  59. RSTC_KEY = 0xA5000000
  60. RSTC_URSTEN = 0x00000001
  61. WDT_BASE = 0xFFFFFD40
  62. WDT_MR_OFF = 0x00000004
  63. WDT_WDDIS = 0x00008000
  64. MC_BASE = 0xFFFFFF00
  65. MC_FMR_OFF = 0x00000060
  66. MC_FWS_1FWS = 0x00480100
  67. .section .vectors,"ax"
  68. .code 32
  69. /****************************************************************************/
  70. /* Vector table and reset entry */
  71. /****************************************************************************/
  72. _vectors:
  73. ldr pc, ResetAddr /* Reset */
  74. ldr pc, UndefAddr /* Undefined instruction */
  75. ldr pc, SWIAddr /* Software interrupt */
  76. ldr pc, PAbortAddr /* Prefetch abort */
  77. ldr pc, DAbortAddr /* Data abort */
  78. ldr pc, ReservedAddr /* Reserved */
  79. ldr pc, IRQAddr /* IRQ interrupt */
  80. ldr pc, FIQAddr /* FIQ interrupt */
  81. ResetAddr: .word ResetHandler
  82. UndefAddr: .word UndefHandler
  83. SWIAddr: .word SWIHandler
  84. PAbortAddr: .word PAbortHandler
  85. DAbortAddr: .word DAbortHandler
  86. ReservedAddr: .word 0
  87. IRQAddr: .word IRQHandler
  88. FIQAddr: .word FIQHandler
  89. .ltorg
  90. .section .init, "ax"
  91. .code 32
  92. .global ResetHandler
  93. .global ExitFunction
  94. .extern main
  95. /****************************************************************************/
  96. /* Reset handler */
  97. /****************************************************************************/
  98. ResetHandler:
  99. /*
  100. * The watchdog is enabled after processor reset. Disable it.
  101. */
  102. ldr r1, =WDT_BASE
  103. ldr r0, =WDT_WDDIS
  104. str r0, [r1, #WDT_MR_OFF]
  105. /*
  106. * Enable user reset: assertion length programmed to 1ms
  107. */
  108. ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
  109. ldr r1, =RSTC_MR
  110. str r0, [r1, #0]
  111. /*
  112. * Use 2 cycles for flash access.
  113. */
  114. ldr r1, =MC_BASE
  115. ldr r0, =MC_FWS_1FWS
  116. str r0, [r1, #MC_FMR_OFF]
  117. /*
  118. * Disable all interrupts. Useful for debugging w/o target reset.
  119. */
  120. ldr r1, =AIC_BASE
  121. mvn r0, #0
  122. str r0, [r1, #AIC_EOICR_OFF]
  123. str r0, [r1, #AIC_IDCR_OFF]
  124. /*
  125. * Setup a stack for each mode
  126. */
  127. msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
  128. ldr sp, =__stack_und_end
  129. msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
  130. ldr sp, =__stack_abt_end
  131. msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
  132. ldr sp, =__stack_fiq_end
  133. msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
  134. ldr sp, =__stack_irq_end
  135. msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
  136. ldr sp, =__stack_svc_end
  137. /*
  138. * Clear .bss section
  139. */
  140. ldr r1, =__bss_start
  141. ldr r2, =__bss_end
  142. ldr r3, =0
  143. bss_clear_loop:
  144. cmp r1, r2
  145. strne r3, [r1], #+4
  146. bne bss_clear_loop
  147. /*
  148. * Jump to main
  149. */
  150. mrs r0, cpsr
  151. bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
  152. msr cpsr, r0
  153. mov r0, #0 /* No arguments */
  154. mov r1, #0 /* No arguments */
  155. ldr r2, =main
  156. mov lr, pc
  157. bx r2 /* And jump... */
  158. ExitFunction:
  159. nop
  160. nop
  161. nop
  162. b ExitFunction
  163. /****************************************************************************/
  164. /* Default interrupt handler */
  165. /****************************************************************************/
  166. UndefHandler:
  167. b UndefHandler
  168. SWIHandler:
  169. b SWIHandler
  170. PAbortHandler:
  171. b PAbortHandler
  172. DAbortHandler:
  173. b DAbortHandler
  174. IRQHandler:
  175. b IRQHandler
  176. FIQHandler:
  177. b FIQHandler
  178. .weak ExitFunction
  179. .weak UndefHandler, PAbortHandler, DAbortHandler
  180. .weak IRQHandler, FIQHandler
  181. .ltorg
  182. /*** EOF ***/