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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin
  3. * lundin@mlu.mine.nu
  4. *
  5. * Copyright (C) 2008 by Spencer Oliver
  6. * spen@spen-soft.co.uk
  7. *
  8. * Copyright (C) 2009 by Oyvind Harboe
  9. * oyvind.harboe@zylin.com
  10. *
  11. * Copyright (C) 2009-2010 by David Brownell
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the
  25. * Free Software Foundation, Inc.,
  26. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  27. ***************************************************************************/
  28. /**
  29. * @file
  30. * This file implements JTAG transport support for cores implementing
  31. the ARM Debug Interface version 5 (ADIv5).
  32. */
  33. #ifdef HAVE_CONFIG_H
  34. #include "config.h"
  35. #endif
  36. #include "arm.h"
  37. #include "arm_adi_v5.h"
  38. #include <helper/time_support.h>
  39. /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  40. #define JTAG_DP_ABORT 0x8
  41. #define JTAG_DP_DPACC 0xA
  42. #define JTAG_DP_APACC 0xB
  43. #define JTAG_DP_IDCODE 0xE
  44. /* three-bit ACK values for DPACC and APACC reads */
  45. #define JTAG_ACK_OK_FAULT 0x2
  46. #define JTAG_ACK_WAIT 0x1
  47. /***************************************************************************
  48. *
  49. * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
  50. *
  51. ***************************************************************************/
  52. /**
  53. * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
  54. * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
  55. * discusses operations which access these registers.
  56. *
  57. * Note that only one scan is performed. If RnW is set, a separate scan
  58. * will be needed to collect the data which was read; the "invalue" collects
  59. * the posted result of a preceding operation, not the current one.
  60. *
  61. * @param dap the DAP
  62. * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
  63. * @param reg_addr two significant bits; A[3:2]; for APACC access, the
  64. * SELECT register has more addressing bits.
  65. * @param RnW false iff outvalue will be written to the DP or AP
  66. * @param outvalue points to a 32-bit (little-endian) integer
  67. * @param invalue NULL, or points to a 32-bit (little-endian) integer
  68. * @param ack points to where the three bit JTAG_ACK_* code will be stored
  69. */
  70. static int adi_jtag_dp_scan(struct adiv5_dap *dap,
  71. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  72. uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  73. {
  74. struct arm_jtag *jtag_info = dap->jtag_info;
  75. struct scan_field fields[2];
  76. uint8_t out_addr_buf;
  77. int retval;
  78. retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
  79. if (retval != ERROR_OK)
  80. return retval;
  81. /* Scan out a read or write operation using some DP or AP register.
  82. * For APACC access with any sticky error flag set, this is discarded.
  83. */
  84. fields[0].num_bits = 3;
  85. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  86. fields[0].out_value = &out_addr_buf;
  87. fields[0].in_value = ack;
  88. /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
  89. * complete; data we write is discarded, data we read is unpredictable.
  90. * When overrun detect is active, STICKYORUN is set.
  91. */
  92. fields[1].num_bits = 32;
  93. fields[1].out_value = outvalue;
  94. fields[1].in_value = invalue;
  95. jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
  96. /* Add specified number of tck clocks after starting memory bus
  97. * access, giving the hardware time to complete the access.
  98. * They provide more time for the (MEM) AP to complete the read ...
  99. * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
  100. */
  101. if ((instr == JTAG_DP_APACC)
  102. && ((reg_addr == AP_REG_DRW)
  103. || ((reg_addr & 0xF0) == AP_REG_BD0))
  104. && (dap->memaccess_tck != 0))
  105. jtag_add_runtest(dap->memaccess_tck,
  106. TAP_IDLE);
  107. return ERROR_OK;
  108. }
  109. /**
  110. * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
  111. * This is exactly like adi_jtag_dp_scan(), except that endianness
  112. * conversions are performed (so the types of invalue and outvalue
  113. * must be different).
  114. */
  115. static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
  116. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  117. uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
  118. {
  119. uint8_t out_value_buf[4];
  120. int retval;
  121. buf_set_u32(out_value_buf, 0, 32, outvalue);
  122. retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
  123. out_value_buf, (uint8_t *)invalue, ack);
  124. if (retval != ERROR_OK)
  125. return retval;
  126. if (invalue)
  127. jtag_add_callback(arm_le_to_h_u32,
  128. (jtag_callback_data_t) invalue);
  129. return retval;
  130. }
  131. /**
  132. * Utility to write AP registers.
  133. */
  134. static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
  135. uint8_t reg_addr, uint8_t *outvalue)
  136. {
  137. return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
  138. outvalue, NULL, NULL);
  139. }
  140. static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
  141. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  142. uint32_t outvalue, uint32_t *invalue)
  143. {
  144. int retval;
  145. /* Issue the read or write */
  146. retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
  147. RnW, outvalue, NULL, NULL);
  148. if (retval != ERROR_OK)
  149. return retval;
  150. /* For reads, collect posted value; RDBUFF has no other effect.
  151. * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
  152. */
  153. if ((RnW == DPAP_READ) && (invalue != NULL))
  154. retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
  155. DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
  156. return retval;
  157. }
  158. static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
  159. {
  160. int retval;
  161. uint32_t ctrlstat;
  162. /* too expensive to call keep_alive() here */
  163. /* Here be dragons!
  164. *
  165. * It is easy to be in a JTAG clock range where the target
  166. * is not operating in a stable fashion. This happens
  167. * for a few reasons:
  168. *
  169. * - the user may construct a simple test case to try to see
  170. * if a higher JTAG clock works to eke out more performance.
  171. * This simple case may pass, but more complex situations can
  172. * fail.
  173. *
  174. * - The mostly works JTAG clock rate and the complete failure
  175. * JTAG clock rate may be as much as 2-4x apart. This seems
  176. * to be especially true on RC oscillator driven parts.
  177. *
  178. * So: even if calling adi_jtag_scan_inout_check_u32() multiple
  179. * times here seems to "make things better here", it is just
  180. * hiding problems with too high a JTAG clock.
  181. *
  182. * Note that even if some parts have RCLK/RTCK, that doesn't
  183. * mean that RCLK/RTCK is the *correct* rate to run the JTAG
  184. * interface at, i.e. RCLK/RTCK rates can be "too high", especially
  185. * before the RC oscillator phase is not yet complete.
  186. */
  187. /* Post CTRL/STAT read; discard any previous posted read value
  188. * but collect its ACK status.
  189. */
  190. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  191. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  192. if (retval != ERROR_OK)
  193. return retval;
  194. retval = jtag_execute_queue();
  195. if (retval != ERROR_OK)
  196. return retval;
  197. dap->ack = dap->ack & 0x7;
  198. /* common code path avoids calling timeval_ms() */
  199. if (dap->ack != JTAG_ACK_OK_FAULT) {
  200. long long then = timeval_ms();
  201. while (dap->ack != JTAG_ACK_OK_FAULT) {
  202. if (dap->ack == JTAG_ACK_WAIT) {
  203. if ((timeval_ms()-then) > 1000) {
  204. /* NOTE: this would be a good spot
  205. * to use JTAG_DP_ABORT.
  206. */
  207. LOG_WARNING("Timeout (1000ms) waiting "
  208. "for ACK=OK/FAULT "
  209. "in JTAG-DP transaction");
  210. return ERROR_JTAG_DEVICE_ERROR;
  211. }
  212. } else {
  213. LOG_WARNING("Invalid ACK %#x "
  214. "in JTAG-DP transaction",
  215. dap->ack);
  216. return ERROR_JTAG_DEVICE_ERROR;
  217. }
  218. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  219. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. retval = jtag_execute_queue();
  223. if (retval != ERROR_OK)
  224. return retval;
  225. dap->ack = dap->ack & 0x7;
  226. }
  227. }
  228. /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
  229. /* Check for STICKYERR and STICKYORUN */
  230. if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
  231. LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
  232. /* Check power to debug regions */
  233. if ((ctrlstat & 0xf0000000) != 0xf0000000) {
  234. retval = ahbap_debugport_init(dap);
  235. if (retval != ERROR_OK)
  236. return retval;
  237. } else {
  238. uint32_t mem_ap_csw, mem_ap_tar;
  239. /* Maybe print information about last intended
  240. * MEM-AP access; but not if autoincrementing.
  241. * *Real* CSW and TAR values are always shown.
  242. */
  243. if (dap->ap_tar_value != (uint32_t) -1)
  244. LOG_DEBUG("MEM-AP Cached values: "
  245. "ap_bank 0x%" PRIx32
  246. ", ap_csw 0x%" PRIx32
  247. ", ap_tar 0x%" PRIx32,
  248. dap->ap_bank_value,
  249. dap->ap_csw_value,
  250. dap->ap_tar_value);
  251. if (ctrlstat & SSTICKYORUN)
  252. LOG_ERROR("JTAG-DP OVERRUN - check clock, "
  253. "memaccess, or reduce jtag speed");
  254. if (ctrlstat & SSTICKYERR)
  255. LOG_ERROR("JTAG-DP STICKY ERROR");
  256. /* Clear Sticky Error Bits */
  257. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  258. DP_CTRL_STAT, DPAP_WRITE,
  259. dap->dp_ctrl_stat | SSTICKYORUN
  260. | SSTICKYERR, NULL);
  261. if (retval != ERROR_OK)
  262. return retval;
  263. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  264. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  265. if (retval != ERROR_OK)
  266. return retval;
  267. retval = jtag_execute_queue();
  268. if (retval != ERROR_OK)
  269. return retval;
  270. LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
  271. retval = dap_queue_ap_read(dap,
  272. AP_REG_CSW, &mem_ap_csw);
  273. if (retval != ERROR_OK)
  274. return retval;
  275. retval = dap_queue_ap_read(dap,
  276. AP_REG_TAR, &mem_ap_tar);
  277. if (retval != ERROR_OK)
  278. return retval;
  279. retval = jtag_execute_queue();
  280. if (retval != ERROR_OK)
  281. return retval;
  282. LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
  283. PRIx32, mem_ap_csw, mem_ap_tar);
  284. }
  285. retval = jtag_execute_queue();
  286. if (retval != ERROR_OK)
  287. return retval;
  288. return ERROR_JTAG_DEVICE_ERROR;
  289. }
  290. return ERROR_OK;
  291. }
  292. /*--------------------------------------------------------------------------*/
  293. static int jtag_idcode_q_read(struct adiv5_dap *dap,
  294. uint8_t *ack, uint32_t *data)
  295. {
  296. struct arm_jtag *jtag_info = dap->jtag_info;
  297. int retval;
  298. struct scan_field fields[1];
  299. /* This is a standard JTAG operation -- no DAP tweakage */
  300. retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
  301. if (retval != ERROR_OK)
  302. return retval;
  303. fields[0].num_bits = 32;
  304. fields[0].out_value = NULL;
  305. fields[0].in_value = (void *) data;
  306. jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
  307. jtag_add_callback(arm_le_to_h_u32,
  308. (jtag_callback_data_t) data);
  309. return ERROR_OK;
  310. }
  311. static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
  312. uint32_t *data)
  313. {
  314. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  315. reg, DPAP_READ, 0, data);
  316. }
  317. static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
  318. uint32_t data)
  319. {
  320. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  321. reg, DPAP_WRITE, data, NULL);
  322. }
  323. /** Select the AP register bank matching bits 7:4 of reg. */
  324. static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
  325. {
  326. uint32_t select_ap_bank = reg & 0x000000F0;
  327. if (select_ap_bank == dap->ap_bank_value)
  328. return ERROR_OK;
  329. dap->ap_bank_value = select_ap_bank;
  330. select_ap_bank |= dap->ap_current;
  331. return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
  332. }
  333. static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
  334. uint32_t *data)
  335. {
  336. int retval = jtag_ap_q_bankselect(dap, reg);
  337. if (retval != ERROR_OK)
  338. return retval;
  339. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
  340. DPAP_READ, 0, data);
  341. }
  342. static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
  343. uint32_t data)
  344. {
  345. uint8_t out_value_buf[4];
  346. int retval = jtag_ap_q_bankselect(dap, reg);
  347. if (retval != ERROR_OK)
  348. return retval;
  349. buf_set_u32(out_value_buf, 0, 32, data);
  350. return adi_jtag_ap_write_check(dap, reg, out_value_buf);
  351. }
  352. static int jtag_ap_q_read_block(struct adiv5_dap *dap, unsigned reg,
  353. uint32_t blocksize, uint8_t *buffer)
  354. {
  355. uint32_t readcount;
  356. int retval = ERROR_OK;
  357. /* Scan out first read */
  358. retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
  359. DPAP_READ, 0, NULL, NULL);
  360. if (retval != ERROR_OK)
  361. return retval;
  362. for (readcount = 0; readcount < blocksize - 1; readcount++) {
  363. /* Scan out next read; scan in posted value for the
  364. * previous one. Assumes read is acked "OK/FAULT",
  365. * and CTRL_STAT says that meant "OK".
  366. */
  367. retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
  368. DPAP_READ, 0, buffer + 4 * readcount,
  369. &dap->ack);
  370. if (retval != ERROR_OK)
  371. return retval;
  372. }
  373. /* Scan in last posted value; RDBUFF has no other effect,
  374. * assuming ack is OK/FAULT and CTRL_STAT says "OK".
  375. */
  376. retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
  377. DPAP_READ, 0, buffer + 4 * readcount,
  378. &dap->ack);
  379. return retval;
  380. }
  381. static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
  382. {
  383. /* for JTAG, this is the only valid ABORT register operation */
  384. return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
  385. 0, DPAP_WRITE, 1, NULL, ack);
  386. }
  387. static int jtag_dp_run(struct adiv5_dap *dap)
  388. {
  389. return jtagdp_transaction_endcheck(dap);
  390. }
  391. /* FIXME don't export ... just initialize as
  392. * part of DAP setup
  393. */
  394. const struct dap_ops jtag_dp_ops = {
  395. .queue_idcode_read = jtag_idcode_q_read,
  396. .queue_dp_read = jtag_dp_q_read,
  397. .queue_dp_write = jtag_dp_q_write,
  398. .queue_ap_read = jtag_ap_q_read,
  399. .queue_ap_write = jtag_ap_q_write,
  400. .queue_ap_read_block = jtag_ap_q_read_block,
  401. .queue_ap_abort = jtag_ap_q_abort,
  402. .run = jtag_dp_run,
  403. };
  404. static const uint8_t swd2jtag_bitseq[] = {
  405. /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
  406. * putting both JTAG and SWD logic into reset state.
  407. */
  408. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  409. /* Switching equence disables SWD and enables JTAG
  410. * NOTE: bits in the DP's IDCODE can expose the need for
  411. * the old/deprecated sequence (0xae 0xde).
  412. */
  413. 0x3c, 0xe7,
  414. /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
  415. * putting both JTAG and SWD logic into reset state.
  416. * NOTE: some docs say "at least 5".
  417. */
  418. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  419. };
  420. /** Put the debug link into JTAG mode, if the target supports it.
  421. * The link's initial mode may be either SWD or JTAG.
  422. *
  423. * @param target Enters JTAG mode (if possible).
  424. *
  425. * Note that targets implemented with SW-DP do not support JTAG, and
  426. * that some targets which could otherwise support it may have been
  427. * configured to disable JTAG signaling
  428. *
  429. * @return ERROR_OK or else a fault code.
  430. */
  431. int dap_to_jtag(struct target *target)
  432. {
  433. int retval;
  434. LOG_DEBUG("Enter JTAG mode");
  435. /* REVISIT it's nasty to need to make calls to a "jtag"
  436. * subsystem if the link isn't in JTAG mode...
  437. */
  438. retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
  439. swd2jtag_bitseq, TAP_RESET);
  440. if (retval == ERROR_OK)
  441. retval = jtag_execute_queue();
  442. /* REVISIT set up the DAP's ops vector for JTAG mode. */
  443. return retval;
  444. }