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  1. /***************************************************************************
  2. * Copyright (C) 2008 by *
  3. * Karl RobinSod <karl.robinsod@gmail.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. /***************************************************************************
  21. * There are some things to notice
  22. *
  23. * You need to unprotect flash sectors each time you connect the OpenOCD
  24. * Dumping 1MB takes about 60 Seconds
  25. * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
  26. * Writing 1MB takes 88 seconds
  27. *
  28. ***************************************************************************/
  29. #ifdef HAVE_CONFIG_H
  30. #include "config.h"
  31. #endif
  32. #include "replacements.h"
  33. #include "lpc288x.h"
  34. #include "flash.h"
  35. #include "target.h"
  36. #include "log.h"
  37. #include "binarybuffer.h"
  38. #include "types.h"
  39. #include <stdlib.h>
  40. #include <string.h>
  41. #include <unistd.h>
  42. #define LOAD_TIMER_ERASE 0
  43. #define LOAD_TIMER_WRITE 1
  44. #define FLASH_PAGE_SIZE 512
  45. /* LPC288X control registers */
  46. #define DBGU_CIDR 0x8000507C
  47. /* LPC288X flash registers */
  48. #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
  49. #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
  50. #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
  51. #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
  52. #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0 */
  53. #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
  54. #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
  55. #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
  56. #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
  57. #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
  58. #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
  59. #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power savings. R/W 1*/
  60. #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from Power Down mode. R/W -*/
  61. /* F_CTRL bits */
  62. #define FC_CS 0x0001
  63. #define FC_FUNC 0x0002
  64. #define FC_WEN 0x0004
  65. #define FC_RD_LATCH 0x0020
  66. #define FC_PROTECT 0x0080
  67. #define FC_SET_DATA 0x0400
  68. #define FC_RSSL 0x0800
  69. #define FC_PROG_REQ 0x1000
  70. #define FC_CLR_BUF 0x4000
  71. #define FC_LOAD_REQ 0x8000
  72. /* F_STAT bits */
  73. #define FS_DONE 0x0001
  74. #define FS_PROGGNT 0x0002
  75. #define FS_RDY 0x0004
  76. #define FS_ERR 0x0020
  77. /* F_PROG_TIME */
  78. #define FPT_TIME_MASK 0x7FFF
  79. #define FPT_ENABLE 0x8000
  80. /* F_WAIT */
  81. #define FW_WAIT_STATES_MASK 0x00FF
  82. #define FW_SET_MASK 0xC000
  83. /* F_CLK_TIME */
  84. #define FCT_CLK_DIV_MASK 0x0FFF
  85. int lpc288x_register_commands(struct command_context_s *cmd_ctx);
  86. int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  87. int lpc288x_erase(struct flash_bank_s *bank, int first, int last);
  88. int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last);
  89. int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  90. int lpc288x_probe(struct flash_bank_s *bank);
  91. int lpc288x_auto_probe(struct flash_bank_s *bank);
  92. int lpc288x_erase_check(struct flash_bank_s *bank);
  93. int lpc288x_protect_check(struct flash_bank_s *bank);
  94. int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  95. void lpc288x_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
  96. u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout);
  97. void lpc288x_load_timer(int erase, struct target_s *target);
  98. void lpc288x_set_flash_clk(struct flash_bank_s *bank);
  99. u32 lpc288x_system_ready(struct flash_bank_s *bank);
  100. int lpc288x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  101. flash_driver_t lpc288x_flash =
  102. {
  103. .name = "lpc288x",
  104. .register_commands = lpc288x_register_commands,
  105. .flash_bank_command = lpc288x_flash_bank_command,
  106. .erase = lpc288x_erase,
  107. .protect = lpc288x_protect,
  108. .write = lpc288x_write,
  109. .probe = lpc288x_probe,
  110. .auto_probe = lpc288x_probe,
  111. .erase_check = lpc288x_erase_check,
  112. .protect_check = lpc288x_protect_check,
  113. .info = lpc288x_info
  114. };
  115. int lpc288x_register_commands(struct command_context_s *cmd_ctx)
  116. {
  117. return ERROR_OK;
  118. }
  119. u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
  120. {
  121. u32 status;
  122. target_t *target = bank->target;
  123. do
  124. {
  125. usleep(1000);
  126. timeout--;
  127. target_read_u32(target, F_STAT, &status);
  128. }while (((status & FS_DONE) == 0) && timeout);
  129. if(timeout == 0)
  130. {
  131. LOG_DEBUG("Timedout!");
  132. return ERROR_FLASH_OPERATION_FAILED;
  133. }
  134. return ERROR_OK;
  135. }
  136. /* Read device id register and fill in driver info structure */
  137. int lpc288x_read_part_info(struct flash_bank_s *bank)
  138. {
  139. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  140. target_t *target = bank->target;
  141. u32 cidr;
  142. int i = 0;
  143. u32 offset;
  144. if (lpc288x_info->cidr == 0x0102100A)
  145. return ERROR_OK; /* already probed, multiple probes may cause memory leak, not allowed */
  146. /* Read and parse chip identification register */
  147. target_read_u32(target, DBGU_CIDR, &cidr);
  148. if (cidr != 0x0102100A)
  149. {
  150. LOG_WARNING("Cannot identify target as an LPC288X (%08X)",cidr);
  151. return ERROR_FLASH_OPERATION_FAILED;
  152. }
  153. lpc288x_info->cidr = cidr;
  154. lpc288x_info->sector_size_break = 0x000F0000;
  155. lpc288x_info->target_name = "LPC288x";
  156. /* setup the sector info... */
  157. offset = bank->base;
  158. bank->num_sectors = 23;
  159. bank->sectors = malloc(sizeof(flash_sector_t) * 23);
  160. for (i = 0; i < 15; i++)
  161. {
  162. bank->sectors[i].offset = offset;
  163. bank->sectors[i].size = 64 * 1024;
  164. offset += bank->sectors[i].size;
  165. bank->sectors[i].is_erased = -1;
  166. bank->sectors[i].is_protected = 1;
  167. }
  168. for (i = 15; i < 23; i++)
  169. {
  170. bank->sectors[i].offset = offset;
  171. bank->sectors[i].size = 8 * 1024;
  172. offset += bank->sectors[i].size;
  173. bank->sectors[i].is_erased = -1;
  174. bank->sectors[i].is_protected = 1;
  175. }
  176. return ERROR_OK;
  177. }
  178. int lpc288x_protect_check(struct flash_bank_s *bank)
  179. {
  180. return ERROR_OK;
  181. }
  182. /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
  183. int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  184. {
  185. lpc288x_flash_bank_t *lpc288x_info;
  186. if (argc < 6)
  187. {
  188. LOG_WARNING("incomplete flash_bank LPC288x configuration");
  189. return ERROR_FLASH_BANK_INVALID;
  190. }
  191. lpc288x_info = malloc(sizeof(lpc288x_flash_bank_t));
  192. bank->driver_priv = lpc288x_info;
  193. /* part wasn't probed for info yet */
  194. lpc288x_info->cidr = 0;
  195. lpc288x_info->cclk = strtoul(args[6], NULL, 0);
  196. return ERROR_OK;
  197. }
  198. /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
  199. * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
  200. * AHB = 12 MHz ?
  201. * 12000000/66000 = 182
  202. * CLK_DIV = 60 ? */
  203. void lpc288x_set_flash_clk(struct flash_bank_s *bank)
  204. {
  205. u32 clk_time;
  206. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  207. clk_time = (lpc288x_info->cclk / 66000) / 3;
  208. target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN);
  209. target_write_u32(bank->target, F_CLK_TIME, clk_time);
  210. }
  211. /* AHB tcyc (in ns) 83 ns
  212. * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
  213. * = 9412 (9500) (AN10548 9375)
  214. * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
  215. * = 23 (75) (AN10548 72 - is this wrong?)
  216. * TODO: Sort out timing calcs ;) */
  217. void lpc288x_load_timer(int erase, struct target_s *target)
  218. {
  219. if (erase == LOAD_TIMER_ERASE)
  220. {
  221. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
  222. }
  223. else
  224. {
  225. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
  226. }
  227. }
  228. u32 lpc288x_system_ready(struct flash_bank_s *bank)
  229. {
  230. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  231. if (lpc288x_info->cidr == 0)
  232. {
  233. return ERROR_FLASH_BANK_NOT_PROBED;
  234. }
  235. if (bank->target->state != TARGET_HALTED)
  236. {
  237. LOG_ERROR("Target not halted");
  238. return ERROR_TARGET_NOT_HALTED;
  239. }
  240. return ERROR_OK;
  241. }
  242. int lpc288x_erase_check(struct flash_bank_s *bank)
  243. {
  244. u32 status = lpc288x_system_ready(bank); /* probed? halted? */
  245. if (status != ERROR_OK)
  246. {
  247. LOG_INFO("Processor not halted/not probed");
  248. return status;
  249. }
  250. return ERROR_OK;
  251. }
  252. int lpc288x_erase(struct flash_bank_s *bank, int first, int last)
  253. {
  254. u32 status;
  255. int sector;
  256. target_t *target = bank->target;
  257. status = lpc288x_system_ready(bank); /* probed? halted? */
  258. if (status != ERROR_OK)
  259. {
  260. return status;
  261. }
  262. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  263. {
  264. LOG_INFO("Bad sector range");
  265. return ERROR_FLASH_SECTOR_INVALID;
  266. }
  267. /* Configure the flash controller timing */
  268. lpc288x_set_flash_clk(bank);
  269. for (sector = first; sector <= last; sector++)
  270. {
  271. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  272. {
  273. return ERROR_FLASH_OPERATION_FAILED;
  274. }
  275. lpc288x_load_timer(LOAD_TIMER_ERASE,target);
  276. target_write_u32(target, bank->sectors[sector].offset, 0x00);
  277. target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS);
  278. }
  279. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  280. {
  281. return ERROR_FLASH_OPERATION_FAILED;
  282. }
  283. return ERROR_OK;
  284. }
  285. int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
  286. {
  287. u8 page_buffer[FLASH_PAGE_SIZE];
  288. u32 i, status, source_offset,dest_offset;
  289. target_t *target = bank->target;
  290. u32 bytes_remaining = count;
  291. u32 first_sector, last_sector, sector, page;
  292. /* probed? halted? */
  293. status = lpc288x_system_ready(bank);
  294. if (status != ERROR_OK)
  295. {
  296. return status;
  297. }
  298. /* Initialise search indices */
  299. first_sector = last_sector = 0xffffffff;
  300. /* validate the write range... */
  301. for (i = 0; i < bank->num_sectors; i++)
  302. {
  303. if ((offset >= bank->sectors[i].offset) &&
  304. (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
  305. (first_sector == 0xffffffff))
  306. {
  307. first_sector = i;
  308. /* all writes must start on a sector boundary... */
  309. if (offset % bank->sectors[i].size)
  310. {
  311. LOG_INFO("offset 0x%x breaks required alignment 0x%x", offset, bank->sectors[i].size);
  312. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  313. }
  314. }
  315. if (((offset + count) > bank->sectors[i].offset) &&
  316. ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
  317. (last_sector == 0xffffffff))
  318. {
  319. last_sector = i;
  320. }
  321. }
  322. /* Range check... */
  323. if (first_sector == 0xffffffff || last_sector == 0xffffffff)
  324. {
  325. LOG_INFO("Range check failed %x %x", offset, count);
  326. return ERROR_FLASH_DST_OUT_OF_BANK;
  327. }
  328. /* Configure the flash controller timing */
  329. lpc288x_set_flash_clk(bank);
  330. /* initialise the offsets */
  331. source_offset = 0;
  332. dest_offset = 0;
  333. for (sector = first_sector; sector <= last_sector; sector++)
  334. {
  335. for (page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++)
  336. {
  337. if (bytes_remaining == 0)
  338. {
  339. count = 0;
  340. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  341. }
  342. else if (bytes_remaining < FLASH_PAGE_SIZE)
  343. {
  344. count = bytes_remaining;
  345. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  346. memcpy(page_buffer, &buffer[source_offset], count);
  347. }
  348. else
  349. {
  350. count = FLASH_PAGE_SIZE;
  351. memcpy(page_buffer, &buffer[source_offset], count);
  352. }
  353. /* Wait for flash to become ready */
  354. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  355. {
  356. return ERROR_FLASH_OPERATION_FAILED;
  357. }
  358. /* fill flash data latches with 1's */
  359. target_write_u32(target, F_CTRL, FC_CS | FC_SET_DATA | FC_WEN | FC_FUNC);
  360. target_write_u32(target, F_CTRL, FC_CS | FC_WEN | FC_FUNC);
  361. /*would be better to use the clean target_write_buffer() interface but
  362. * it seems not to be a LOT slower....
  363. * bulk_write_memory() is no quicker :(*/
  364. #if 1
  365. if (target->type->write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
  366. {
  367. LOG_ERROR("Write failed s %x p %x", sector, page);
  368. return ERROR_FLASH_OPERATION_FAILED;
  369. }
  370. #else
  371. if (target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE, page_buffer) != ERROR_OK)
  372. {
  373. LOG_INFO("Write to flash buffer failed");
  374. return ERROR_FLASH_OPERATION_FAILED;
  375. }
  376. #endif
  377. dest_offset += FLASH_PAGE_SIZE;
  378. source_offset += count;
  379. bytes_remaining -= count;
  380. lpc288x_load_timer(LOAD_TIMER_WRITE, target);
  381. target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC | FC_CS);
  382. }
  383. }
  384. return ERROR_OK;
  385. }
  386. int lpc288x_probe(struct flash_bank_s *bank)
  387. {
  388. /* we only deal with LPC2888 so flash config is fixed */
  389. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  390. int retval;
  391. if (lpc288x_info->cidr != 0)
  392. {
  393. return ERROR_OK; /* already probed */
  394. }
  395. if (bank->target->state != TARGET_HALTED)
  396. {
  397. LOG_ERROR("Target not halted");
  398. return ERROR_TARGET_NOT_HALTED;
  399. }
  400. retval = lpc288x_read_part_info(bank);
  401. if (retval != ERROR_OK)
  402. return retval;
  403. return ERROR_OK;
  404. }
  405. int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size)
  406. {
  407. snprintf(buf, buf_size, "lpc288x flash driver");
  408. return ERROR_OK;
  409. }
  410. int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last)
  411. {
  412. int lockregion, status;
  413. u32 value;
  414. target_t *target = bank->target;
  415. /* probed? halted? */
  416. status = lpc288x_system_ready(bank);
  417. if (status != ERROR_OK)
  418. {
  419. return status;
  420. }
  421. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  422. {
  423. return ERROR_FLASH_SECTOR_INVALID;
  424. }
  425. /* Configure the flash controller timing */
  426. lpc288x_set_flash_clk(bank);
  427. for (lockregion = first; lockregion <= last; lockregion++)
  428. {
  429. if (set)
  430. {
  431. /* write an odd value to base addy to protect... */
  432. value = 0x01;
  433. }
  434. else
  435. {
  436. /* write an even value to base addy to unprotect... */
  437. value = 0x00;
  438. }
  439. target_write_u32(target, bank->sectors[lockregion].offset, value);
  440. target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC | FC_CS);
  441. }
  442. return ERROR_OK;
  443. }