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  1. # Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
  2. # The board has separate JTAG ports for cpu and CPLD/FPGA devices
  3. # Chaining is done on IO interfaces if desired.
  4. source [find target/pxa270.cfg]
  5. # The board supports separate reset lines
  6. # Override this in the interface config for parallel dongles
  7. reset_config trst_and_srst separate
  8. # flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
  9. # 29LV650 64Mbit Flash
  10. set _FLASHNAME $_CHIPNAME.flash
  11. flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME